By Topic

# [1992] Proceedings The European Conference on Design Automation

## Filter Results

Displaying Results 1 - 25 of 94
• ### Proceedings. The European Conference on Design Automation (Cat. No.92TH0414-3)

Publication Year: 1992
| PDF (245 KB)
• ### MULTIPAR: behavioral partitioning for synthesizing application-specific multiprocessor architecture

Publication Year: 1992, Page(s):14 - 18
Cited by:  Papers (4)
| | PDF (468 KB)

The authors present methods for scheduling and partitioning behavioral descriptions in order to synthesize application specific multiprocessor systems. The target application domain is real-time digital signal processing (DSP). In order to meet the real-time constraints, maximizing the system throughput and minimizing the number of communications between processors are important. A model of the ta... View full abstract»

• ### Exploiting hierarchy in a cache-based switch-level simulator

Publication Year: 1992, Page(s):207 - 211
| | PDF (372 KB)

The article presents a caching method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory it is shown how the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables and significantl... View full abstract»

• ### Verification of self-checking properties by means of output code space computation

Publication Year: 1992, Page(s):169 - 174
Cited by:  Papers (2)
| | PDF (532 KB)

In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of ... View full abstract»

• ### Modeling data flow and control flow for high level memory management

Publication Year: 1992, Page(s):8 - 13
Cited by:  Papers (8)  |  Patents (1)
| | PDF (464 KB)

The goal of this paper is to advocate a control flow independent modeling of data flow in applicative algorithm specifications. The model is utilized in the synthesis of ASIC architectures for real-time signal processing applications. It allows for a generalization of control flow transformations which are used to optimize the memory organization at an early stage in the synthesis trajectory. Argu... View full abstract»

• ### An automatic layout generator for analog circuits

Publication Year: 1992, Page(s):513 - 519
Cited by:  Papers (16)  |  Patents (4)
| | PDF (580 KB)

A design by example' approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert's knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module's shape e.g. a d... View full abstract»

• ### A parallel switch-level simulator for mixed analog-digital circuit simulation

Publication Year: 1992, Page(s):202 - 206
| | PDF (300 KB)

Presents a parallel event-driven switch-level simulator intended for medium-grain multicomputers. The chosen parallel algorithm ensures that node voltages are always defined. This avoids problems with undefined node states and makes the simulator suitable for mixed analog-digital simulation. The active devices are modeled as piecewise-constant current sources, which gives high timing accuracy and ... View full abstract»

• ### Concatenable cellular automata register design for built-in self-test

Publication Year: 1992, Page(s):164 - 168
Cited by:  Papers (1)
| | PDF (364 KB)

The paper describes the principles of concatenations of cellular automata based LFSRs (MISR). It proves some theorems and lemmas which show if a certain cellular automata based register has a reducible polynomial of the form xg(x) or (x+l)h(x). Further it answers the question how to find a minimal set of standard CAD system cells to permit the construction of various length and various primitive c... View full abstract»

• ### System-level synthesis using re-programmable components

Publication Year: 1992, Page(s):2 - 7
Cited by:  Papers (76)  |  Patents (2)
| | PDF (608 KB)

The authors formulate the synthesis problem of complex behavioral descriptions with performance constraints as a hardware-software co-design problem. The target system architecture consists of a software component as a program running on a re-programmable processor assisted by application-specific hardware components. System synthesis is performed by first partitioning the input system description... View full abstract»

• ### Reduced RC models for IC interconnections with coupling capacitances

Publication Year: 1992, Page(s):132 - 136
Cited by:  Papers (8)  |  Patents (6)
| | PDF (268 KB)

The transmission behavior of interconnections in integrated circuits is often determined by their distributed RC effects. The authors present a modeling technique, for incorporation in a layout-to-circuit extraction program, that accurately represents these effects. The method consists of first replacing IC interconnections by a complex RC network and then transforming this complex RC network into... View full abstract»

• ### State assignment for general FSM networks

Publication Year: 1992, Page(s):245 - 249
Cited by:  Papers (3)
| | PDF (460 KB)

A theoretical formulation of state assignment for general finite state machine (FSM) networks is presented. The goal is to assign binary codes to individual machines so as to satisfy the maximum number of constraints generated from all the machines of the network simultaneously. Using an earlier formulation of a state assignment problem for a single FSM, the state assignment for a general FSM netw... View full abstract»

• ### Automatic jog insertion for 2D mask compaction: a global optimization perspective

Publication Year: 1992, Page(s):508 - 512
Cited by:  Papers (1)  |  Patents (3)
| | PDF (388 KB)

A novel approach is presented to global optimization in 2D symbolic layout compaction based on branch and bound' optimization, including automatic overconstraint resolution and jog insertion. The main characteristics are: an efficient generation in 2D of a nearly irredundant set of simple X and Y, diagonal and user constraints; incremental event-driven longest path calculation with positive cycle... View full abstract»

• ### Sizing of analogue circuits for small-signal gains

Publication Year: 1992, Page(s):469 - 473
Cited by:  Papers (1)
| | PDF (316 KB)

Efficient computational techniques are presented for the sizing of analogue circuits subject to small-signal gain specifications. Particular attention is given to the estimation and control of the effects of device mismatch View full abstract»

• ### A synthesis for testability technique for PLA-based finite state machines

Publication Year: 1992, Page(s):361 - 365
Cited by:  Papers (1)
| | PDF (452 KB)

Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test seq... View full abstract»

• ### A data flow graph exchange standard

Publication Year: 1992, Page(s):193 - 199
Cited by:  Papers (20)  |  Patents (1)
| | PDF (568 KB)

Presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project, ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a unique degree of freedom for time and area optimizati... View full abstract»

• ### Logic synthesis for arithmetic circuits using the Reed-Muller representation

Publication Year: 1992, Page(s):109 - 113
Cited by:  Papers (15)
| | PDF (392 KB)

A procedure for multi-level Reed-Muller minimization has been developed which introduces a Reed-Muller factored form, and uses algebraic algorithms for factorization, decomposition, resubstitution, collapsing, and extraction of common cubes and subexpressions. The procedure has been used to design some arithmetic circuits using a gate library containing a wide range of gates, and the resulting cir... View full abstract»

• ### Testing embedded single and multi-port RAMs using BIST and boundary scan

Publication Year: 1992, Page(s):159 - 163
Cited by:  Papers (1)  |  Patents (3)
| | PDF (468 KB)

The paper presents a general BIST scheme for the test of RAMs (single and multi-port) embedded in very complex ASICs. A simple BIST circuit driven by the IEEE standard for the boundary scan (BS) is shared by all the memories that are tested simultaneously. The area overhead is greatly compensated by the test development time reduction and the link with BS View full abstract»

• ### Efficient test set evaluation

Publication Year: 1992, Page(s):428 - 433
| | PDF (504 KB)

The fault coverage obtained by a set of test patterns is usually determined by expensive fault simulation. Even when using fault dropping techniques, fault simulation provides more information than actually needed. For each fault, the pattern is determined which detects this fault first. This is mainly redundant information if diagnosis is not required. One can dispense with this high resolution a... View full abstract»

• ### Heuristic approach to binate covering problem

Publication Year: 1992, Page(s):123 - 129
Cited by:  Papers (1)
| | PDF (480 KB)

Covering problem is a problem of extraction of a minimum cost subset from a given set that satisfies certain constraints expressed as a Boolean formula in conjunctive normal form. This problem is NP-hard, heuristic methods are thus of interest. The authors present two heuristic methods to finding a nearly minimal solution and compare them to each other. The authors derive the asymptotic complexity... View full abstract»

• ### Automatic synthesis of large Moore sequencers

Publication Year: 1992, Page(s):237 - 244
Cited by:  Papers (2)
| | PDF (624 KB)

The automatic synthesis of large Moore sequencers is performed on architectures whose novel features include the use of a ROM, a partitioned micro-sequencer on standard cells and a masking technique which restricts the computation of next state codes to significant bits. Extensive experiments have shown the efficiency of the approach in terms of both area and speed compared with a full standard ce... View full abstract»

• ### Specification and analysis of timing constraints in signal transition graphs

Publication Year: 1992, Page(s):302 - 306
Cited by:  Papers (31)  |  Patents (3)
| | PDF (304 KB)

The introduction of timing constraints in signal transition graphs (STG) is discussed. The possible interpretations of these timing constraints (called the firing semantics) is also discussed. During synthesis it is an important task to calculate the minimum and maximum distance in time between two transitions based on timing information present in the STG. A new recursive algorithm that calculate... View full abstract»

• ### Resources restricted aggressive scheduling

Publication Year: 1992, Page(s):501 - 506
Cited by:  Papers (1)
| | PDF (416 KB)

A scheduling methodology is described for high-level synthesis of designs with a significant amount of control structure. The objective is to utilize all the available resources while scheduling with respect to resource restriction. To do so, a vector/matrix structure is built which provides a global view of resource usage at each node. It supports the migration of operations across basic blocks t... View full abstract»

• ### DaDaMo-a conceptual data model for electronic design applications

Publication Year: 1992, Page(s):394 - 398
Cited by:  Papers (6)
| | PDF (400 KB)

DaDaMo is a conceptual data model for design applications requiring complex modelling techniques. By the integration and extension of semantic and object-oriented modelling concepts, DaDaMo provides modelling mechanisms considering especially the requirements of complex design applications. These mechanisms are described in detail and their adequacy in particular for electronic design applications... View full abstract»

• ### Analog behavioral models for simulation and synthesis of mixed-signal systems

Publication Year: 1992, Page(s):464 - 468
Cited by:  Papers (6)  |  Patents (1)
| | PDF (344 KB)

A behavioral simulator is shown to be an essential part of a performance-driven hierarchical top-down design strategy for analog blocks within mixed-signal integrated systems. It is used to accurately estimate the performance of the system while down-mapping the specifications over the hierarchy, in order to avoid time-consuming design iterations. It is also indispensable for the final bottom-up v... View full abstract»

• ### Derivation of high quality tests for large heterogeneous circuits: floating-point operations

Publication Year: 1992, Page(s):355 - 360
Cited by:  Papers (4)
| | PDF (464 KB)

The problem of deriving high quality tests for fast combinational floating-point realizations is investigated. Floating-point circuits are heterogeneous, consisting of a large number of regular and irregular modules. Thus, the test strategy applied combines specialized structure based methods and universal test generation. In order to guarantee sufficient controllability and observability of embed... View full abstract»