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Design Automation, 1992. Proceedings., [3rd] European Conference on

Date 16-19 March 1992

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Displaying Results 1 - 25 of 94
  • Proceedings. The European Conference on Design Automation (Cat. No.92TH0414-3)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (245 KB)
    Freely Available from IEEE
  • Functional testing of modern microprocessors

    Publication Year: 1992, Page(s):350 - 354
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In the early 1980s, a method was developed for functional testing of microprocessors. Modern microprocessors have a functionality, such as on-chip caches, which is not covered by that model. This paper extends that functional model and proposes fault models, together with tests for such modern microprocessors. The proposed concepts and algorithms have been applied to the Intel i860 microprocessor ... View full abstract»

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  • Scheduling between basic blocks in the CADDY synthesis system

    Publication Year: 1992, Page(s):496 - 500
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In `high level' IC synthesis, basic blocks are caused by the control schemes and the block structure of the specification language (branches, loops). These schemes must be considered by the construction of the controller. A method is presented to handle the basic blocks in a more flexible way which allows one to move operations between basic block boundaries. The goal is to improve the number of c... View full abstract»

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  • TELE: a timing evaluator using layout estimation for high level applications

    Publication Year: 1992, Page(s):137 - 141
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    The authors address the problem of early accurate timing prediction of VLSI layouts, prior to any physical design tasks. The authors present an approach based on two models, analytical and constructive. This approach permits the user to trade off the accuracy of the prediction versus the runtime of the predictor. Such a scheme is quite useful for high level design tasks such as high-level synthesi... View full abstract»

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  • A synthesis for testability technique for PLA-based finite state machines

    Publication Year: 1992, Page(s):361 - 365
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test seq... View full abstract»

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  • Analog behavioral models for simulation and synthesis of mixed-signal systems

    Publication Year: 1992, Page(s):464 - 468
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A behavioral simulator is shown to be an essential part of a performance-driven hierarchical top-down design strategy for analog blocks within mixed-signal integrated systems. It is used to accurately estimate the performance of the system while down-mapping the specifications over the hierarchy, in order to avoid time-consuming design iterations. It is also indispensable for the final bottom-up v... View full abstract»

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  • Testing analog circuits by sensitivity computation

    Publication Year: 1992, Page(s):532 - 537
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    An approach is presented for fault diagnosis, at component level of analog circuits, by using functional testing. It is based on the determination of the deviation of one or many components with respect to the value fixed by the designer. Components deviation is determined by measuring a number of output parameters and by sensitivity estimation. A solution of the test equations, based on the sensi... View full abstract»

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  • Global weighted scheduling and allocation algorithms

    Publication Year: 1992, Page(s):491 - 495
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Scheduling and allocation are very complex problems in a high-level synthesis system. It was proven, in related work, that the two are NP-complete optimization problems. The authors introduce a new global approach for scheduling and allocation. The approach uses graphs to formulate the two problems and applies a partitioning procedure on these graphs to find the minimal number of cliques. The obta... View full abstract»

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  • Partial strength ordering applied to symbolic switch-level analysis

    Publication Year: 1992, Page(s):388 - 392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Presents the application of partially ordered strength sets within the symbolic switch-level analysis of digital MOS circuits, where until now only a straightforward approach using a total ordering was used. The paper gives a mathematical formulation for the analysis. The method has been implemented within the existing switch-level analyzer ANAMOS, and has been applied successfully to practical ci... View full abstract»

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  • Efficient verification of sequential circuits on a parallel system

    Publication Year: 1992, Page(s):64 - 68
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The paper presents a method to verify functional correctness of FSMs on a parallel system. The equivalence condition is expressed in theoretical terms within the framework of the product machine. It consists in proving that a set of states of the product machine is unreachable from the initial reset state. The algorithm is based on state-of-the-art simulation techniques for explicit enumeration on... View full abstract»

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  • Synthesis of sequential circuits for parallel scan

    Publication Year: 1992, Page(s):366 - 370
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Sequential circuit testing is known to be a difficult problem. The authors present a synthesis for testability (SFT) method to solve this problem. In this approach, some testability features analogous to the traditional scan design are added to the normal logic equations which define the finite state machine (FSM). The augmented FSM is then synthesized with these added features built in. The overh... View full abstract»

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  • Derivation of high quality tests for large heterogeneous circuits: floating-point operations

    Publication Year: 1992, Page(s):355 - 360
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The problem of deriving high quality tests for fast combinational floating-point realizations is investigated. Floating-point circuits are heterogeneous, consisting of a large number of regular and irregular modules. Thus, the test strategy applied combines specialized structure based methods and universal test generation. In order to guarantee sufficient controllability and observability of embed... View full abstract»

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  • Advanced ordering and manipulation techniques for binary decision diagrams

    Publication Year: 1992, Page(s):452 - 457
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced as well, which accelerates commonly used operation... View full abstract»

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  • Resources restricted aggressive scheduling

    Publication Year: 1992, Page(s):501 - 506
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A scheduling methodology is described for high-level synthesis of designs with a significant amount of control structure. The objective is to utilize all the available resources while scheduling with respect to resource restriction. To do so, a vector/matrix structure is built which provides a global view of resource usage at each node. It supports the migration of operations across basic blocks t... View full abstract»

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  • Formalized timing diagrams

    Publication Year: 1992, Page(s):372 - 377
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Traditionally, the timing behavior of digital circuits has been described using timing or waveform diagrams. These diagrams concisely represent the shape of the waveforms that are observed at the interface of a circuit and the temporal relationships between their edges. Timing information takes two principal forms: propagation delays that abstract the internal implementation of the circuit and tim... View full abstract»

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  • Intelligent VLSI design object management

    Publication Year: 1992, Page(s):410 - 414
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    Designing a VLSI chip is almost always an iterative process and a group effort. As a result, proliferation of design versions, becomes one of the most important issues in the development of design automation systems. The authors present the design and implementation of a VLSI object management system that supports several novel low-level storage management and access control services not found in ... View full abstract»

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  • A structural optimization method for symbolic FSMs

    Publication Year: 1992, Page(s):232 - 236
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The paper presents a new structural optimization method for symbolic finite state machines. It is based on the common use of outputs for generating both the next state and the output vectors. An upper bound on the number of shared outputs is given as well as the algorithm giving the best solution View full abstract»

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  • YOR: a yield optimizing routing algorithm by minimizing critical area and vias

    Publication Year: 1992, Page(s):525 - 529
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The goal of a channel routing algorithm is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. A new channel routing algorithm is presented to deal with this problem. The approach is to sys... View full abstract»

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  • Space-efficient extraction algorithms

    Publication Year: 1992, Page(s):520 - 524
    Cited by:  Papers (4)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A description is given of how the authors limited the space complexity of a layout to circuit extractor by: a combination of the scanline technique with the corner stitching technique; a region-based extraction algorithm; a judicious choice of netlist format; and a union-find data structure also supporting deletions of elements. The efficiency of the new algorithms and the resulting extractor is c... View full abstract»

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  • Transfer free register allocation in cyclic data flow graphs

    Publication Year: 1992, Page(s):181 - 185
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Discusses an algorithm for the optimal register allocation problem in cyclic data flow graphs. Cyclic data flow graphs result from high level behavioral descriptions that contain loops. Algorithms published up till now did not consider cyclic data flow graphs specifically. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations may be introduced. ... View full abstract»

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  • Functional abstraction and formal proof of digital circuits

    Publication Year: 1992, Page(s):458 - 462
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second... View full abstract»

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  • Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs?

    Publication Year: 1992, Page(s):538 - 542
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Investigations are made into the suitability of supply current monitoring as a technique for the testing of analogue circuit modules. Iddq monitoring is already recognised in the digital field. The possibility of a unified testing approach for mixed ASICs is raised. The potential effectiveness of the method is investigated. Simulation results are reported to illustrate typical supply current level... View full abstract»

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  • Verification of self-checking properties by means of output code space computation

    Publication Year: 1992, Page(s):169 - 174
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of ... View full abstract»

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  • An error decoder for the Compact Disc player as an example of VLSI programming

    Publication Year: 1992, Page(s):69 - 74
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is nee... View full abstract»

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  • Principles of design methodology management for electronic CAD frameworks

    Publication Year: 1992, Page(s):25 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The author introduces a set of design methodology management (DMM) modeling principles as applied to VLSI design environments consisting of CAD tools that were not purposely developed so as to be included into design flows and then do not conform to any specific procedural interface. In the author's view DMM services have two major goals: to discipline designers' behavior and to automate the run o... View full abstract»

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