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# [1992] Proceedings The European Conference on Design Automation

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Displaying Results 1 - 25 of 94
• ### Proceedings. The European Conference on Design Automation (Cat. No.92TH0414-3)

Publication Year: 1992
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• ### Automatic synthesis of large Moore sequencers

Publication Year: 1992, Page(s):237 - 244
Cited by:  Papers (2)
| | PDF (624 KB)

The automatic synthesis of large Moore sequencers is performed on architectures whose novel features include the use of a ROM, a partitioned micro-sequencer on standard cells and a masking technique which restricts the computation of next state codes to significant bits. Extensive experiments have shown the efficiency of the approach in terms of both area and speed compared with a full standard ce... View full abstract»

• ### Automatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by the SFG-tracing methodology

Publication Year: 1992, Page(s):54 - 58
Cited by:  Papers (5)
| | PDF (524 KB)

Research on the verification of synchronous circuits has been focussed recently on alternative methodologies instead of traditional methods like ad-hoc simulation. Where logic simulation can not avoid the combinatorial explosion that would normally occur when evaluating circuits for each possible input and initial state, new methods such as theorem proving, tautology checking and symbolic simulati... View full abstract»

• ### Functional decomposition for universal logic cells using substitution

Publication Year: 1992, Page(s):38 - 42
Cited by:  Papers (4)
| | PDF (392 KB)

Known synthesis tools with a strong relationship to a library of gates lead to poor results for target architectures based on universal logic cells as basic elements. The authors present an algorithm which uses function substitution in-order to minimize the costs of the decomposed function. Experimental results show an high degree of improvement over other existing synthesis programs View full abstract»

• ### An asynchronous architecture model for behavioral synthesis

Publication Year: 1992, Page(s):307 - 311
Cited by:  Papers (11)
| | PDF (396 KB)

An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by self-timed modules. Signal transition graphs (STGs) are used to specify the behavior of the control processes. By using existing synthesis procedures for STGs, circuits based on the p... View full abstract»

• ### Flow-a concurrent methodology manager

Publication Year: 1992, Page(s):20 - 24
Cited by:  Papers (2)
| | PDF (408 KB)

The Flow system is used to define methodology for ULSI design tasks in a formal way. It provides a concurrent environment in which such tasks are carried out automatically. The automatic execution of tasks in the Flow system utilize a set of workstations as computing resources. This paper describes the motivation for the development of Flow, the semantics used for methodology definition and the Fl... View full abstract»

• ### Functional testing of modern microprocessors

Publication Year: 1992, Page(s):350 - 354
Cited by:  Papers (2)
| | PDF (428 KB)

In the early 1980s, a method was developed for functional testing of microprocessors. Modern microprocessors have a functionality, such as on-chip caches, which is not covered by that model. This paper extends that functional model and proposes fault models, together with tests for such modern microprocessors. The proposed concepts and algorithms have been applied to the Intel i860 microprocessor ... View full abstract»

• ### Functional abstraction and formal proof of digital circuits

Publication Year: 1992, Page(s):458 - 462
Cited by:  Papers (3)  |  Patents (3)
| | PDF (432 KB)

A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second... View full abstract»

• ### A structural optimization method for symbolic FSMs

Publication Year: 1992, Page(s):232 - 236
Cited by:  Patents (1)
| | PDF (332 KB)

The paper presents a new structural optimization method for symbolic finite state machines. It is based on the common use of outputs for generating both the next state and the output vectors. An upper bound on the number of shared outputs is given as well as the algorithm giving the best solution View full abstract»

• ### Heuristics for computing robust tests for stuck-open faults from stuck-at test sets

Publication Year: 1992, Page(s):416 - 420
| | PDF (324 KB)

Heuristics for identifying stuck-open faults for which a robust test can be computed from any stuck-at-test set are presented. Experimental results show that these heuristics can be used to compute robust tests for a large percentage of stuck-upon faults. Since stuck-at test generation is considerably faster than computing a robust test-pair for a given stuck-open fault, these heuristics can be us... View full abstract»

• ### Rule-based analog circuit design

Publication Year: 1992, Page(s):480 - 484
Cited by:  Papers (4)
| | PDF (296 KB)

A prototype of a rule-based environment for analog integrated circuit design is presented. It features a hierarchical design style, multifunctionality and adaption capability for its knowledge bases. The prototype called AC/DC has been realized as a set of cooperating tools for design and verification. The overall system can act like an automatic tool as well as a design assistant. In its current ... View full abstract»

• ### Automatic jog insertion for 2D mask compaction: a global optimization perspective

Publication Year: 1992, Page(s):508 - 512
Cited by:  Papers (1)  |  Patents (3)
| | PDF (388 KB)

A novel approach is presented to global optimization in 2D symbolic layout compaction based on branch and bound' optimization, including automatic overconstraint resolution and jog insertion. The main characteristics are: an efficient generation in 2D of a nearly irredundant set of simple X and Y, diagonal and user constraints; incremental event-driven longest path calculation with positive cycle... View full abstract»

• ### The Sprite Input Language-an intermediate format for high level synthesis

Publication Year: 1992, Page(s):186 - 192
Cited by:  Papers (14)
| | PDF (496 KB)

Describes a simple and powerful input language (intermediate format) for high level synthesis. The language belongs to the class of signalflow graphs. The Sprite Input Language (SIL) encompasses both the applicative constructs on which classical DSP languages like Silage are based, the functional constructs from hardware description languages like ELLA, and the operational constructs from sequenti... View full abstract»

• ### Input driven synthesis of PLDs and PGAs

Publication Year: 1992, Page(s):48 - 52
Cited by:  Papers (8)
| | PDF (388 KB)

The paper presents a fast and efficient algorithm for synthesis of Boolean functions on Xilinx and PAL devices. It starts from lexicographical factorized trees and performs a partitioning of these aces defined by input slices'. This allows the creation of subfunctions depending on identical subsets of inputs which can then be easily clustered into the same physical device. Results are shown for a... View full abstract»

• ### Controlling cooperation through design-object specification-a database-oriented approach

Publication Year: 1992, Page(s):30 - 35
Cited by:  Papers (1)
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The authors propose an operational framework for supporting cooperative design processes carried out by a group of designers. Besides the cooperative refinement of the design-object specification, the introduced cooperation protocol allows cooperative design by system-controlled interchange of design object versions. The versions reflect the process of step-wise improving the design object so as t... View full abstract»

• ### A synthesis for testability technique for PLA-based finite state machines

Publication Year: 1992, Page(s):361 - 365
Cited by:  Papers (1)
| | PDF (452 KB)

Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test seq... View full abstract»

• ### Formalized timing diagrams

Publication Year: 1992, Page(s):372 - 377
Cited by:  Papers (10)  |  Patents (1)
| | PDF (528 KB)

Traditionally, the timing behavior of digital circuits has been described using timing or waveform diagrams. These diagrams concisely represent the shape of the waveforms that are observed at the interface of a circuit and the temporal relationships between their edges. Timing information takes two principal forms: propagation delays that abstract the internal implementation of the circuit and tim... View full abstract»

• ### Specification and analysis of timing constraints in signal transition graphs

Publication Year: 1992, Page(s):302 - 306
Cited by:  Papers (31)  |  Patents (3)
| | PDF (304 KB)

The introduction of timing constraints in signal transition graphs (STG) is discussed. The possible interpretations of these timing constraints (called the firing semantics) is also discussed. During synthesis it is an important task to calculate the minimum and maximum distance in time between two transitions based on timing information present in the STG. A new recursive algorithm that calculate... View full abstract»

• ### The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits

Publication Year: 1992, Page(s):549 - 553
Cited by:  Papers (1)
| | PDF (364 KB)

Due to the presence of multiple paths to charge or discharge the output node of a BiCMOS logic gate, many of the realistic open and short faults appear as rise or fall time delay faults without changing the functionality of the circuit. Based on circuit level faults, it has been observed that delay fault tests can produce a fault coverage as high as 92% compared to 29% produced by stuck-at tests, ... View full abstract»

• ### Signature analysis under a delay fault model

Publication Year: 1992, Page(s):285 - 290
Cited by:  Papers (3)
| | PDF (428 KB)

A framework for aliasing under a delay fault model is presented. First, error patterns under this fault model are characterized. Through this, specific error patterns that can occur are identified. Based on this, it is shown that using a model similar to the equiprobable model, the aliasing probability under certain conditions converges to 2-m for delay faults as well. A closed form ex... View full abstract»

• ### Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs?

Publication Year: 1992, Page(s):538 - 542
Cited by:  Papers (12)
| | PDF (332 KB)

Investigations are made into the suitability of supply current monitoring as a technique for the testing of analogue circuit modules. Iddq monitoring is already recognised in the digital field. The possibility of a unified testing approach for mixed ASICs is raised. The potential effectiveness of the method is investigated. Simulation results are reported to illustrate typical supply current level... View full abstract»

• ### MULTIPAR: behavioral partitioning for synthesizing application-specific multiprocessor architecture

Publication Year: 1992, Page(s):14 - 18
Cited by:  Papers (4)
| | PDF (468 KB)

The authors present methods for scheduling and partitioning behavioral descriptions in order to synthesize application specific multiprocessor systems. The target application domain is real-time digital signal processing (DSP). In order to meet the real-time constraints, maximizing the system throughput and minimizing the number of communications between processors are important. A model of the ta... View full abstract»

• ### An alternative to fault simulation for delay-fault diagnosis

Publication Year: 1992, Page(s):274 - 279
Cited by:  Papers (7)
| | PDF (488 KB)

Delay testing is a test procedure to verify the timing performance of manufactured digital circuits. A diagnosis process is often implemented after the detection of a fault in a circuit. Unfortunately, existing methodologies for locating delay defects on digital circuits have shown certain deficiencies. A new method for delay fault diagnosis, based on critical path tracing from a symbolic simulati... View full abstract»

• ### A clock net routing algorithm for high performance VLSI

Publication Year: 1992, Page(s):343 - 347
Cited by:  Papers (1)  |  Patents (6)
| | PDF (428 KB)

Presents a new algorithm, called FSTM (`feasible segment tree method'), for the clock net routing of high performance VLSI designs. To avoid the clock skew, FSTM constructs a binary tree such that for each internal vertex of the tree, the cardinality of its sub-trees are balanced and the distances to its children are equal. The authors evaluate their results in terms of wire length and delay time ... View full abstract»

• ### Advanced ordering and manipulation techniques for binary decision diagrams

Publication Year: 1992, Page(s):452 - 457
Cited by:  Papers (7)  |  Patents (1)
| | PDF (500 KB)

Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced as well, which accelerates commonly used operation... View full abstract»