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Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on

Date 23-25 May 1995

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  • Proceedings 25th International Symposium on Multiple-Valued Logic

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (414 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Join-irreducible clones of multiple valued logic algebra

    Publication Year: 1995, Page(s):194 - 199
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    We study a problem of representation for the lattice of clones of multiple valued logic (MVL) functions. It is a problem of description of a generating system of clones, from which the whole lattice, or a given sublattice, can be reconstructed by synthesis. Here, the “synthetic means” considered is the join operation (V) for lattice elements. The generating set of clones is defined to ... View full abstract»

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  • Reed-Muller forms for incompletely specified functions via sparse polynomial interpolation

    Publication Year: 1995, Page(s):36 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    In this paper we investigate the possibility of exploiting incompletely specified functions for the purpose of minimizing Reed-Muller (RM) forms. All the previous work in this area has been based on exhaustive search for the optimal solution, or on some approximations to it. Here we show that an alternative approach can bring better results: the definition of the MVL RM transforms as a polynomial ... View full abstract»

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  • On logic of paradox

    Publication Year: 1995, Page(s):248 - 253
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    G. Priest introduced nonmonotonicity into a paraconsistent logic, so-called logic of paradox LP, that yields a solution to the weakness of paraconsistent logic. The resulting logic (of minimal parades) LPm is nonmonotonic in the sense that inconsistency is minimal. The problem of proof theory of logic LPm left open because the base logic LP is paraconsistent so that syntacti... View full abstract»

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  • On designing of 4-valued memory with double-gate TFT

    Publication Year: 1995, Page(s):187 - 192
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    We propose and analyze a new 4 valued memory cell by using the double gate thin film transistor (TFT). First, the structure of the double gate TFT is introduced. An equivalent circuit of the double gate TFT is proposed for the HSPICE simulation. Two circuits which are composed of the resistor load and the CMOS load basic block circuit are proposed and analyzed. The simulation results by using a la... View full abstract»

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  • Planar multiple-valued decision diagrams

    Publication Year: 1995, Page(s):28 - 35
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to bin... View full abstract»

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  • Wire-free computing circuits using optical wave-casting

    Publication Year: 1995, Page(s):8 - 13
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper presents wire-free computing circuits using optical wave-casting to provide a solution to the interconnection problems in parallel processing. The “wave-casting” implies wire-free communication scheme, where intensity-modulated optical signals are employed as information carriers and their frequencies represent the information in the system. In wavecasting-based parallel pro... View full abstract»

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  • Random pattern fault simulation in multi-valued circuits

    Publication Year: 1995, Page(s):98 - 103
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We present a fault simulator for Multi-Valued Logic Networks (MVLN). With this tool we investigate their Random Pattern Testability (RPT). We show for a restricted class of multi-valued circuits that the RPT is better than for two-valued circuits. We point out the relation between redundancies in two- and multi-valued logic networks. Moreover we show that the role of fault simulation for MVLNs is ... View full abstract»

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  • Uniqueness of partially specified multiple-valued Kleenean function

    Publication Year: 1995, Page(s):242 - 247
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A multiple-valued Kleenean function is a mapping fk:[0,1]n→[0,1], which is representable by a logic formula consisting n variables, three logical connectives, and any constant value of [0,1]. In this paper, some properties of the partially specified multiple-valued Kleenean functions by a subset A of [0,1] are investigated and the identification problem of logic formula ... View full abstract»

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  • A fuzzy membership function circuit using hysteretic resonant tunneling diodes

    Publication Year: 1995, Page(s):182 - 186
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The use of novel resonant tunneling devices in fuzzy logic hardware has been demonstrated previously (H. Tang, H.C. Lin, 1994). The results have shown great improvement in speed and reduced circuit complexity. However, one major problem associated with these resonant tunneling diodes (RTDs) is the hysteretic effect which in some applications may deteriorate circuit performance considerably. The pa... View full abstract»

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  • Some new results for multiple-valued genetic algorithms

    Publication Year: 1995, Page(s):264 - 269
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The paper describes each of the operations involved in a genetic algorithm: reproduction, mutation, and selection, and discusses each in the language of classical multiple-valued logic. The differences among forms of reproduction that have been used by various researchers are examined and the relative importance of each of the operations in searching for highly fit members of a population is evalu... View full abstract»

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  • Design of a highly parallel multiple-valued linear digital system for k-ary operations based on extended representation matrices

    Publication Year: 1995, Page(s):20 - 25
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Design of highly parallel multiple-valued circuits for k-ary operations with minimum critical path delay is discussed. The linear circuit for a k-ary operation can be designed by superposition of k unary operations. The code assignment of the symbols must be consistent in all the unary operations. Moreover, a set of the sparse representation matrices must be found to make the circuit parallel. In ... View full abstract»

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  • Three-valued constructive logic and logic programs

    Publication Year: 1995, Page(s):276 - 281
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    We propose three valued constructive logic with strong negation 3N by describing both proof and model theory. We relate the proposed three valued system to J. Lukasiewicz's (1920) three valued logic. We demonstrate that 3N is very useful to formalize a semantics for logic programs with negation as failure within the framework of constructive logic. We introduce the concept of N completion to provi... View full abstract»

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  • Multiple-valued logic design using multiple-valued EXOR

    Publication Year: 1995, Page(s):290 - 294
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    An approach to logic minimization using a new sum operation called multiple valued EXOR is proposed. The paper introduces the multiple valued sum of products expression using the EXOR. As the scheme of the minimization, we utilize an idea based on neural computing. First, we demonstrate the method to minimize the binary EXOR of MINs expressions and show that the method is effective. Next, we apply... View full abstract»

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  • A high-speed interconnect network using ternary logic

    Publication Year: 1995, Page(s):2 - 7
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper describes the design and implementation of a high-speed interconnect network (ICN) for a multiprocessor system using ternary logic. By using ternary logic and a fast point-to-point communication technique called STARI (Self-Timed At Receiver's Input), the communication between the processors is free of clock skew and insensitive to any delay differences in buffers and wires. In addition... View full abstract»

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  • Multiple-valued arithmetic integrated circuits based on 1.5 V-supply dual-rail source-coupled logic

    Publication Year: 1995, Page(s):64 - 69
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper presents a new multiple-valued current-mode MOS integrated circuit for high-speed arithmetic systems with a low supply voltage. The use of a multiple-valued source-coupled logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the switching delay of the circuit can be reduced at a low supply voltage. As an applicatio... View full abstract»

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  • Quantum device model based super pass gate for multiple-valued digital systems

    Publication Year: 1995, Page(s):92 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The investigation of the device functions required from the systems point of view is important for the development of the next generation of VLSI devices and systems. A super pass transistor (SPT) model is presented as a quantum device candidate for future multiple-valued VLSI systems. Since it has the powerful capability of multiple-signal-level detection, the SPT will be useful for implementing ... View full abstract»

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  • Resonant tunneling transistor and its application to multiple-valued logic circuits

    Publication Year: 1995, Page(s):130 - 138
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Progress in multiple-valued logic (MVL) depends much on the development of devices that are inherently suitable for MVL operation. With their multiple stable states, resonant tunneling devices are promising candidates. Although not at a matured stage yet, resonant tunneling transistors (RTTs) and diodes (RTDs) are expected to be indispensable for practical applications of MVL in the near future. I... View full abstract»

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  • A characterization of Kleenean functions

    Publication Year: 1995, Page(s):236 - 241
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The paper deals with Kleenean sanctions defined as fuzzy logic functions with constants. Kleenean functions provide a means of handling conditions of indeterminate truth value (ambiguous states) which ordinary classical logic (binary logic) cannot cope with. The paper clarifies a necessary and sufficient condition for a function to be a Kleenean function. The condition is provided with a set of tw... View full abstract»

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  • The high speed ternary logic gates based on the multiple β transistors

    Publication Year: 1995, Page(s):178 - 181
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The paper develops a kind of multiple β transistor based on the multiple emitter transistor whose emitter has different current gain β. It then presents the design of the linear AND/OR gates and multi valued literal circuits. These two kinds of circuits have not only simple structures but also very high operating speeds so that they can be utilized to the design of the high speed multi v... View full abstract»

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  • Finitary approximations and metric structure of the space of clones

    Publication Year: 1995, Page(s):200 - 205
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Let Ok denote the set of all multivariable functions over Ek into Ek where Ek is a k element set (k⩾2). A clone over Ek is a subset of Ok which is closed under composition. The set Lk of all clones over Ek is called the clone space. The structure of L2 is completely known since E.L. Post (1941),... View full abstract»

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  • Properties of the Zhang-Watari transform

    Publication Year: 1995, Page(s):44 - 49
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The relationship between the 2D multiple-valued (complex-valued) Haar transform and the 2D real valued Zhang-Watari transform of patterns is studied and a method is disclosed to compute the Haar-(more properly, Watari)-spectrum of a pattern by using only real arithmetic. It is shown that to extend the straight forward 1D results to the 2D case, a special permutation operation has to be introduced.... View full abstract»

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  • Decomposition of multiple-valued functions

    Publication Year: 1995, Page(s):256 - 261
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    This paper presents a generalized method for decomposition of multiple-valued functions. The main reason for using the described method is efficient implementation of logic circuits as well as effective representation of data in information systems. In logic synthesis, the method reduces the demand for silicon space required to implement designs. It is shown that the decomposition technique leads ... View full abstract»

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  • Redundant complex number systems

    Publication Year: 1995, Page(s):14 - 19
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    This paper presents redundant complex number systems (RCNSs)-new complex number representations for high-speed arithmetic circuits. RCNS is a positional number system that has a complex radix rj and a digit set {-α,…,0,…,α}, where r⩾2 and [(r2 -1)/2]⩽α⩽r2-1. The use of complex radix rj allows additions and multiplications of complex... View full abstract»

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