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Proceedings 25th International Symposium on Multiple-Valued Logic

23-25 May 1995

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  • Proceedings 25th International Symposium on Multiple-Valued Logic

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (414 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (60 KB)
    Freely Available from IEEE
  • On input permutation technique for multiple-valued logic synthesis

    Publication Year: 1995, Page(s):170 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    An input permutation technique with respect to multiple valued logic synthesis is introduced. First, it is applied to multiple valued sum of products expressions where sum refers to TSUM. Some upper bounds are clarified on the number of implicants in minimal sum of products expressions for one variable and two variable functions with permuted logic values. An experiment was done on randomly genera... View full abstract»

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  • Factorization of multi-valued logic functions

    Publication Year: 1995, Page(s):164 - 169
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The paper describes an approach to factorization of multi valued logic (MVL) functions. The key concept is to formulate the problem as a rectangular covering problem. First, we develop an MVL algebraic factorization algorithm. Then, by incorporating two MVL Boolean properties: “identical” and “complementary”, we further improve the purely algebraic factorization algorithm t... View full abstract»

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  • Efficient algorithm for the generation of fixed polarity quaternary Reed-Muller expansions

    Publication Year: 1995, Page(s):158 - 163
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    An efficient algorithm for the generation of fixed polarity Reed-Muller expansions over Galois field GF(4) has been introduced. The polarity coefficient matrices of quaternary switching functions in Reed-Muller expansions are generated by means of recursive square matrices. The number of required addition and multiplication operations has been found advantageous in comparison to the known D.H. Gre... View full abstract»

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  • Finitary approximations and metric structure of the space of clones

    Publication Year: 1995, Page(s):200 - 205
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Let Ok denote the set of all multivariable functions over Ek into Ek where Ek is a k element set (k⩾2). A clone over Ek is a subset of Ok which is closed under composition. The set Lk of all clones over Ek is called the clone space. The structure of L2 is completely known since E.L. Post (1941),... View full abstract»

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  • The evaluation of full sensitivity for test generation in MVL circuits

    Publication Year: 1995, Page(s):104 - 109
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The evaluation of a method for test generation for MVL circuits, based on the notion of full sensitivity, is given. The estimation is made on the functional level, by establishing a lower bound on the number of m-valued n-variable functions that are fully sensitive to all their variables. It is shown, that for practical values of m and n, the fraction of functions not fully sensitive to all their ... View full abstract»

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  • Segment matrix vector quantization and fuzzy logic for isolated-word speech recognition

    Publication Year: 1995, Page(s):152 - 156
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A novel speech recognition approach using segment matrix vector quantization (SMVQ) and fuzzy logic recognizer (FLR) is presented. SMVQ incorporates time sequence information and segment characteristics of speech signals. Firstly, the feature vector sequences of the speech signal is nonlinearly normalized to M frames. Secondly, the sequence is divided into N equal length segments. Finally, VQ is c... View full abstract»

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  • Three-valued constructive logic and logic programs

    Publication Year: 1995, Page(s):276 - 281
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    We propose three valued constructive logic with strong negation 3N by describing both proof and model theory. We relate the proposed three valued system to J. Lukasiewicz's (1920) three valued logic. We demonstrate that 3N is very useful to formalize a semantics for logic programs with negation as failure within the framework of constructive logic. We introduce the concept of N completion to provi... View full abstract»

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  • Reed-Muller forms for incompletely specified functions via sparse polynomial interpolation

    Publication Year: 1995, Page(s):36 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    In this paper we investigate the possibility of exploiting incompletely specified functions for the purpose of minimizing Reed-Muller (RM) forms. All the previous work in this area has been based on exhaustive search for the optimal solution, or on some approximations to it. Here we show that an alternative approach can bring better results: the definition of the MVL RM transforms as a polynomial ... View full abstract»

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  • Join-irreducible clones of multiple valued logic algebra

    Publication Year: 1995, Page(s):194 - 199
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    We study a problem of representation for the lattice of clones of multiple valued logic (MVL) functions. It is a problem of description of a generating system of clones, from which the whole lattice, or a given sublattice, can be reconstructed by synthesis. Here, the “synthetic means” considered is the join operation (V) for lattice elements. The generating set of clones is defined to ... View full abstract»

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  • Random pattern fault simulation in multi-valued circuits

    Publication Year: 1995, Page(s):98 - 103
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We present a fault simulator for Multi-Valued Logic Networks (MVLN). With this tool we investigate their Random Pattern Testability (RPT). We show for a restricted class of multi-valued circuits that the RPT is better than for two-valued circuits. We point out the relation between redundancies in two- and multi-valued logic networks. Moreover we show that the role of fault simulation for MVLNs is ... View full abstract»

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  • Novel quantized transform for ternary systems

    Publication Year: 1995, Page(s):117 - 122
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A nonlinear quantized transform, called the “sign transform”, has been introduced. Besides being unique, and converting binary/ternary data into the ternary spectral domain, forward and inverse sign transforms can be used for converting data between known spectral “sign Haar” and “sign Walsh” domains. Recursive definitions for the calculation of the new transfor... View full abstract»

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  • Multiple-valued logic design using multiple-valued EXOR

    Publication Year: 1995, Page(s):290 - 294
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    An approach to logic minimization using a new sum operation called multiple valued EXOR is proposed. The paper introduces the multiple valued sum of products expression using the EXOR. As the scheme of the minimization, we utilize an idea based on neural computing. First, we demonstrate the method to minimize the binary EXOR of MINs expressions and show that the method is effective. Next, we apply... View full abstract»

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  • Resonant tunneling transistor and its application to multiple-valued logic circuits

    Publication Year: 1995, Page(s):130 - 138
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Progress in multiple-valued logic (MVL) depends much on the development of devices that are inherently suitable for MVL operation. With their multiple stable states, resonant tunneling devices are promising candidates. Although not at a matured stage yet, resonant tunneling transistors (RTTs) and diodes (RTDs) are expected to be indispensable for practical applications of MVL in the near future. I... View full abstract»

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  • On lattice-isomorphism between fuzzy equivalence relations and fuzzy partitions

    Publication Year: 1995, Page(s):146 - 151
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We present our results concerning the fact that fuzzy equivalence relations and fuzzy partitions together with appropriate partial orderings form lattices and that these lattices are isomorphic. In our investigation we apply the results of H. Thiele, N. Schmechel (1995) concerning the definitions of fuzzy equivalence relations, fuzzy partitions and the existence of a bijection between them. We sho... View full abstract»

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  • Learning multiple-valued logic networks based on backpropagation

    Publication Year: 1995, Page(s):270 - 275
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    This paper describes a learning multiple-valued logic (MVL) network based on back propagation. The learning MVL network is derived directly from a canonical realization of MVL functions and therefore its functional completeness is guaranteed. We extend traditional back propagation to include the prior human knowledge on the MVL networks, for example, the architecture and the number of hidden units... View full abstract»

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  • Planar multiple-valued decision diagrams

    Publication Year: 1995, Page(s):28 - 35
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to bin... View full abstract»

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  • On designing of 4-valued memory with double-gate TFT

    Publication Year: 1995, Page(s):187 - 192
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    We propose and analyze a new 4 valued memory cell by using the double gate thin film transistor (TFT). First, the structure of the double gate TFT is introduced. An equivalent circuit of the double gate TFT is proposed for the HSPICE simulation. Two circuits which are composed of the resistor load and the CMOS load basic block circuit are proposed and analyzed. The simulation results by using a la... View full abstract»

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  • Race-hazard and skip-hazard in multivalued combinational circuits

    Publication Year: 1995, Page(s):222 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The paper discusses race hazards based on AND/OR expression of functions in multivalued combinational circuits, and proposes techniques for eliminating race hazards by algebraic and K map's means. Furthermore, the paper analyzes the skip hazard, another inherent hazard in multivalued circuits, and points out that it is a normal response for multivalued circuits. They can be restrained by using the... View full abstract»

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  • From multivalued current mode CMOS circuits to efficient voltage mode CMOS arithmetic operators

    Publication Year: 1995, Page(s):58 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    We show that a 3-valued current mode CMOS 2-input BSC adder can be converted into a CMOS binary 4-2 counter or into a 1-digit Avizienis-like adder using a redundant number representation. Using a current mode algorithm to derive binary CMOS implementations of these arithmetic operators leads to equivalent or faster circuit implementation than the typical implementations that have been used until n... View full abstract»

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  • Decomposition of multiple-valued functions

    Publication Year: 1995, Page(s):256 - 261
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    This paper presents a generalized method for decomposition of multiple-valued functions. The main reason for using the described method is efficient implementation of logic circuits as well as effective representation of data in information systems. In logic synthesis, the method reduces the demand for silicon space required to implement designs. It is shown that the decomposition technique leads ... View full abstract»

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  • Quantum device model based super pass gate for multiple-valued digital systems

    Publication Year: 1995, Page(s):92 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The investigation of the device functions required from the systems point of view is important for the development of the next generation of VLSI devices and systems. A super pass transistor (SPT) model is presented as a quantum device candidate for future multiple-valued VLSI systems. Since it has the powerful capability of multiple-signal-level detection, the SPT will be useful for implementing ... View full abstract»

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  • Redundant complex number systems

    Publication Year: 1995, Page(s):14 - 19
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    This paper presents redundant complex number systems (RCNSs)-new complex number representations for high-speed arithmetic circuits. RCNS is a positional number system that has a complex radix rj and a digit set {-α,…,0,…,α}, where r⩾2 and [(r2 -1)/2]⩽α⩽r2-1. The use of complex radix rj allows additions and multiplications of complex... View full abstract»

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  • The high speed ternary logic gates based on the multiple β transistors

    Publication Year: 1995, Page(s):178 - 181
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The paper develops a kind of multiple β transistor based on the multiple emitter transistor whose emitter has different current gain β. It then presents the design of the linear AND/OR gates and multi valued literal circuits. These two kinds of circuits have not only simple structures but also very high operating speeds so that they can be utilized to the design of the high speed multi v... View full abstract»

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