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Proceedings 25th International Symposium on Multiple-Valued Logic

23-25 May 1995

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Displaying Results 1 - 25 of 46
  • Proceedings 25th International Symposium on Multiple-Valued Logic

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (414 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Classification of functions and enumeration of bases of set logic under Boolean compositions

    Publication Year: 1995, Page(s):78 - 85
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This paper discusses some classification and enumeration problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic. B-maximal sets are maximal sets containing all Boolean functions, where Boolean functions are those obtained from ∪, ∩ and ... View full abstract»

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  • The radii of Sheffer functions over E(3)

    Publication Year: 1995, Page(s):72 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    If f is a two place function over E(k) that is either Sheffer or Sheffer with constants, then the radius of f is that least natural number r such that each two place function over E(k) can be defined as the composition of r or fewer copies of f. The radii of the 322 isotopy classes of Sheffer functions over E(3) are calculated. A sequence of useful conditions that a Sheffer function have small rad... View full abstract»

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  • On lattice-isomorphism between fuzzy equivalence relations and fuzzy partitions

    Publication Year: 1995, Page(s):146 - 151
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We present our results concerning the fact that fuzzy equivalence relations and fuzzy partitions together with appropriate partial orderings form lattices and that these lattices are isomorphic. In our investigation we apply the results of H. Thiele, N. Schmechel (1995) concerning the definitions of fuzzy equivalence relations, fuzzy partitions and the existence of a bijection between them. We sho... View full abstract»

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  • Multiple-valued arithmetic integrated circuits based on 1.5 V-supply dual-rail source-coupled logic

    Publication Year: 1995, Page(s):64 - 69
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper presents a new multiple-valued current-mode MOS integrated circuit for high-speed arithmetic systems with a low supply voltage. The use of a multiple-valued source-coupled logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the switching delay of the circuit can be reduced at a low supply voltage. As an applicatio... View full abstract»

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  • On the mutual definability of fuzzy tolerance relations and fuzzy tolerance coverings

    Publication Year: 1995, Page(s):140 - 145
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Studies the mathematical foundations of cluster analysis, i.e. the correspondences between binary relations (“similarity relations”) and systems of sets (“clusters”) with respect to a fixed universe. For a long time, from crisp set theory and the classical (crisp) theory of universal algebras, such correspondences have been well-known as bijections and lattice isomorphisms ... View full abstract»

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  • From multivalued current mode CMOS circuits to efficient voltage mode CMOS arithmetic operators

    Publication Year: 1995, Page(s):58 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    We show that a 3-valued current mode CMOS 2-input BSC adder can be converted into a CMOS binary 4-2 counter or into a 1-digit Avizienis-like adder using a redundant number representation. Using a current mode algorithm to derive binary CMOS implementations of these arithmetic operators leads to equivalent or faster circuit implementation than the typical implementations that have been used until n... View full abstract»

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  • Resonant tunneling transistor and its application to multiple-valued logic circuits

    Publication Year: 1995, Page(s):130 - 138
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Progress in multiple-valued logic (MVL) depends much on the development of devices that are inherently suitable for MVL operation. With their multiple stable states, resonant tunneling devices are promising candidates. Although not at a matured stage yet, resonant tunneling transistors (RTTs) and diodes (RTDs) are expected to be indispensable for practical applications of MVL in the near future. I... View full abstract»

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  • Memory circuits for multiple valued logic voltage signals

    Publication Year: 1995, Page(s):52 - 57
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Voltage-mode CMOS multiple valued logic memory circuits have been realized in a standard 2-micron p-well polysilicon-gate CMOS technology. These circuits requantize multiple-valued logical voltages during a SETUP clock mode and latch the input value during the HOLD clock mode. Using a 5 volt supply and logical voltage increments of 1.67 volts, two similar quaternary memory circuits have worst-case... View full abstract»

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  • Wire-free computing circuits using optical wave-casting

    Publication Year: 1995, Page(s):8 - 13
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper presents wire-free computing circuits using optical wave-casting to provide a solution to the interconnection problems in parallel processing. The “wave-casting” implies wire-free communication scheme, where intensity-modulated optical signals are employed as information carriers and their frequencies represent the information in the system. In wavecasting-based parallel pro... View full abstract»

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  • A three-valued semantics for discourse representations

    Publication Year: 1995, Page(s):123 - 128
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Outlines a three-valued semantics for discourse representation theory (DRT) with a sequent calculus LKD. The proposed sequent calculus lacks the identity axiom and is a fragment of Gentzen's LK. By translating discourse representation structures into formulas in predicate logic, LKD can yield a proof theory for DRT based on the Schütte (1977) valuations. Some formal results for three-valued s... View full abstract»

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  • Properties of the Zhang-Watari transform

    Publication Year: 1995, Page(s):44 - 49
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The relationship between the 2D multiple-valued (complex-valued) Haar transform and the 2D real valued Zhang-Watari transform of patterns is studied and a method is disclosed to compute the Haar-(more properly, Watari)-spectrum of a pattern by using only real arithmetic. It is shown that to extend the straight forward 1D results to the 2D case, a special permutation operation has to be introduced.... View full abstract»

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  • Random pattern fault simulation in multi-valued circuits

    Publication Year: 1995, Page(s):98 - 103
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We present a fault simulator for Multi-Valued Logic Networks (MVLN). With this tool we investigate their Random Pattern Testability (RPT). We show for a restricted class of multi-valued circuits that the RPT is better than for two-valued circuits. We point out the relation between redundancies in two- and multi-valued logic networks. Moreover we show that the role of fault simulation for MVLNs is ... View full abstract»

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  • A high-speed interconnect network using ternary logic

    Publication Year: 1995, Page(s):2 - 7
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper describes the design and implementation of a high-speed interconnect network (ICN) for a multiprocessor system using ternary logic. By using ternary logic and a fast point-to-point communication technique called STARI (Self-Timed At Receiver's Input), the communication between the processors is free of clock skew and insensitive to any delay differences in buffers and wires. In addition... View full abstract»

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  • Novel quantized transform for ternary systems

    Publication Year: 1995, Page(s):117 - 122
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A nonlinear quantized transform, called the “sign transform”, has been introduced. Besides being unique, and converting binary/ternary data into the ternary spectral domain, forward and inverse sign transforms can be used for converting data between known spectral “sign Haar” and “sign Walsh” domains. Recursive definitions for the calculation of the new transfor... View full abstract»

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  • Race-hazard and skip-hazard in multivalued combinational circuits

    Publication Year: 1995, Page(s):222 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The paper discusses race hazards based on AND/OR expression of functions in multivalued combinational circuits, and proposes techniques for eliminating race hazards by algebraic and K map's means. Furthermore, the paper analyzes the skip hazard, another inherent hazard in multivalued circuits, and points out that it is a normal response for multivalued circuits. They can be restrained by using the... View full abstract»

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  • Reed-Muller forms for incompletely specified functions via sparse polynomial interpolation

    Publication Year: 1995, Page(s):36 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    In this paper we investigate the possibility of exploiting incompletely specified functions for the purpose of minimizing Reed-Muller (RM) forms. All the previous work in this area has been based on exhaustive search for the optimal solution, or on some approximations to it. Here we show that an alternative approach can bring better results: the definition of the MVL RM transforms as a polynomial ... View full abstract»

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  • Quantum device model based super pass gate for multiple-valued digital systems

    Publication Year: 1995, Page(s):92 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The investigation of the device functions required from the systems point of view is important for the development of the next generation of VLSI devices and systems. A super pass transistor (SPT) model is presented as a quantum device candidate for future multiple-valued VLSI systems. Since it has the powerful capability of multiple-signal-level detection, the SPT will be useful for implementing ... View full abstract»

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  • Paraconsistent circumscription: first-order case

    Publication Year: 1995, Page(s):112 - 116
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    In this paper we describe paraconsistent circumscription by application of predicate circumscription in a paraconsistent logic. In addition to circumscribe the predicates, we also circumscribe the inconsistency. Paraconsistent circumscription can be well characterized by the minimal semantics that is both nonmonotonic and paraconsistent. It brings us advantages at least in two respects: nonmonoton... View full abstract»

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  • Current-mode CMOS multiple-valued logic function realization using a direct cover algorithm

    Publication Year: 1995, Page(s):216 - 221
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    In the past, several heuristic based programs have been reported to obtain an efficient sum of product (SOP) form expression for a given MVL function using the literal, min, and tsum set of operators. HAMLET, one of these programs, includes implementation of many earlier reported heuristic based algorithms. In HAMLET, the Gold heuristic chooses the best realization after applying all other heurist... View full abstract»

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  • Factorization of multi-valued logic functions

    Publication Year: 1995, Page(s):164 - 169
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The paper describes an approach to factorization of multi valued logic (MVL) functions. The key concept is to formulate the problem as a rectangular covering problem. First, we develop an MVL algebraic factorization algorithm. Then, by incorporating two MVL Boolean properties: “identical” and “complementary”, we further improve the purely algebraic factorization algorithm t... View full abstract»

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  • Planar multiple-valued decision diagrams

    Publication Year: 1995, Page(s):28 - 35
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to bin... View full abstract»

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  • Uniqueness of partially specified multiple-valued Kleenean function

    Publication Year: 1995, Page(s):242 - 247
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A multiple-valued Kleenean function is a mapping fk:[0,1]n→[0,1], which is representable by a logic formula consisting n variables, three logical connectives, and any constant value of [0,1]. In this paper, some properties of the partially specified multiple-valued Kleenean functions by a subset A of [0,1] are investigated and the identification problem of logic formula ... View full abstract»

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  • A fuzzy membership function circuit using hysteretic resonant tunneling diodes

    Publication Year: 1995, Page(s):182 - 186
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The use of novel resonant tunneling devices in fuzzy logic hardware has been demonstrated previously (H. Tang, H.C. Lin, 1994). The results have shown great improvement in speed and reduced circuit complexity. However, one major problem associated with these resonant tunneling diodes (RTDs) is the hysteretic effect which in some applications may deteriorate circuit performance considerably. The pa... View full abstract»

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