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Proceedings 13th IEEE VLSI Test Symposium

April 30 1995-May 3 1995

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Displaying Results 1 - 25 of 71
  • Proceedings 13th IEEE VLSI Test Symposium

    Publication Year: 1995
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    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (112 KB)
    Freely Available from IEEE
  • An approach for system tests design and its application

    Publication Year: 1995, Page(s):448 - 453
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An approach for system test design is suggested and justified by the corresponding mathematical model. It is based on the representation of a testing process in an aggregate form of two dynamically interacting components: a control testing table and a testing processor. Control testing tables are equivalent to linear programs which process Boolean arrays. It is proved that the correctness problem ... View full abstract»

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  • Diagnosis of interconnects and FPICs using a structured walking-1 approach

    Publication Year: 1995, Page(s):256 - 261
    Cited by:  Papers (30)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). The proposed structural test method explicitly avoids aliasing and confounding and as applicable to dense as well as sparse layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two alg... View full abstract»

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  • Detectable perturbations: a paradigm for technology-specific multi-fault test generation

    Publication Year: 1995, Page(s):350 - 357
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    This paper introduces the concept of detectable perturbations as a method to generate tests that can then cover any technology-specific faults such as multiple bridging, open and stuck-at faults. Rather than devising a customized test pattern generation system for each class of technology-specific faults, we implemented a generic system to generate tests for single and multiple perturbations. We d... View full abstract»

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  • Synthesis of locally exhaustive test pattern generators

    Publication Year: 1995, Page(s):440 - 445
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compute the linear sums for real circuits up to several hundreds of inputs and outputs. The idea is to substitute a strategy of introducing fresh variables into an array of sums for the former linear independence test. This re... View full abstract»

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  • An approach to dynamic power consumption current testing of CMOS ICs

    Publication Year: 1995, Page(s):95 - 100
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    IDDQ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the... View full abstract»

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  • Transformed pseudo-random patterns for BIST

    Publication Year: 1995, Page(s):410 - 416
    Cited by:  Papers (36)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The transformation is performed by a small amount of mapping logic that decodes sets of patterns that don't detect any new faults and maps them into pattern... View full abstract»

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  • Diagnosis of scan path failures

    Publication Year: 1995, Page(s):250 - 255
    Cited by:  Papers (65)  |  Patents (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains View full abstract»

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  • A scheduling problem in test generation

    Publication Year: 1995, Page(s):344 - 349
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The order of faults which are targeted for test-pattern generation affects both the processing time for test generation and the number of test-patterns. This order is referred to as a test generation schedule. In this paper, we consider the test generation scheduling problem which minimizes the cost of testing. We analyze the effect of scheduling based on test-pattern generation time and dominatin... View full abstract»

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  • Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits

    Publication Year: 1995, Page(s):434 - 439
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during test mode, result in an overhead for the circuit. However, cutting edges containing registers eliminates these secondary effects. In this paper, we present a... View full abstract»

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  • Redundancy removal and test generation for circuits with non-Boolean primitives

    Publication Year: 1995, Page(s):12 - 19
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    Production VLSI circuits typically consist of primitives like tri-state buffers, bidirectional buffers and bus configurations that assume non-Boolean values like the high-impedance state. The present work describes a systematic methodology for extending test generation algorithms to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based t... View full abstract»

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  • Cyclic stress tests for full scan circuits

    Publication Year: 1995, Page(s):89 - 94
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It ... View full abstract»

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  • Verification of transient response of linear analog circuits

    Publication Year: 1995, Page(s):42 - 47
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    With the introduction of complex analog designs the need to verify the circuit behavior completely and efficiently cannot be overemphasized. Recognizing the limitation of circuit simulation to achieve this goal, we present a novel approach based on formal techniques developed for digital circuits. Given a transfer function (specification) and its implementation using operational amplifier macro ci... View full abstract»

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  • Multifault testability of delay-testable circuits

    Publication Year: 1995, Page(s):400 - 403
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    This paper investigates the relationship between path-delay-fault testability and multiple stuck-at-fault testability in multilevel combinational circuits. It is shown that a complete robust path-delay-fault test set may not detect all multiple stuck-at faults in multilevel circuits. We also show that path-delay-fault testability does not imply multiple stuck-at-fault testability in multilevel cir... View full abstract»

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  • Improving the efficiency of error identification via signature analysis

    Publication Year: 1995, Page(s):244 - 249
    Cited by:  Papers (26)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=fa(x)fb(x) where f a(x) and fb(x) have different degrees and are of the form fn(x)=xn+xn-1+1. The input polynomial must be of degree <lcm(ord(fa(x)), o... View full abstract»

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  • On the design of at-speed testable VLSI circuits

    Publication Year: 1995, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    In this paper, a new design-for-testability technique for sequential circuits is presented. This technique may be considered as an alternative to full scan. The fault coverages obtained with this technique are comparable to those produced by full scan techniques. However, the present method improves full scan in several ways. The application test time of a device is reduced to that of applying par... View full abstract»

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  • Improving topological ATPG with symbolic techniques

    Publication Year: 1995, Page(s):338 - 343
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their sequ... View full abstract»

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  • Testability metrics for synthesis of self-testable designs and effective test plans

    Publication Year: 1995, Page(s):170 - 175
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    We propose a set of unified metrics for self-testability which are portable across different phases of synthesis. Furthermore, applicability of the proposed test metrics is verified through extensive experiments on benchmark designs View full abstract»

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  • Decompression of test data using variable-length seed LFSRs

    Publication Year: 1995, Page(s):426 - 433
    Cited by:  Papers (51)  |  Patents (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    This paper presents a new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan. The scheme is based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits. The paper analyzes the effectiveness ... View full abstract»

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  • Identifying sequentially untestable faults using illegal states

    Publication Year: 1995, Page(s):4 - 11
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In this paper, we first present an algorithm (FILL) which efficiently identifies a large subset of the illegal states in a synchronous sequential circuit, without assuming a global reset mechanism. A second algorithm, FUNI, finds sequentially untestable faults whose detection requires some of the illegal states computed by FlLL. Although based on binary decision diagrams (BDDs), FILL is able to pr... View full abstract»

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  • Frequency-based BIST for analog circuit testing

    Publication Year: 1995, Page(s):54 - 59
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value ±ε. A sine wave generator and two different BISTs are ... View full abstract»

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  • Test pattern generation for IDDQ: increasing test quality

    Publication Year: 1995, Page(s):304 - 309
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during t... View full abstract»

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  • The concept of resistance interval: a new parametric model for realistic resistive bridging fault

    Publication Year: 1995, Page(s):184 - 189
    Cited by:  Papers (54)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 Ω to 500 Ω. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible,... View full abstract»

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  • Self-test in a VCM driver chip

    Publication Year: 1995, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    This paper describes a cost effective self-test mode in a complex mixed-signal device. The device under test (DUT) is a Voice-Coil Motor (VCM) H-bridge amplifier with an onchip 11-bit D/A converter. The self-test mode can be initiated at the chip, board and system levels of testing and troubleshooting. The added self-test circuitry does not induce any noticeable silicon overhead View full abstract»

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