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Proceedings 13th IEEE VLSI Test Symposium

April 30 1995-May 3 1995

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  • Proceedings 13th IEEE VLSI Test Symposium

    Publication Year: 1995
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    Freely Available from IEEE
  • Testability of floating gate defects in sequential circuits

    Publication Year: 1995, Page(s):202 - 207
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB)

    The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable bra... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Arithmetic built-in self test for high-level synthesis

    Publication Year: 1995, Page(s):132 - 139
    Cited by:  Papers (28)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits View full abstract»

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  • Checking experiments to test latches

    Publication Year: 1995, Page(s):196 - 201
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Necessary and sufficient conditions for exhaustive functional tests (checking experiments) of 2-state latches are derived. These conditions are used to derive minimum-length checking experiments. The checking experiment for the D-latch is simulated using an HSpice implementation of the transmission gate latch. All detectable shorted interconnects, open interconnects, short-to-power, short-to-groun... View full abstract»

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  • An apparatus for pseudo-deterministic testing

    Publication Year: 1995, Page(s):125 - 131
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST. We employ an arbitrary length Shift Register driven by a LFSR (LFSR/SR) with the size of the LFSR dependent only on the number of care bits in any test vector. We provide an efficient method to compute positions of bit-patterns at arbitrarily chosen tap confi... View full abstract»

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  • Partial scan designs without using a separate scan clock

    Publication Year: 1995, Page(s):277 - 282
    Cited by:  Papers (5)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Existing flip-flop selection and test generation methods for partial scan designs assume the use of a separate scan clock. With a separate clock for the scan operation, the states of the non-scan flip-flops can be frozen during the scan operation and any state can be scanned into the scan register without affecting the states of the non-scan flip-flops. Under this assumption, test vectors can be e... View full abstract»

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  • High level fault modeling of asynchronous circuits

    Publication Year: 1995, Page(s):190 - 195
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A method is proposed for high level fault modeling of asynchronous circuits which are described by the signal transition graph. Transitional fault models are introduced. It is shown that the transitional faults are the direct mappings of most of the low level faults View full abstract»

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  • Fault coverage analysis of RAM test algorithms

    Publication Year: 1995, Page(s):227 - 234
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    A methodology for evaluating the fault coverage of RAM test algorithms is proposed and the architecture of a flexible software analysis program is described. The analysis, performed for arbitrary test sequences, provides a comprehensive set of coverage statistics for functional cell-array faults. An overview of the analysis capabilities of the program is given, the fault state transition condition... View full abstract»

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  • Structural constraints for circular self-test paths

    Publication Year: 1995, Page(s):486 - 491
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Constraints on the structure of circular self-test paths in register transfer level (RTL) circuits with circular Built-In Self Test (BIST) features are discussed. These constraints arise from the desire to avoid bit-level correlation, which can have a devastating effect on test quality. Two causes of bit-level correlation are examined, with examples demonstrating the resulting degradation in test ... View full abstract»

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  • Signature analysis and aliasing for sequential circuits

    Publication Year: 1995, Page(s):118 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    Many built-in self-test techniques insert test registers and thus segment the circuit into subcircuits which are surrounded by test registers. If not all registers of the circuit are enhanced to test registers, the resulting subcircuits are sequential. Errors in their test responses generally depend on the state of the subcircuit and hence can be correlated both in space and in time. In this paper... View full abstract»

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  • Diagnosis of scan path failures

    Publication Year: 1995, Page(s):250 - 255
    Cited by:  Papers (65)  |  Patents (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains View full abstract»

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  • Asynchronous multiple scan chains

    Publication Year: 1995, Page(s):270 - 276
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    The long test application times needed for scan designs increase the costs of testing. In this paper we introduce the concept of asynchronous multiple scan chains in which groups of scan chains operate independently. This is achieved by using more than one made signal to control the scan flip-flops. Asynchronous multiple chains can provide large reductions in the test application time. We present ... View full abstract»

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  • Detecting IDDQ defective CMOS circuits by depowering

    Publication Year: 1995, Page(s):324 - 329
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    When disconnecting the power supply line of a CMOS circuit in its quiescent state, the capacitances present in the circuit hold the logic valves in all their nodes. In non defective circuits, these capacitances discharge very slowly due to the extremely small IDDQ discharge current. On the other hand, in IDDQ defective circuits the discharge is faster than in the previous cas... View full abstract»

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  • The concept of resistance interval: a new parametric model for realistic resistive bridging fault

    Publication Year: 1995, Page(s):184 - 189
    Cited by:  Papers (54)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 Ω to 500 Ω. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible,... View full abstract»

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  • VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits

    Publication Year: 1995, Page(s):221 - 226
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    VISION is an efficient parallel pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient parallel pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the parallel pattern fault simulation for synchronous sequential circuits. According to our expe... View full abstract»

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  • Test pattern generation for IDDQ: increasing test quality

    Publication Year: 1995, Page(s):304 - 309
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during t... View full abstract»

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  • An experimental evaluation of the differential BICS for IDDQ testing

    Publication Year: 1995, Page(s):472 - 480
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    In this paper we present an experimental study on the effectiveness of IDDQ testing using the differential built-in current sensor (BICS) circuit. Two new test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different “realistic” CMOS faults: inter- and intra-layer sho... View full abstract»

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  • On shrinking wide compressors

    Publication Year: 1995, Page(s):108 - 117
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed... View full abstract»

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  • Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits

    Publication Year: 1995, Page(s):434 - 439
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during test mode, result in an overhead for the circuit. However, cutting edges containing registers eliminates these secondary effects. In this paper, we present a... View full abstract»

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  • Improving the efficiency of error identification via signature analysis

    Publication Year: 1995, Page(s):244 - 249
    Cited by:  Papers (26)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=fa(x)fb(x) where f a(x) and fb(x) have different degrees and are of the form fn(x)=xn+xn-1+1. The input polynomial must be of degree <lcm(ord(fa(x)), o... View full abstract»

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  • Detection and location of faults and defects using digital signal processing

    Publication Year: 1995, Page(s):262 - 267
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper presents the bases of a test method that can detect and locate faults and defects. This method is based on the use of digital signal processing applied on sampled current or voltage and can be applied to technologies with significant quiescent current. A simple procedure is also proposed in order to locate parasitic resistive contacts, and diagnosis potential of the method is explored View full abstract»

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  • CURRENT: a test generation system for IDDQ testing

    Publication Year: 1995, Page(s):317 - 323
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    This paper presents an IDDQ test generation system for scan-based circuits, called CURRENT. A library-based fault modeling strategy is used to specify a realistic target fault set, which encompasses intra-gate shorts (for example stuck-on faults, gate-drain shorts) as well as inter-gate shorts (bridging faults). CURRENT consists of a fault simulator and a deterministic test generator. T... View full abstract»

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  • An approach for system tests design and its application

    Publication Year: 1995, Page(s):448 - 453
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An approach for system test design is suggested and justified by the corresponding mathematical model. It is based on the representation of a testing process in an aggregate form of two dynamically interacting components: a control testing table and a testing processor. Control testing tables are equivalent to linear programs which process Boolean arrays. It is proved that the correctness problem ... View full abstract»

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  • Frequency-based BIST for analog circuit testing

    Publication Year: 1995, Page(s):54 - 59
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value ±ε. A sine wave generator and two different BISTs are ... View full abstract»

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