Proceedings 13th IEEE VLSI Test Symposium

April 30 1995-May 3 1995

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  • Proceedings 13th IEEE VLSI Test Symposium

    Publication Year: 1995
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    Freely Available from IEEE
  • Testability of floating gate defects in sequential circuits

    Publication Year: 1995, Page(s):202 - 207
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB)

    The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable bra... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Decompression of test data using variable-length seed LFSRs

    Publication Year: 1995, Page(s):426 - 433
    Cited by:  Papers (52)  |  Patents (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    This paper presents a new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan. The scheme is based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits. The paper analyzes the effectiveness ... View full abstract»

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  • Diagnosis of scan path failures

    Publication Year: 1995, Page(s):250 - 255
    Cited by:  Papers (66)  |  Patents (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains View full abstract»

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  • A novel pattern generator for near-perfect fault-coverage

    Publication Year: 1995, Page(s):417 - 425
    Cited by:  Papers (47)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The pattern generator consists of two components: a GLFSR, earlier proposed as a pseudo-random pattern generator, and combinational logic, to snap the outputs of the pseudo-random pattern generator. Using fewer test patterns with only a small area overhead, this combinatorial logic block, for a... View full abstract»

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  • Verification of transient response of linear analog circuits

    Publication Year: 1995, Page(s):42 - 47
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    With the introduction of complex analog designs the need to verify the circuit behavior completely and efficiently cannot be overemphasized. Recognizing the limitation of circuit simulation to achieve this goal, we present a novel approach based on formal techniques developed for digital circuits. Given a transfer function (specification) and its implementation using operational amplifier macro ci... View full abstract»

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  • Detectable perturbations: a paradigm for technology-specific multi-fault test generation

    Publication Year: 1995, Page(s):350 - 357
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    This paper introduces the concept of detectable perturbations as a method to generate tests that can then cover any technology-specific faults such as multiple bridging, open and stuck-at faults. Rather than devising a customized test pattern generation system for each class of technology-specific faults, we implemented a generic system to generate tests for single and multiple perturbations. We d... View full abstract»

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  • Improving the efficiency of error identification via signature analysis

    Publication Year: 1995, Page(s):244 - 249
    Cited by:  Papers (26)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=fa(x)fb(x) where f a(x) and fb(x) have different degrees and are of the form fn(x)=xn+xn-1+1. The input polynomial must be of degree <lcm(ord(fa(x)), o... View full abstract»

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  • A low cost 100 MHz analog test bus

    Publication Year: 1995, Page(s):60 - 65
    Cited by:  Papers (10)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This paper describes an on-chip analog bus whose bandwidth is limited primarily by an off-chip amplifier. It uses only a digital 3-state inverter for each bus input. The high-speed and constant low-input capacitance of this scheme make it suitable for measuring sensitive or even digital signals. For equal silicon area, the signal bandwidth is demonstrated to be 10 to 40 times that of previously re... View full abstract»

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  • Generation of high quality tests for functional sensitizable paths

    Publication Year: 1995, Page(s):374 - 379
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Some previously published results show that in a number of combinational circuits a significant portion of long paths is neither robustly nor non-robustly testable. However, not all of those untestable paths may be ignored in delay testing. Functional sensitizable paths are robust and non-robust untestable but, under some faulty conditions, may degrade the performance of the circuit. Even though t... View full abstract»

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  • The use of IDDQ testing in low stuck-at coverage situations

    Publication Year: 1995, Page(s):84 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    An unresolved issue in IC testing is what mix of coverages of different types of test is required in order to achieve a given quality goal. This paper investigates the interaction between IDDQ and stuck-at coverage and examines the use of IDDQ to increase effective stuck-at coverage, particularly in situations where the graded coverage is lower than the desired goal. Empirical data is presented wh... View full abstract»

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  • Transformed pseudo-random patterns for BIST

    Publication Year: 1995, Page(s):410 - 416
    Cited by:  Papers (38)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The transformation is performed by a small amount of mapping logic that decodes sets of patterns that don't detect any new faults and maps them into pattern... View full abstract»

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  • Testing combinational iterative logic arrays for realistic faults

    Publication Year: 1995, Page(s):35 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficien... View full abstract»

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  • Real-time on-board bus testing

    Publication Year: 1995, Page(s):140 - 145
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper will define and describe a methodology for testing wide buses in real-time at speed. In today's environment, computer buses are growing along with system clock speeds. These wide high-speed buses require special attention at time of board layout and analysis. Characterization of tests on a bus at high-speed cause unnecessary problems of tester interference. For example, the addition of ... View full abstract»

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  • An experimental evaluation of the differential BICS for IDDQ testing

    Publication Year: 1995, Page(s):472 - 480
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    In this paper we present an experimental study on the effectiveness of IDDQ testing using the differential built-in current sensor (BICS) circuit. Two new test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different “realistic” CMOS faults: inter- and intra-layer sho... View full abstract»

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  • A scheduling problem in test generation

    Publication Year: 1995, Page(s):344 - 349
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The order of faults which are targeted for test-pattern generation affects both the processing time for test generation and the number of test-patterns. This order is referred to as a test generation schedule. In this paper, we consider the test generation scheduling problem which minimizes the cost of testing. We analyze the effect of scheduling based on test-pattern generation time and dominatin... View full abstract»

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  • Reliability evaluation of combinational logic circuits by symbolic simulation

    Publication Year: 1995, Page(s):235 - 242
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple faults on circuit functionality, we use fault indicators as control variables. We use BDD-based symbolic simulation to avoid the explicit enumeration of faults. We present experimental results on fault-tolerant implementations of several mcnc b... View full abstract»

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  • Synthesis of locally exhaustive test pattern generators

    Publication Year: 1995, Page(s):440 - 445
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compute the linear sums for real circuits up to several hundreds of inputs and outputs. The idea is to substitute a strategy of introducing fresh variables into an array of sums for the former linear independence test. This re... View full abstract»

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  • Frequency-based BIST for analog circuit testing

    Publication Year: 1995, Page(s):54 - 59
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value ±ε. A sine wave generator and two different BISTs are ... View full abstract»

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  • Identifying sequentially untestable faults using illegal states

    Publication Year: 1995, Page(s):4 - 11
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In this paper, we first present an algorithm (FILL) which efficiently identifies a large subset of the illegal states in a synchronous sequential circuit, without assuming a global reset mechanism. A second algorithm, FUNI, finds sequentially untestable faults whose detection requires some of the illegal states computed by FlLL. Although based on binary decision diagrams (BDDs), FILL is able to pr... View full abstract»

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  • Reducing test application time in scan design schemes

    Publication Year: 1995, Page(s):367 - 372
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test g... View full abstract»

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  • On the decline of testing efficiency as fault coverage approaches 100%

    Publication Year: 1995, Page(s):74 - 83
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defect... View full abstract»

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  • On the application of local circuit transformations with special emphasis on path delay fault testability

    Publication Year: 1995, Page(s):387 - 392
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Several types of local transformations and their effect on path delay fault testability have been examined in the literature. In this paper we present SALT (System for Application of Local Transformations), which is a general tool for the application of a user-defined set of local transformations. The concepts of “related transformations” and of “pseudo-isomorphism” are int... View full abstract»

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  • Multifault testability of delay-testable circuits

    Publication Year: 1995, Page(s):400 - 403
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    This paper investigates the relationship between path-delay-fault testability and multiple stuck-at-fault testability in multilevel combinational circuits. It is shown that a complete robust path-delay-fault test set may not detect all multiple stuck-at faults in multilevel circuits. We also show that path-delay-fault testability does not imply multiple stuck-at-fault testability in multilevel cir... View full abstract»

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