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Proceedings. Fifth Great Lakes Symposium on VLSI

16-18 March 1995

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  • Proceedings. Fifth Great Lakes Symposium on VLSI

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (267 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (95 KB)
    Freely Available from IEEE
  • On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing

    Publication Year: 1995, Page(s):204 - 207
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Locally optimal breaking strategy was already developed for disjoint directed circuits in the vertical constraint graph. The paper reports extensions to two classes of nondisjoint circuits: with a common vertex, and with a common path. The significance of this is that the demonstration of general applicability of the locally optimal breaking concept opens a new approach to improving the channel ro... View full abstract»

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  • Fast algorithm for performance-oriented Steiner routing

    Publication Year: 1995, Page(s):198 - 203
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a ... View full abstract»

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  • A systolic algorithm and architecture for image thinning

    Publication Year: 1995, Page(s):138 - 143
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    In this paper, we describe a new special purpose VLSI architecture for image thinning. The architecture is systolic and is based on an algorithm that achieves a high degree of parallelism. The proposed algorithm computes the skeleton of multiple objects in an image in linear time by making 2 scans over the 4-distance transform of the image. The algorithm is mapped onto a linear systolic array of s... View full abstract»

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  • Pseudo-random behavioral ATPG

    Publication Year: 1995, Page(s):192 - 195
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper deals with a new approach for the Automatic Test Pattern Generation (ATPG) of circuits described from a behavioral point of view in VHDL. This approach is based on a pseudo-random process characterized by the fact that criteria for computing the test length and evaluating the quality of the generated data come from the field of software engineering. This paper presents the bases of this... View full abstract»

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  • Priority driven channel pin assignment

    Publication Year: 1995, Page(s):132 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    We present a polynomial time improvement of the linear channel pin assignment LCPA algorithms presented by Cai and Wong in 1990. We solve the LCPA problem according to minimum channel density under a special priority schedule subject to vertical constraints and flux. The priority driven linear channel pin assignment algorithm (PDCPA) reduces the channel height by an average of 17% without increasi... View full abstract»

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  • Automated verification of temporal properties specified as state machines in VHDL

    Publication Year: 1995, Page(s):100 - 105
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper presents a new verification methodology to prove that a high level HDL description of a synchronous sequential circuit satisfies certain desired behavior or that it is free of certain malicious behavior. The correctness specifications are modeled as state machines with some transitions having unspecified inputs. We show that this suffices for specification of a large class of properties... View full abstract»

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  • A universal formalization of the effects of threshold voltages for discrete switch-level circuit models

    Publication Year: 1995, Page(s):266 - 271
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In most discrete switch-level circuit models, switches, or transistors, are assumed to be perfect. That is, the effects of threshold voltages on signals are neglected in the discrete description of circuit behavior. In the formalization presented in this paper, the effects of imperfection of switches can be calculated separately from the abstracted circuit behavior. Furthermore, this formalization... View full abstract»

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  • Test application time reduction for scan based sequential circuits

    Publication Year: 1995, Page(s):188 - 191
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-ato... View full abstract»

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  • An efficient heuristic approach on minimizing the number of feedthrough cells in standard cell placement

    Publication Year: 1995, Page(s):128 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Standard cell design style has been widely applied for the design automation of VLSI circuits because of the easy implementation of the layout design. Since the aim of most standard cell design systems is to minimize the utilization of chip area, the number of feedthrough cells in a standard cell layout will be further minimized to reduce the layout size. In this paper, first, we model a row assig... View full abstract»

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  • Coding a terminated bus for low power

    Publication Year: 1995, Page(s):70 - 73
    Cited by:  Papers (28)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Coding was proposed as a general method of decreasing power dissipation for the I/O. Lower power dissipation can be obtained by using extra bus liner for coding the data. This paper presents an application of the general theory of limited-weight codes for a class of parallel terminated buses with pull-up terminators (e.g. Rambus). Power dissipation on such a bus-line is larger for a logical 1 and ... View full abstract»

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  • Scheduling conditional data-flow graphs with resource sharing

    Publication Year: 1995, Page(s):94 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper proposes pipeline scheduling algorithms for conditional branches and loop constructs, which are represented in the form of a conditional data-flow graph, where each node is associated with a condition vector. A novel data structure for dynamic resource sharing and a novel scheduling algorithm for resource sharing are proposed. Based on such a data structure and a modified rotation sched... View full abstract»

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  • ATM burst traffic generator

    Publication Year: 1995, Page(s):262 - 265
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    The Markov modulated process is widely used to model ATM (Asynchronous Transmission Mode) traffic sources because it can emulate the bursty and correlated traffic arrival. We propose a hardware sample generator emulating the bursty behavior of the Markov process and develop circuits for a 2-state Markov modulated process and an N-state homogeneous Markov modulated process. The generator can produc... View full abstract»

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  • Statistical estimation of delay fault detectabilities and fault grading

    Publication Year: 1995, Page(s):184 - 187
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detecta... View full abstract»

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  • Parallel hierarchical global routing for general cell layout

    Publication Year: 1995, Page(s):212 - 215
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine... View full abstract»

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  • Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs

    Publication Year: 1995, Page(s):148 - 151
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    We describe a technique for translating semicustom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based environment. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and tran... View full abstract»

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  • Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions

    Publication Year: 1995, Page(s):112 - 116
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The use of symbolic techniques to store integer-valued functions has been shown to be extremely effective in handling both transform matrices and spectral representations of large Boolean functions. In this paper we propose a novel application of symbolic Rademacher-Walsh spectral transforms to the evaluation of Boolean function correlation. In particular, we present an ADD-based algorithm to comp... View full abstract»

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  • Performance driven standard-cell placement using the genetic algorithm

    Publication Year: 1995, Page(s):124 - 127
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumer... View full abstract»

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  • Design and analysis of a low-power energy-recovery adder

    Publication Year: 1995, Page(s):66 - 69
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies View full abstract»

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  • Optimizing wiring space in slicing floorplans

    Publication Year: 1995, Page(s):54 - 57
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This paper addresses the problem of minimizing wiring space in an existing slicing floorplan. Wiring space is measured in terms of net density, and the existing floorplan is adjusted only by interchanging sibling rectangles and by mirroring circuit modules. An exact branch and bound algorithm and a heuristic are given for this problem. Experiments show that both algorithms are effective in reducin... View full abstract»

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  • Thumbnail rectilinear Steiner trees

    Publication Year: 1995, Page(s):46 - 49
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The rectilinear Steiner tree problem is to find a minimum-length set of horizontal and vertical line segments that interconnect a given set of points in the plane. Here we study the thumbnail rectilinear Steiner tree problem, where the input points are drawn from a small integer grid. Specifically, we devise a full-set decomposition algorithm for computing optimal thumbnail rectilinear Steiner tre... View full abstract»

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  • A scalable analog architecture for neural networks with on-chip learning and refreshing

    Publication Year: 1995, Page(s):33 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    This paper discusses various techniques for analog storage and handling and proposes a new class of architecture suitable for modular and scalable analog neural networks with on-chip learning and refreshing. The new architecture is based on analog functional blocks and analog pass switches which enhance the system versatility. Supporting algorithms are also developed. A novel characteristic is the... View full abstract»

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  • A new look at the conditions for the synthesis of speed-independent circuits

    Publication Year: 1995, Page(s):230 - 235
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of t... View full abstract»

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  • A differential model approach to analog design automation

    Publication Year: 1995, Page(s):22 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A high-level analog design synthesis approach using differential equations as the hardware definition language is presented. From the differential equations, annotated with performance requirements, the design process generates a set of device requirements that can be used as the input requirements to existing low-level analog circuit synthesis tools which build the necessary low level analog devi... View full abstract»

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