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Proceedings. Fifth Great Lakes Symposium on VLSI

16-18 March 1995

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  • Proceedings. Fifth Great Lakes Symposium on VLSI

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (267 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (95 KB)
    Freely Available from IEEE
  • A scalable shared buffer ATM switch architecture

    Publication Year: 1995, Page(s):256 - 261
    Cited by:  Papers (2)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A scalable shared buffer switch architecture for asynchronous transfer mode (ATM) with O(√N) complexity for memory bandwidth requirement and maximum crosspoint switch size, and O(N) scalability for buffer memory size is proposed. Access time to buffer memories has been reduced by virtue of parallel access. The switch architecture features multiple buffer memories between the input and output... View full abstract»

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  • A personal computer based VLSI design curriculum

    Publication Year: 1995, Page(s):250 - 253
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    We have developed a VLSI curriculum based on personal computers that can be used at teaching institutions and corporations alike. The curriculum consists of three courses: a capstone VLSI course, an analog design course, and an advanced digital design synthesis course. No workstations are necessary, laboratories may be given without teaching assistants, and the entire system be used with minimal r... View full abstract»

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  • Symbolic execution of data paths

    Publication Year: 1995, Page(s):80 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitatio... View full abstract»

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  • A differential model approach to analog design automation

    Publication Year: 1995, Page(s):22 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A high-level analog design synthesis approach using differential equations as the hardware definition language is presented. From the differential equations, annotated with performance requirements, the design process generates a set of device requirements that can be used as the input requirements to existing low-level analog circuit synthesis tools which build the necessary low level analog devi... View full abstract»

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  • Linking fabrication and parametric testing to VLSI design courses

    Publication Year: 1995, Page(s):246 - 249
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The actual versus simulated performance of VLSI systems is dependent on the accuracy of the simulation model parameters and the soundness of the design rules used. Future process engineers must be schooled in VLSI design principles, while at the same time understanding the origin of the process based design rules and the statistical variation of device model parameters. This paper describes RIT's ... View full abstract»

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  • Circuit/architecture for low-power high-performance 32-bit adder

    Publication Year: 1995, Page(s):74 - 77
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    A novel 32-bit adder has been designed using a Conditional Sum Adder (CSA) architecture and CPL-like logic implementation. The new implementation outperforms several architectures such as CLA, CS and Manchester which use the CMOS circuit styles (CPL, DPL, TG, static-conventional) in terms of power and speed. This is verified for a range of power supply voltage from 3.3 V down to 1 V. The compariso... View full abstract»

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  • Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks

    Publication Year: 1995, Page(s):60 - 65
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper we propose a new approach to the problem of estimating worst-case power consumption of CMOS combinational circuits based on neural models. Given the gate level description of a circuit, we build the corresponding neural network, we store it, we calculate the energy dissipated by the network and, finally, we derive the power dissipated by the original circuit. All the operations above... View full abstract»

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  • Thumbnail rectilinear Steiner trees

    Publication Year: 1995, Page(s):46 - 49
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The rectilinear Steiner tree problem is to find a minimum-length set of horizontal and vertical line segments that interconnect a given set of points in the plane. Here we study the thumbnail rectilinear Steiner tree problem, where the input points are drawn from a small integer grid. Specifically, we devise a full-set decomposition algorithm for computing optimal thumbnail rectilinear Steiner tre... View full abstract»

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  • Optimal technology mapping for single output cells

    Publication Year: 1995, Page(s):14 - 19
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mapping based methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for duplication of logic ... View full abstract»

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  • Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test

    Publication Year: 1995, Page(s):242 - 245
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The XC4000 Logic Cell Array Family of field programmable gate arrays developed by Xilinx includes support for the IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. Boundary-scan with built-in self-test is known to provide tests of high quality. The design and implementation of boundary-scan with built-in self-test that conforms fully to the IEEE Standard 1149.1 for the XC4000 d... View full abstract»

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  • A local clocking approach for self-timed datapath designs

    Publication Year: 1995, Page(s):152 - 155
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in an asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation using... View full abstract»

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  • Improving self-timed pipeline ring performance through the addition of buffer loops

    Publication Year: 1995, Page(s):218 - 223
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    While self-timed pipelines have overcome the problem of clock skew which degrades the performance of synchronous pipelines, the improvement is not without its cost; self-timed pipelines are forced to spend a larger amount of time on communication than their synchronous counterparts. This has led researchers to search for ways to improve the performance of self-timed pipelines by changing the commu... View full abstract»

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  • A universal formalization of the effects of threshold voltages for discrete switch-level circuit models

    Publication Year: 1995, Page(s):266 - 271
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In most discrete switch-level circuit models, switches, or transistors, are assumed to be perfect. That is, the effects of threshold voltages on signals are neglected in the discrete description of circuit behavior. In the formalization presented in this paper, the effects of imperfection of switches can be calculated separately from the abstracted circuit behavior. Furthermore, this formalization... View full abstract»

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  • Coding a terminated bus for low power

    Publication Year: 1995, Page(s):70 - 73
    Cited by:  Papers (29)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Coding was proposed as a general method of decreasing power dissipation for the I/O. Lower power dissipation can be obtained by using extra bus liner for coding the data. This paper presents an application of the general theory of limited-weight codes for a class of parallel terminated buses with pull-up terminators (e.g. Rambus). Power dissipation on such a bus-line is larger for a logical 1 and ... View full abstract»

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  • Optimizing wiring space in slicing floorplans

    Publication Year: 1995, Page(s):54 - 57
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This paper addresses the problem of minimizing wiring space in an existing slicing floorplan. Wiring space is measured in terms of net density, and the existing floorplan is adjusted only by interchanging sibling rectangles and by mirroring circuit modules. An exact branch and bound algorithm and a heuristic are given for this problem. Experiments show that both algorithms are effective in reducin... View full abstract»

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  • Technology mapping algorithms for sequential circuits using look-up table based FPGAS

    Publication Year: 1995, Page(s):164 - 167
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper presents a set of algorithms for mapping sequential circuits onto look-up table based FPGAs and explores how it is possible to reduce the time delay and simplify the final routing results of this mapping. We define several new terms which are used to describe the problem. This work focuses on the mapping of flip-flops and their adjacent combinational parts in sequential circuits using L... View full abstract»

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  • Partitioning transition relations efficiently and automatically

    Publication Year: 1995, Page(s):106 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible perf... View full abstract»

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  • Test application time reduction for scan based sequential circuits

    Publication Year: 1995, Page(s):188 - 191
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-ato... View full abstract»

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  • Priority driven channel pin assignment

    Publication Year: 1995, Page(s):132 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    We present a polynomial time improvement of the linear channel pin assignment LCPA algorithms presented by Cai and Wong in 1990. We solve the LCPA problem according to minimum channel density under a special priority schedule subject to vertical constraints and flux. The priority driven linear channel pin assignment algorithm (PDCPA) reduces the channel height by an average of 17% without increasi... View full abstract»

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  • Scheduling conditional data-flow graphs with resource sharing

    Publication Year: 1995, Page(s):94 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper proposes pipeline scheduling algorithms for conditional branches and loop constructs, which are represented in the form of a conditional data-flow graph, where each node is associated with a condition vector. A novel data structure for dynamic resource sharing and a novel scheduling algorithm for resource sharing are proposed. Based on such a data structure and a modified rotation sched... View full abstract»

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  • Bus minimization and scheduling of multi-chip systems

    Publication Year: 1995, Page(s):40 - 45
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency... View full abstract»

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  • Optimization using implicit techniques for industrial designs

    Publication Year: 1995, Page(s):8 - 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The increasing complexity of industrial designs progressively obsoletes classical Boolean optimization techniques. Thus, the application of Binary Decision Diagrams in Logic Synthesis becomes an attractive alternative to push forward the design complexity. In this paper, we develop new Optimization techniques only based on implicit techniques; all steps were completely reformulated to provide a po... View full abstract»

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  • Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT

    Publication Year: 1995, Page(s):238 - 241
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A 2000 transistor p-well CMOS gate array has been designed for use as a teaching tool in the microelectronic engineering program at RIT. Students in microelectronic engineering study integrated circuit design and integrated circuit manufacturing starting in the first year of the five year program. The gate array is manufactured up to level 8 of the 11 level process by students in 5th year manufact... View full abstract»

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