Proceedings. Fifth Great Lakes Symposium on VLSI

16-18 March 1995

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  • Proceedings. Fifth Great Lakes Symposium on VLSI

    Publication Year: 1995
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1995
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    Freely Available from IEEE
  • Fast algorithm for performance-oriented Steiner routing

    Publication Year: 1995, Page(s):198 - 203
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (508 KB)

    We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a ... View full abstract»

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  • Pseudo-random behavioral ATPG

    Publication Year: 1995, Page(s):192 - 195
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (328 KB)

    This paper deals with a new approach for the Automatic Test Pattern Generation (ATPG) of circuits described from a behavioral point of view in VHDL. This approach is based on a pseudo-random process characterized by the fact that criteria for computing the test length and evaluating the quality of the generated data come from the field of software engineering. This paper presents the bases of this... View full abstract»

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  • Test application time reduction for scan based sequential circuits

    Publication Year: 1995, Page(s):188 - 191
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (336 KB)

    This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-ato... View full abstract»

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  • Statistical estimation of delay fault detectabilities and fault grading

    Publication Year: 1995, Page(s):184 - 187
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (336 KB)

    In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detecta... View full abstract»

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  • A personal computer based VLSI design curriculum

    Publication Year: 1995, Page(s):250 - 253
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (348 KB)

    We have developed a VLSI curriculum based on personal computers that can be used at teaching institutions and corporations alike. The curriculum consists of three courses: a capstone VLSI course, an analog design course, and an advanced digital design synthesis course. No workstations are necessary, laboratories may be given without teaching assistants, and the entire system be used with minimal r... View full abstract»

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  • Scheduling conditional data-flow graphs with resource sharing

    Publication Year: 1995, Page(s):94 - 97
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    This paper proposes pipeline scheduling algorithms for conditional branches and loop constructs, which are represented in the form of a conditional data-flow graph, where each node is associated with a condition vector. A novel data structure for dynamic resource sharing and a novel scheduling algorithm for resource sharing are proposed. Based on such a data structure and a modified rotation sched... View full abstract»

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  • An efficient heuristic approach on minimizing the number of feedthrough cells in standard cell placement

    Publication Year: 1995, Page(s):128 - 131
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Standard cell design style has been widely applied for the design automation of VLSI circuits because of the easy implementation of the layout design. Since the aim of most standard cell design systems is to minimize the utilization of chip area, the number of feedthrough cells in a standard cell layout will be further minimized to reduce the layout size. In this paper, first, we model a row assig... View full abstract»

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  • A protocol extraction strategy for control point insertion in design for test of transition signaling circuits

    Publication Year: 1995, Page(s):178 - 183
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (648 KB)

    Control/observation points have been used to detect undetectable faults in delay-insensitive/speed-independent circuits but no techniques exist so far for its use in reducing the test length. The major difficulty is in deriving a safe hazard-free test. A theory for control point insertion is presented for the purpose of test length reduction of transition signaling circuits. It is based on extract... View full abstract»

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  • Linking fabrication and parametric testing to VLSI design courses

    Publication Year: 1995, Page(s):246 - 249
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    The actual versus simulated performance of VLSI systems is dependent on the accuracy of the simulation model parameters and the soundness of the design rules used. Future process engineers must be schooled in VLSI design principles, while at the same time understanding the origin of the process based design rules and the statistical variation of device model parameters. This paper describes RIT's ... View full abstract»

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  • Synthesis of SEU-tolerant ASICs using concurrent error correction

    Publication Year: 1995, Page(s):90 - 93
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    We present a new design technique for the concurrent error correction of single event upsets in the memory elements of ASICs. The technique uses a single error correction/double error detection (SEC/DED) Hamming code to encode the content of the memory elements. The area and delay overhead and error-correction capability are optimized by partitioning the set of memory elements. Design experiments ... View full abstract»

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  • Performance driven standard-cell placement using the genetic algorithm

    Publication Year: 1995, Page(s):124 - 127
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumer... View full abstract»

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  • Using EDIF for software generation

    Publication Year: 1995, Page(s):172 - 175
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    With the advent of the FPGA and parallel microprocessors the need for practical codesign methods is becoming increasingly important. This paper proposes that codesign can be approached from existing hardware development tools. The paper also reports on the development of a software tool which uses EDIF to generate parallel, real-time C code. The view taken is that the problematic issues of codesig... View full abstract»

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  • Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test

    Publication Year: 1995, Page(s):242 - 245
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    The XC4000 Logic Cell Array Family of field programmable gate arrays developed by Xilinx includes support for the IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. Boundary-scan with built-in self-test is known to provide tests of high quality. The design and implementation of boundary-scan with built-in self-test that conforms fully to the IEEE Standard 1149.1 for the XC4000 d... View full abstract»

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  • Specification and synthesis of bounded indirection

    Publication Year: 1995, Page(s):86 - 89
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (396 KB)

    Bounded indirection is a restricted form of pointers, for system specification. It provides a mechanism for compact descriptions of many complex control structures, such as interrupts, continuations, and dynamic connections between machines. We describe three kinds of indirection-control state, value and net indirection-for use in different aspects of system description. Transformations on indirec... View full abstract»

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  • An efficient building block layout methodology for compact placement

    Publication Year: 1995, Page(s):118 - 123
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    In this paper, a new efficient methodology for building block layout is presented by using synthesis placement and compaction. The synthesis placement part of the methodology is based on a formal language called GEOMETRIA. The compaction part is based on geometric reshapings (gs) of blocks and the merging of the communication channels. Both reshaping and merging follow the VLSI regulations for leg... View full abstract»

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  • Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs

    Publication Year: 1995, Page(s):148 - 151
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB)

    We describe a technique for translating semicustom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based environment. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and tran... View full abstract»

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  • Modeling of communication protocols in VHDL

    Publication Year: 1995, Page(s):168 - 171
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. In this paper, the feasibility of using VHDL language to model communication protocols is examined, and a modeling methodology for such systems using VHDL is presented. We demonstrate our methodology on the transport protocol ISO/CCITT class... View full abstract»

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  • Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT

    Publication Year: 1995, Page(s):238 - 241
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (236 KB)

    A 2000 transistor p-well CMOS gate array has been designed for use as a teaching tool in the microelectronic engineering program at RIT. Students in microelectronic engineering study integrated circuit design and integrated circuit manufacturing starting in the first year of the five year program. The gate array is manufactured up to level 8 of the 11 level process by students in 5th year manufact... View full abstract»

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  • Symbolic execution of data paths

    Publication Year: 1995, Page(s):80 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitatio... View full abstract»

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  • Parallel hierarchical global routing for general cell layout

    Publication Year: 1995, Page(s):212 - 215
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (396 KB)

    In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine... View full abstract»

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  • A universal formalization of the effects of threshold voltages for discrete switch-level circuit models

    Publication Year: 1995, Page(s):266 - 271
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    In most discrete switch-level circuit models, switches, or transistors, are assumed to be perfect. That is, the effects of threshold voltages on signals are neglected in the discrete description of circuit behavior. In the formalization presented in this paper, the effects of imperfection of switches can be calculated separately from the abstracted circuit behavior. Furthermore, this formalization... View full abstract»

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  • Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions

    Publication Year: 1995, Page(s):112 - 116
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    The use of symbolic techniques to store integer-valued functions has been shown to be extremely effective in handling both transform matrices and spectral representations of large Boolean functions. In this paper we propose a novel application of symbolic Rademacher-Walsh spectral transforms to the evaluation of Boolean function correlation. In particular, we present an ADD-based algorithm to comp... View full abstract»

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  • Analyzing and verifying locally clocked circuits with the concurrency workbench

    Publication Year: 1995, Page(s):144 - 147
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB)

    Locally Clocked Modules (LCMs) allow asynchronous communication between synchronous computational elements. The concurrency workbench models concurrent systems in the CCS process algebra. We describe the use of the concurrency workbench to specify, simulate, and verify implementations of LCMs and discuss its application to the specification of asynchronous circuits View full abstract»

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