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Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on

Date 27-29 March 1995

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  • Proceedings. Sixteenth Conference on Advanced Research in VLSI

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (171 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (51 KB)
    Freely Available from IEEE
  • Efficient retiming under a general delay model

    Publication Year: 1995, Page(s):368 - 382
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    The polynomial-time retiming algorithms that were developed in the eighties assumed simple delay models that neglected several timing issues that arise in logic design. Recent retiming algorithms for more comprehensive delay models rely on non-linear formulations and run in worst-case exponential time using branch-and-bound techniques. In this paper, we investigate the retiming problem for edge-tr... View full abstract»

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  • An evaluation of bipartitioning techniques

    Publication Year: 1995, Page(s):383 - 402
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1188 KB)

    Logic partitioning is an important issue in VLSI CAD, and has been an active area of research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a methodology for determining the best mix of approaches... View full abstract»

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  • Abacus: a 1024 processor 8 ns SIMD array

    Publication Year: 1995, Page(s):28 - 40
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    Describes the Abacus machine at a number of levels. Presents the microarchitecture of the PE comprising the reconfigurable bit-parallel array, a set of arithmetic and communication primitives, details of the VLSI implementation, and system-level design issues of a high-speed SIMD array. The most concrete goal of the Abacus project was to design and build a machine that could be used by members of ... View full abstract»

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  • A multi-sender asynchronous extension to the AER protocol

    Publication Year: 1995, Page(s):158 - 169
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The address-event representation (AER) is an asynchronous point-to-point communications protocol for silicon neural systems. This paper describes an extension of the AER protocol that allows multiple AER senders to share a common bus. A fully-functional silicon implementation of the extended protocol is described, as well as a functional board-level system of several of these chips sharing a commo... View full abstract»

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  • Automatic synthesis of gate-level timed circuits with choice

    Publication Year: 1995, Page(s):42 - 58
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Our procedure begins with a textu... View full abstract»

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  • A 590,000 transistor 48,000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina

    Publication Year: 1995, Page(s):225 - 240
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    We present an experimental analog VLSI focal plane processor for the phototransduction, local gain control and edge enhancement of natural images. The single chip system incorporates 590,000 transistors in 48,000 pixels, and it has been fabricated on a 9.5×9.3 mm die in a 1.2 μm n-well double metal, double poly, digital oriented CMOS technology. The organization of the system abstracts fr... View full abstract»

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  • Bit-serial bidirectional A/D/A conversion

    Publication Year: 1995, Page(s):108 - 120
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A fault-tolerant VLSI architecture implementing a bi-directional bit-serial A/D/A (analog-to-digital and digital-to-analog) converter is presented. Both functions of algorithmic D/A conversion and successive approximation A/D conversion are combined into a single device, converting bits in the order from most to least significant. The MSB-first order allows for robust implementation, relatively in... View full abstract»

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  • Single-transistor transparent-latch clocking

    Publication Year: 1995, Page(s):331 - 341
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    We propose a single-phase clocking scheme for CMOS VLSI designs in which the traditional master-slave data-latches are replaced with transparent-latches where each transparent-latch is implemented using a single NMOS transistor. The clocking scheme places a constraint on the allowable width of the clock pulses which can be satisfied by a clock driver that is integrated with a dynamic buffer. Our e... View full abstract»

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  • High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips

    Publication Year: 1995, Page(s):91 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    VLSI chips suffer from exaggerated clock skew problems when the clock rate reaches several hundred MHz. To overcome this problem, back-propagating clock signals, the use of which is usually avoided (due to extended clock period) but known to be safe, can be exploited, resulting in a new pipelining method. We named this Counterflow-Clocked (C2) Pipelining. The major advantages of this ne... View full abstract»

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  • A technique for high-speed, fine-resolution pattern generation and its CMOS implementation

    Publication Year: 1995, Page(s):131 - 148
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This differenc... View full abstract»

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  • OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions

    Publication Year: 1995, Page(s):258 - 271
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Most behavioral synthesis tools perform limited architectural transformations to optimize hardware and power. Previously, researchers have proposed decomposition of multiplications into shifts and adds to achieve average savings of 2.5 times in hardware. In this paper, we propose a new program called OPTIMUS and related algorithms, that combine an architectural transformation procedure called numb... View full abstract»

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  • HAL: heuristic algorithms for layout synthesis

    Publication Year: 1995, Page(s):185 - 199
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    This paper describes graph theory based algorithms for layout synthesis of leaf cells. A new layout style termed 1-1/2-d layout style is used for the layouts. The transistors are aligned based on common poly gates or common circuit nodes between two sets of transistors. The two sets of transistors can be a set of PMOS transistors and a set of NMOS transistors, or both the sets can be formed by sim... View full abstract»

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  • Systematic objective-driven computer architecture optimization

    Publication Year: 1995, Page(s):286 - 300
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Computer designers now have more transistors and architectural alternatives than at any time. Computer-aided design tools automate much of the physical design process. However, few tools have been developed to help the computer architect specify near-optimal microarchitectural configurations in the early design stages. Such tools are needed to systematically guide the early design specifications s... View full abstract»

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  • Quasi-algebraic decompositions of switching functions

    Publication Year: 1995, Page(s):358 - 367
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    Brayton (1982-90) and others have developed a rich theory of decomposition of switching functions based on algebraic manipulations of monomials. In this theory, a product g(Xg)·h(Xh ) is algebraic if Xg∩Xh=Ø. There are efficient methods for determining if a function has an algebraic product. If a function does not have an algebraic prod... View full abstract»

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  • Analog VLSI circuits for manufacturing inspection

    Publication Year: 1995, Page(s):241 - 255
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    We present three types of analog VLSI circuits that can be used in manufacturing inspection systems. The first set of circuits performs an adaptive threshold of an input image. The second circuit uses morphological operations with programmable structuring elements to detect oriented edges. Both of these circuits can be used as high speed preprocessors for visual inspection of manufacturing process... View full abstract»

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  • Silicon VLSI processing architectures incorporating integrated optoelectronic devices

    Publication Year: 1995, Page(s):17 - 27
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Integrated optoelectronic interconnects offer a potentially lower cost, higher density alternative to wire-based technologies for I/O and inter-chip communication. This paper outlines two systems being designed at Georgia Tech which incorporate integrated thin film optoelectronic devices onto high throughput VLSI digital processors. The first system places an array of thin film detectors on top of... View full abstract»

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  • Distributed synchronous clocking

    Publication Year: 1995, Page(s):316 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    It is difficult to distribute a well aligned hardware clock throughout the physical extent of a synchronous processor. In this paper, we present an alternative approach-Distributed Synchronous Clocking-that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking. A network of independent oscillators takes the place of the centralized clock source, ... View full abstract»

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  • Non-dissipative rail drivers for adiabatic circuits

    Publication Year: 1995, Page(s):404 - 414
    Cited by:  Papers (11)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Energy dissipation of CMOS circuits is becoming a major concern in the design of digital systems. Earlier, we presented a new form of CMOS charge recovery logic (SCRL), with an energy dissipation per operation that falls linearly with operating frequency, as opposed to the constant energy required for conventional CMOS circuits. These SCRL circuits, along with most adiabatic circuit techniques pro... View full abstract»

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  • Array-of-arrays architecture for parallel floating point multiplication

    Publication Year: 1995, Page(s):150 - 157
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, simulated in HSpi... View full abstract»

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  • Low latency self-timed flow-through FIFOs

    Publication Year: 1995, Page(s):76 - 90
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    Self-timed flow-through FIFOs are constructed easily using only a single C-element as control for each stage of the FIFO. Throughput can be very high in this type of FIFO as the communication required to send new data to the FIFO is local to only the first element of the FIFO. Circuit density can also be high because the control overhead is very small. However because data must travel through ever... View full abstract»

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  • Combined DRAM and logic chip for massively parallel systems

    Publication Year: 1995, Page(s):4 - 16
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    A new 5 V 0.8 μm CMOS technology merges 100 K custom circuits and 4.5 Mb DRAM onto a single die that supports both high density memory and significant computing logic. One of the first chips built with this technology implements a unique Processor-In-Memory (PIM) computer architecture termed EXECUBE and has 8 separate 25 MHz CPU macros and 16 separate 32 K×9 b DRAM macros on a single die.... View full abstract»

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  • Dynamic CMOS circuit techniques for delay and power reduction in parallel adders

    Publication Year: 1995, Page(s):121 - 130
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The successful design of high-speed parallel adders depend mainly on fast calculation of carry signals. A technique based on combining Manchester-Carry chains (MCC) with Clock-and-Data pre-charged dynamic logic blocks (CDPD) is suggested and analysed. This technique, as well as pure MCC and CDPD techniques, was incorporated into the design of carry calculation trees. Simulations indicate that 11-2... View full abstract»

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  • On the performance of level-clocked circuits

    Publication Year: 1995, Page(s):342 - 356
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Although it is well-known that substituting level-sensitive latches for edge-triggered registers can boost circuit performance, results of measuring the performance gained by using latches in real circuits-when retiming is used to optimize the performance of both types of circuits-have been disappointing. In this paper we re-examine the speedup that can be expected from using latches and develop u... View full abstract»

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