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Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Date 18-20 Jan. 1995

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Displaying Results 1 - 25 of 42
  • Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (68 KB)
    Freely Available from IEEE
  • Yield analysis of fault-tolerant multichip module systems for massively parallel computing

    Publication Year: 1995, Page(s):308 - 317
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    This paper presents analytical models for evaluating the overall yield of systems manufactured using fault-tolerant multichip modules (MCMs) for massively parallel computing. In the proposed approaches, we employ a novel Markov model to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests. Several strategies for appropriately ... View full abstract»

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  • Yield and performance issues in fault-tolerant WSI array architectures

    Publication Year: 1995, Page(s):318 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this paper, a simple but efficient reconfiguration algorithm and placement algorithm are proposed to enhance the manufacturing yield of WSI array processors at low performance degradation. The low performance degradation is significant for high-performance WSI arrays. The objective of our reconfiguration strategy is to achieve better utilization of good spares, while also ensuring that the rest... View full abstract»

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  • The impact of floorplanning on the yield of fault-tolerant ICs

    Publication Year: 1995, Page(s):329 - 338
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Until now, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips View full abstract»

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  • Towards WSI testable devices: an improved scan insertion technique

    Publication Year: 1995, Page(s):339 - 348
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The aim of this paper is to introduce a different approach for the application of the partial scan methodology into a circuit to provide the most convenient solution in terms of overheads and performances. First testability analysis, based on new testability conditions, is performed to identify areas that are hard-to-test; then the partial scan technique is applied in a modified fashion only to th... View full abstract»

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  • The digital micromirror device for projection display

    Publication Year: 1995, Page(s):43 - 51
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The digital micromirror device is the product of a technological development program which began at Texas instruments over 15 years ago. It is a micro-electromechanical system, MEMS, device which includes an array of mirrors fabricated above CMOS static RAM memory elements. Rapid switching of the diagonally hinged mirrors allows incident light to be modulated to form the highest quality video imag... View full abstract»

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  • Large integrated crossbar switch

    Publication Year: 1995, Page(s):217 - 227
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper describes the design of a 256×256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant m... View full abstract»

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  • Reconfiguration and routing in defective WSI processor arrays

    Publication Year: 1995, Page(s):298 - 307
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    In this paper we discuss an alternative to the traditional approach of reconfiguration and adaptive routing. We first reconfigure a faulty processor array, not with the goal of producing a regular topology, but rather to increase the bandwidth of the network (increase the conductivity of a networks defined by percolation theory). This reconfiguration will provide us with a network which is disorde... View full abstract»

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  • Test vehicle for a wafer-scale field programmable gate array

    Publication Year: 1995, Page(s):33 - 42
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect fr... View full abstract»

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  • A life cycle model for the WSI associative string processor (WASP)

    Publication Year: 1995, Page(s):52 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The paper presents a comprehensive life cycle model for the WSI associative string processor (WASP) which simulates the manufacture, acceptance, and operational life of a hypothetical target device. After 100,000 hours of continuous simulated operation, the device is shown to support an average of over 8.5 K APEs per wafer under a worst case scenario, and an average of over 12 K APEs per wafer und... View full abstract»

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  • Optimal switching networks for WSI architectures with fault tolerant path routing

    Publication Year: 1995, Page(s):153 - 162
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    This paper presents an approach for designing fault-tolerant routers for signal distribution by redundant path routing in wafer scale integration (WSI) architectures. The conditions by which a router can be designed using spare lines (tracks) such that the probability of successfully routing all input lines in the prescribed order and in the presence of faults in switches can be optimized (optimal... View full abstract»

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  • Defect-tolerant processor arrays

    Publication Year: 1995, Page(s):228 - 237
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper we describe the design and optimization of a defect tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number of operations per memory word. The optimization includes trade-offs between number of processors, amount of local memory, performance and topology of the interconnection network and yield. The yield analysis consi... View full abstract»

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  • The influence of process parameter variations on the signal distribution behaviour of wafer scale integration devices

    Publication Year: 1995, Page(s):248 - 257
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. Within this paper, simulations, based on real measured process parameters, are undertaken to show ... View full abstract»

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  • Innovative design of CMOS fault tolerant structures

    Publication Year: 1995, Page(s):267 - 276
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and the complemented form of the desired output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they... View full abstract»

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  • High-speed interconnections using true single-phase clocking

    Publication Year: 1995, Page(s):258 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Long interconnections in wafer scale systems can severely limit their operating frequency and the speed of data transfers between distant components. One way to significantly improve these parameters consists in converting long wires into synchronous pipelines. For this purpose, a high-speed pipeline stage has been designed using a state-of-the-art circuit design methodology: single-phase clocking... View full abstract»

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  • A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

    Publication Year: 1995, Page(s):101 - 110
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. One of them, the mesh-connected processor arrays model based on single-track switches, has been proposed in. The model has the advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration ... View full abstract»

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  • Wafer-scale embedded-MPC modules for cost-effective image processing systems

    Publication Year: 1995, Page(s):1 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    In this paper the author sets out to explore the cost-effectiveness of wafer-scale embedded-MPC (massively parallel computers) modules for cost-effective image processing systems. Design considerations for modular-MPC accelerators for image processing workstations have provided the basis for a case-study. It has been demonstrated that, with the WSI ASP modules being developed by Aspex Microsystems... View full abstract»

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  • A substrate area estimation technique for Multi-Chip Modules

    Publication Year: 1995, Page(s):134 - 142
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    The estimation of substrate areas of Multi-Chip Modules is a very important task in the partitioning of a MCM based electronic system. Moreover, due to the similarities between large area MCMs (hybrid-WSI) and monolithic-WSI it has become increasingly clear that regular structures are significantly better suited than others for implementation in these technologies. This paper introduces a substrat... View full abstract»

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  • Teaching the efficient use of hybrid-WSI technology

    Publication Year: 1995, Page(s):72 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    It has become increasingly clear that electronic packaging sets important bounds on system cost and performance. As is evident from Mukund et al. (1993) and Habiger et al. (1993), WSI and hybrid WSI design has recently become a major focus of research activities. Due to its inherent interdisciplinarity a subject like WSI design or in more general electronic packaging does not easily fit into the t... View full abstract»

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  • An evaluation of defect and fault tolerant signal routing strategies for WASP devices

    Publication Year: 1995, Page(s):277 - 287
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the t... View full abstract»

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  • Stream oriented fault tolerant array

    Publication Year: 1995, Page(s):172 - 181
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    This paper describes the architecture of stream oriented fault tolerant array. Stream is a dynamically established one to one communication path among processing cells to make a wide variety of parallel applications possible. Fault tolerance is required for communication paths as well as the processor cell. Our architecture uses majority voting and cell reliability assessment. Our fault tolerant a... View full abstract»

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  • Time redundancy for error detecting neural networks

    Publication Year: 1995, Page(s):111 - 121
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Concurrent error detection at an architectural level is often a basic requirement to achieve fault tolerance in neural networks for mission-critical applications. Time redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic are analyzed as low-cost approaches to concurrent error detection. Different architectu... View full abstract»

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  • A hierarchical redundant cube-connected cycle for WSI yield enhancement

    Publication Year: 1995, Page(s):163 - 171
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance and in yield analysis. We show a sem... View full abstract»

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  • The WASP-3 monolithic-WSI massively parallel processor

    Publication Year: 1995, Page(s):22 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The paper is a progress report on the WASP development programme. It reports on the successful conclusion of a wafer-scale hybridisation experiment, designed as `proof-of-principle' of the wafer stacking procedure used in the mating of WASP-3 wafers and their HDI (High Density Interconnect) layer. WASPS wafers have completed manufacture and are now undergoing final assembly prior to commencing tes... View full abstract»

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