Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

18-20 Jan. 1995

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  • Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

    Publication Year: 1995
    Request permission for commercial reuse | |PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Silicon hybrid wafer scale integration (SHWSI)-a discrete integrated circuit (IC) interconnect scheme

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (69 KB)

    Summary form only given. A silicon-hybrid wafer-scale integration (SHWSI) fabrication technology has been developed to interconnect discrete integrated circuit (IC) die. As a demonstration of this technology, a simple, 3-bit, asynchronous binary counter circuit was implemented using two discrete complementary metal-oxide semiconductor (CMOS) IC die that were independently fabricated by the Metal-O... View full abstract»

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  • 21st century gigascale integration (GSI)

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (67 KB)

    Summary form only given. Throughout the past 35 years integrated electronics has advanced at a pace unmatched in technological history. Minimum feature sizes have declined by about a factor of 1/50, switching energy of a binary transition has decreased by approximately 1/105 times, the number of transistors per chip has multiplied by around 50/spl times/106, the price range of a chip has remained ... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • An experimental fault-tolerant active substrate MPC MCM using standard gate array technology

    Publication Year: 1995, Page(s):197 - 206
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    The Massively Parallel Computing (MPC) arena continues to demand ever more powerful and compact building-blocks, especially for the construction of embedded-MPC systems. Multi-Chip Modules (MCMs) offer a means of implementing such building-blocks, but have been shown to suffer from cost and delivery problems at the complexity levels required. As these problems stem from infant die mortality, assem... View full abstract»

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  • A cache coherency protocol for multiprocessor chip

    Publication Year: 1995, Page(s):238 - 247
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    In this paper, we propose a snoop cache protocol for the WSI implementation which minimizes the accesses to the shared memory. In the modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulatio... View full abstract»

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  • An evaluation of defect and fault tolerant signal routing strategies for WASP devices

    Publication Year: 1995, Page(s):277 - 287
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the t... View full abstract»

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  • A comparison of VLSI, MCM and WSI technologies

    Publication Year: 1995, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    VLSI, MCM and WSI technologies are compared on the basis of silicon area, substrate size and power consumption. Theoretical estimates for these parameters are developed and then illustrated by examining the design of a radix-4 FFT butterfly processing element. The MCM implementation should cost the least in production, but it is the largest and consumes the most power View full abstract»

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  • Defect-tolerant processor arrays

    Publication Year: 1995, Page(s):228 - 237
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    In this paper we describe the design and optimization of a defect tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number of operations per memory word. The optimization includes trade-offs between number of processors, amount of local memory, performance and topology of the interconnection network and yield. The yield analysis consi... View full abstract»

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  • Innovative design of CMOS fault tolerant structures

    Publication Year: 1995, Page(s):267 - 276
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and the complemented form of the desired output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they... View full abstract»

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  • The digital micromirror device for projection display

    Publication Year: 1995, Page(s):43 - 51
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    The digital micromirror device is the product of a technological development program which began at Texas instruments over 15 years ago. It is a micro-electromechanical system, MEMS, device which includes an array of mirrors fabricated above CMOS static RAM memory elements. Rapid switching of the diagonally hinged mirrors allows incident light to be modulated to form the highest quality video imag... View full abstract»

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  • A wafer-scale ATM switching system based on the Manhattan-street network

    Publication Year: 1995, Page(s):182 - 190
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    This paper presents a defect-tolerant wafer-scale switching system for highspeed ATM communication applications. The network topology is based on the Manhattan-street Network (MSN) which has a torus structure. In the MSN, a cell is temporarily misrouted (deflected) through the alternate output of a node if the desired output is not available. This feature, and the regularity of the MSN structure w... View full abstract»

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  • Test strategies for multi-chip modules based on economics considerations

    Publication Year: 1995, Page(s):371 - 378
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (268 KB)

    This paper describes an economics based methodology for the investigation of test strategies for multi-chip modules. Multi chip module technologies offer a way of overcoming the interconnection bottleneck which can be a problem with conventional interconnect technologies as the complexity of integrated circuits increases through the use of rapidly diminishing feature sizes. The use of multi-chip m... View full abstract»

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  • A RAM-based neural network architecture for wafer scale integration

    Publication Year: 1995, Page(s):82 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    The paper presents the design of a RAM-based Artificial Neural Network (ANN) architecture which is particularly well suited to WSI implementation. Using data from a VLSI test chip and prototype system manufactured in 1993, we compare the performance and complexity of FPGA, VLSI and WSI RAM-based neural systems View full abstract»

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  • Large integrated crossbar switch

    Publication Year: 1995, Page(s):217 - 227
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (536 KB)

    This paper describes the design of a 256×256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant m... View full abstract»

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  • High-speed interconnections using true single-phase clocking

    Publication Year: 1995, Page(s):258 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (348 KB)

    Long interconnections in wafer scale systems can severely limit their operating frequency and the speed of data transfers between distant components. One way to significantly improve these parameters consists in converting long wires into synchronous pipelines. For this purpose, a high-speed pipeline stage has been designed using a state-of-the-art circuit design methodology: single-phase clocking... View full abstract»

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  • Reconfiguration and routing in defective WSI processor arrays

    Publication Year: 1995, Page(s):298 - 307
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    In this paper we discuss an alternative to the traditional approach of reconfiguration and adaptive routing. We first reconfigure a faulty processor array, not with the goal of producing a regular topology, but rather to increase the bandwidth of the network (increase the conductivity of a networks defined by percolation theory). This reconfiguration will provide us with a network which is disorde... View full abstract»

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  • Complex-argument universal nonlinear cell for rapid prototyping wafer architecture

    Publication Year: 1995, Page(s):12 - 21
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    The development of generic cells to perform linear and nonlinear arithmetic is critical to successful WSI implementations of signal and image processing algorithms. Our WARP wafer architecture deploys generic cells, thereby offering the capability of mapping a wide variety of computational algorithms on to the same pool of resources. This paper presents a further advance in this direction. Specifi... View full abstract»

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  • Test vehicle for a wafer-scale field programmable gate array

    Publication Year: 1995, Page(s):33 - 42
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect fr... View full abstract»

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  • CCD wafer scale integration

    Publication Year: 1995, Page(s):123 - 133
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (724 KB)

    Wafer scale CCD photodetector arrays of 26 million pixels or more are being fabricated on a limited production basis today. This paper provides an introduction to CCD wafer scale integration with an emphasis on common wafer scale CCD design architectures, applications and fabrication processes. Examples of wafer scale CCD products are reviewed, and a triple poly, double metal wafer scale CCD fabri... View full abstract»

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  • Stream oriented fault tolerant array

    Publication Year: 1995, Page(s):172 - 181
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (280 KB)

    This paper describes the architecture of stream oriented fault tolerant array. Stream is a dynamically established one to one communication path among processing cells to make a wide variety of parallel applications possible. Fault tolerance is required for communication paths as well as the processor cell. Our architecture uses majority voting and cell reliability assessment. Our fault tolerant a... View full abstract»

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  • Algorithms for arithmetic operation in a systolic array of single-bit processor (SASP)

    Publication Year: 1995, Page(s):359 - 370
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    Algorithms for binary integer arithmetic in a Systolic Array of Single-bit Processor (SASP), designed for implementation in wafer scale integration (WSI), are presented. The processing elements (PE), operated in a Single instruction Multiple Data (SIMD) mode, each contains a single-bit arithmetic and logic unit (ALU). The salient feature of the developed algorithms is in the use of the primitive A... View full abstract»

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  • Teaching the efficient use of hybrid-WSI technology

    Publication Year: 1995, Page(s):72 - 81
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (584 KB)

    It has become increasingly clear that electronic packaging sets important bounds on system cost and performance. As is evident from Mukund et al. (1993) and Habiger et al. (1993), WSI and hybrid WSI design has recently become a major focus of research activities. Due to its inherent interdisciplinarity a subject like WSI design or in more general electronic packaging does not easily fit into the t... View full abstract»

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  • Time redundancy for error detecting neural networks

    Publication Year: 1995, Page(s):111 - 121
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB)

    Concurrent error detection at an architectural level is often a basic requirement to achieve fault tolerance in neural networks for mission-critical applications. Time redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic are analyzed as low-cost approaches to concurrent error detection. Different architectu... View full abstract»

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  • Optimal switching networks for WSI architectures with fault tolerant path routing

    Publication Year: 1995, Page(s):153 - 162
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB)

    This paper presents an approach for designing fault-tolerant routers for signal distribution by redundant path routing in wafer scale integration (WSI) architectures. The conditions by which a router can be designed using spare lines (tracks) such that the probability of successfully routing all input lines in the prescribed order and in the presence of faults in switches can be optimized (optimal... View full abstract»

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