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Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

18-20 Jan. 1995

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Displaying Results 1 - 25 of 42
  • Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Silicon hybrid wafer scale integration (SHWSI)-a discrete integrated circuit (IC) interconnect scheme

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB)

    Summary form only given. A silicon-hybrid wafer-scale integration (SHWSI) fabrication technology has been developed to interconnect discrete integrated circuit (IC) die. As a demonstration of this technology, a simple, 3-bit, asynchronous binary counter circuit was implemented using two discrete complementary metal-oxide semiconductor (CMOS) IC die that were independently fabricated by the Metal-O... View full abstract»

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  • 21st century gigascale integration (GSI)

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (67 KB)

    Summary form only given. Throughout the past 35 years integrated electronics has advanced at a pace unmatched in technological history. Minimum feature sizes have declined by about a factor of 1/50, switching energy of a binary transition has decreased by approximately 1/105 times, the number of transistors per chip has multiplied by around 50/spl times/106, the price range of a chip has remained ... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • A life cycle model for the WSI associative string processor (WASP)

    Publication Year: 1995, Page(s):52 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The paper presents a comprehensive life cycle model for the WSI associative string processor (WASP) which simulates the manufacture, acceptance, and operational life of a hypothetical target device. After 100,000 hours of continuous simulated operation, the device is shown to support an average of over 8.5 K APEs per wafer under a worst case scenario, and an average of over 12 K APEs per wafer und... View full abstract»

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  • The digital micromirror device for projection display

    Publication Year: 1995, Page(s):43 - 51
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The digital micromirror device is the product of a technological development program which began at Texas instruments over 15 years ago. It is a micro-electromechanical system, MEMS, device which includes an array of mirrors fabricated above CMOS static RAM memory elements. Rapid switching of the diagonally hinged mirrors allows incident light to be modulated to form the highest quality video imag... View full abstract»

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  • Test vehicle for a wafer-scale field programmable gate array

    Publication Year: 1995, Page(s):33 - 42
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect fr... View full abstract»

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  • The WASP-3 monolithic-WSI massively parallel processor

    Publication Year: 1995, Page(s):22 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The paper is a progress report on the WASP development programme. It reports on the successful conclusion of a wafer-scale hybridisation experiment, designed as `proof-of-principle' of the wafer stacking procedure used in the mating of WASP-3 wafers and their HDI (High Density Interconnect) layer. WASPS wafers have completed manufacture and are now undergoing final assembly prior to commencing tes... View full abstract»

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  • Complex-argument universal nonlinear cell for rapid prototyping wafer architecture

    Publication Year: 1995, Page(s):12 - 21
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The development of generic cells to perform linear and nonlinear arithmetic is critical to successful WSI implementations of signal and image processing algorithms. Our WARP wafer architecture deploys generic cells, thereby offering the capability of mapping a wide variety of computational algorithms on to the same pool of resources. This paper presents a further advance in this direction. Specifi... View full abstract»

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  • Wafer-scale embedded-MPC modules for cost-effective image processing systems

    Publication Year: 1995, Page(s):1 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    In this paper the author sets out to explore the cost-effectiveness of wafer-scale embedded-MPC (massively parallel computers) modules for cost-effective image processing systems. Design considerations for modular-MPC accelerators for image processing workstations have provided the basis for a case-study. It has been demonstrated that, with the WSI ASP modules being developed by Aspex Microsystems... View full abstract»

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  • A post-processing algorithm for short-circuit defect sensitivity reduction in VLSI layouts

    Publication Year: 1995, Page(s):288 - 297
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Yield enhancement may well be regarded as the quintessential objective in microelectronic manufacturing. With diminishing feature size and increasing die area the amount of functional silicon on a die is too expensive to discard in the event of short-circuit and open-circuit faults. Designing chips with high tolerance against faults, therefore, holds a great promise for profitable manufacturing in... View full abstract»

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  • An evaluation of defect and fault tolerant signal routing strategies for WASP devices

    Publication Year: 1995, Page(s):277 - 287
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the t... View full abstract»

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  • Teaching the efficient use of hybrid-WSI technology

    Publication Year: 1995, Page(s):72 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    It has become increasingly clear that electronic packaging sets important bounds on system cost and performance. As is evident from Mukund et al. (1993) and Habiger et al. (1993), WSI and hybrid WSI design has recently become a major focus of research activities. Due to its inherent interdisciplinarity a subject like WSI design or in more general electronic packaging does not easily fit into the t... View full abstract»

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  • Yield analysis of fault-tolerant multichip module systems for massively parallel computing

    Publication Year: 1995, Page(s):308 - 317
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    This paper presents analytical models for evaluating the overall yield of systems manufactured using fault-tolerant multichip modules (MCMs) for massively parallel computing. In the proposed approaches, we employ a novel Markov model to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests. Several strategies for appropriately ... View full abstract»

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  • Test strategies for multi-chip modules based on economics considerations

    Publication Year: 1995, Page(s):371 - 378
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    This paper describes an economics based methodology for the investigation of test strategies for multi-chip modules. Multi chip module technologies offer a way of overcoming the interconnection bottleneck which can be a problem with conventional interconnect technologies as the complexity of integrated circuits increases through the use of rapidly diminishing feature sizes. The use of multi-chip m... View full abstract»

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  • A substrate area estimation technique for Multi-Chip Modules

    Publication Year: 1995, Page(s):134 - 142
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    The estimation of substrate areas of Multi-Chip Modules is a very important task in the partitioning of a MCM based electronic system. Moreover, due to the similarities between large area MCMs (hybrid-WSI) and monolithic-WSI it has become increasingly clear that regular structures are significantly better suited than others for implementation in these technologies. This paper introduces a substrat... View full abstract»

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  • A hierarchical redundant cube-connected cycle for WSI yield enhancement

    Publication Year: 1995, Page(s):163 - 171
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance and in yield analysis. We show a sem... View full abstract»

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  • A comparison of VLSI, MCM and WSI technologies

    Publication Year: 1995, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    VLSI, MCM and WSI technologies are compared on the basis of silicon area, substrate size and power consumption. Theoretical estimates for these parameters are developed and then illustrated by examining the design of a radix-4 FFT butterfly processing element. The MCM implementation should cost the least in production, but it is the largest and consumes the most power View full abstract»

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  • Large integrated crossbar switch

    Publication Year: 1995, Page(s):217 - 227
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper describes the design of a 256×256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant m... View full abstract»

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  • An easily-testable cube-connected cycles structure

    Publication Year: 1995, Page(s):349 - 358
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper, we present an easily-testable cube-connected cycles (CCC) structure for VLSI/WSI implementation. The concept of boundary scan is used to provide test vectors and capture the resulting responses. A simple design modification is made to considerably reduce the test application time. The test access port of each processing element (PE) is utilized to perform comparisons between PEs. Si... View full abstract»

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  • Innovative design of CMOS fault tolerant structures

    Publication Year: 1995, Page(s):267 - 276
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and the complemented form of the desired output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they... View full abstract»

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  • Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design

    Publication Year: 1995, Page(s):62 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Devices are becoming available whose inherent switching speeds are approaching only a few picoseconds. CMOS FET devices with 0.12 micron channel length have exhibited fT values of 89 GHz. SiGe HBTs have been demonstrated with an fT of 117 GHz. InP/InGaAs/AlGaAs HBT's have exhibited an fT of 200 GHz, with minimum feature sizes that are above one micron. InGaAs/AlGaA... View full abstract»

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  • Reconfiguration and routing in defective WSI processor arrays

    Publication Year: 1995, Page(s):298 - 307
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    In this paper we discuss an alternative to the traditional approach of reconfiguration and adaptive routing. We first reconfigure a faulty processor array, not with the goal of producing a regular topology, but rather to increase the bandwidth of the network (increase the conductivity of a networks defined by percolation theory). This reconfiguration will provide us with a network which is disorde... View full abstract»

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  • A RAM-based neural network architecture for wafer scale integration

    Publication Year: 1995, Page(s):82 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The paper presents the design of a RAM-based Artificial Neural Network (ANN) architecture which is particularly well suited to WSI implementation. Using data from a VLSI test chip and prototype system manufactured in 1993, we compare the performance and complexity of FPGA, VLSI and WSI RAM-based neural systems View full abstract»

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  • Yield and performance issues in fault-tolerant WSI array architectures

    Publication Year: 1995, Page(s):318 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this paper, a simple but efficient reconfiguration algorithm and placement algorithm are proposed to enhance the manufacturing yield of WSI array processors at low performance degradation. The low performance degradation is significant for high-performance WSI arrays. The objective of our reconfiguration strategy is to achieve better utilization of good spares, while also ensuring that the rest... View full abstract»

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