By Topic

Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

18-20 Jan. 1995

Filter Results

Displaying Results 1 - 25 of 42
  • Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Silicon hybrid wafer scale integration (SHWSI)-a discrete integrated circuit (IC) interconnect scheme

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB)

    Summary form only given. A silicon-hybrid wafer-scale integration (SHWSI) fabrication technology has been developed to interconnect discrete integrated circuit (IC) die. As a demonstration of this technology, a simple, 3-bit, asynchronous binary counter circuit was implemented using two discrete complementary metal-oxide semiconductor (CMOS) IC die that were independently fabricated by the Metal-O... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 21st century gigascale integration (GSI)

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (67 KB)

    Summary form only given. Throughout the past 35 years integrated electronics has advanced at a pace unmatched in technological history. Minimum feature sizes have declined by about a factor of 1/50, switching energy of a binary transition has decreased by approximately 1/105 times, the number of transistors per chip has multiplied by around 50/spl times/106, the price range of a chip has remained ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (68 KB)
    Freely Available from IEEE
  • The WASP-3 monolithic-WSI massively parallel processor

    Publication Year: 1995, Page(s):22 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The paper is a progress report on the WASP development programme. It reports on the successful conclusion of a wafer-scale hybridisation experiment, designed as `proof-of-principle' of the wafer stacking procedure used in the mating of WASP-3 wafers and their HDI (High Density Interconnect) layer. WASPS wafers have completed manufacture and are now undergoing final assembly prior to commencing tes... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect-tolerant processor arrays

    Publication Year: 1995, Page(s):228 - 237
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper we describe the design and optimization of a defect tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number of operations per memory word. The optimization includes trade-offs between number of processors, amount of local memory, performance and topology of the interconnection network and yield. The yield analysis consi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards WSI testable devices: an improved scan insertion technique

    Publication Year: 1995, Page(s):339 - 348
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The aim of this paper is to introduce a different approach for the application of the partial scan methodology into a circuit to provide the most convenient solution in terms of overheads and performances. First testability analysis, based on new testability conditions, is performed to identify areas that are hard-to-test; then the partial scan technique is applied in a modified fashion only to th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Complex-argument universal nonlinear cell for rapid prototyping wafer architecture

    Publication Year: 1995, Page(s):12 - 21
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The development of generic cells to perform linear and nonlinear arithmetic is critical to successful WSI implementations of signal and image processing algorithms. Our WARP wafer architecture deploys generic cells, thereby offering the capability of mapping a wide variety of computational algorithms on to the same pool of resources. This paper presents a further advance in this direction. Specifi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Time redundancy for error detecting neural networks

    Publication Year: 1995, Page(s):111 - 121
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Concurrent error detection at an architectural level is often a basic requirement to achieve fault tolerance in neural networks for mission-critical applications. Time redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic are analyzed as low-cost approaches to concurrent error detection. Different architectu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Large integrated crossbar switch

    Publication Year: 1995, Page(s):217 - 227
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper describes the design of a 256×256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The impact of floorplanning on the yield of fault-tolerant ICs

    Publication Year: 1995, Page(s):329 - 338
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Until now, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wafer-scale embedded-MPC modules for cost-effective image processing systems

    Publication Year: 1995, Page(s):1 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    In this paper the author sets out to explore the cost-effectiveness of wafer-scale embedded-MPC (massively parallel computers) modules for cost-effective image processing systems. Design considerations for modular-MPC accelerators for image processing workstations have provided the basis for a case-study. It has been demonstrated that, with the WSI ASP modules being developed by Aspex Microsystems... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

    Publication Year: 1995, Page(s):101 - 110
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. One of them, the mesh-connected processor arrays model based on single-track switches, has been proposed in. The model has the advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield improvement of a large area magnetic field sensor array design using redundancy schemes

    Publication Year: 1995, Page(s):207 - 216
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Design of a Large Area Magnetic Field Sensor Array (LAMSA) using redundancy schemes concurrently with the laser link technology for fault repairs is presented. Experimental results obtained on a laser restructurable subarray of three magnetic field sensor cells are shown. An experimental yield measurement method to determine parameters of two yield detractors is described. These parameters obtaine... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield and performance issues in fault-tolerant WSI array architectures

    Publication Year: 1995, Page(s):318 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this paper, a simple but efficient reconfiguration algorithm and placement algorithm are proposed to enhance the manufacturing yield of WSI array processors at low performance degradation. The low performance degradation is significant for high-performance WSI arrays. The objective of our reconfiguration strategy is to achieve better utilization of good spares, while also ensuring that the rest... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An evaluation of defect and fault tolerant signal routing strategies for WASP devices

    Publication Year: 1995, Page(s):277 - 287
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A RAM-based neural network architecture for wafer scale integration

    Publication Year: 1995, Page(s):82 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The paper presents the design of a RAM-based Artificial Neural Network (ANN) architecture which is particularly well suited to WSI implementation. Using data from a VLSI test chip and prototype system manufactured in 1993, we compare the performance and complexity of FPGA, VLSI and WSI RAM-based neural systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A wafer-scale ATM switching system based on the Manhattan-street network

    Publication Year: 1995, Page(s):182 - 190
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    This paper presents a defect-tolerant wafer-scale switching system for highspeed ATM communication applications. The network topology is based on the Manhattan-street Network (MSN) which has a torus structure. In the MSN, a cell is temporarily misrouted (deflected) through the alternate output of a node if the desired output is not available. This feature, and the regularity of the MSN structure w... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test vehicle for a wafer-scale field programmable gate array

    Publication Year: 1995, Page(s):33 - 42
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect fr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A cache coherency protocol for multiprocessor chip

    Publication Year: 1995, Page(s):238 - 247
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, we propose a snoop cache protocol for the WSI implementation which minimizes the accesses to the shared memory. In the modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulatio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An easily-testable cube-connected cycles structure

    Publication Year: 1995, Page(s):349 - 358
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper, we present an easily-testable cube-connected cycles (CCC) structure for VLSI/WSI implementation. The concept of boundary scan is used to provide test vectors and capture the resulting responses. A simple design modification is made to considerably reduce the test application time. The test access port of each processing element (PE) is utilized to perform comparisons between PEs. Si... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A post-processing algorithm for short-circuit defect sensitivity reduction in VLSI layouts

    Publication Year: 1995, Page(s):288 - 297
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Yield enhancement may well be regarded as the quintessential objective in microelectronic manufacturing. With diminishing feature size and increasing die area the amount of functional silicon on a die is too expensive to discard in the event of short-circuit and open-circuit faults. Designing chips with high tolerance against faults, therefore, holds a great promise for profitable manufacturing in... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A module-sliced high yield WSI memory system

    Publication Year: 1995, Page(s):91 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Low yield is one of the practical difficulties in the design of WSI systems, such as array processors or WSI memories. The conventional row-column memory cells organization is not suitable for WSI memory systems due to the long signal delay on a wafer and a much more complicate procedure for replacing a defect row or column of memory cell. To alleviate these difficulties, a module-sliced WSI memor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A comparison of VLSI, MCM and WSI technologies

    Publication Year: 1995, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    VLSI, MCM and WSI technologies are compared on the basis of silicon area, substrate size and power consumption. Theoretical estimates for these parameters are developed and then illustrated by examining the design of a radix-4 FFT butterfly processing element. The MCM implementation should cost the least in production, but it is the largest and consumes the most power View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The digital micromirror device for projection display

    Publication Year: 1995, Page(s):43 - 51
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The digital micromirror device is the product of a technological development program which began at Texas instruments over 15 years ago. It is a micro-electromechanical system, MEMS, device which includes an array of mirrors fabricated above CMOS static RAM memory elements. Rapid switching of the diagonally hinged mirrors allows incident light to be modulated to form the highest quality video imag... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.