[1992] Proceedings International Conference on Wafer Scale Integration

22-24 Jan. 1992

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Displaying Results 1 - 25 of 41
  • Keynote address: critical issues in wafer scale design

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (15 KB)

    Summary form only given. The author discusses critical barriers to the further developments of wafer-scale design technology and its successful transfer to industry. These include: 1) difficulty in obtaining multireticle stepper lithography for sub 2-micron fabrication, (2) limitation to two levels of metal and resulting problems in power and clock distribution, (3) excessive turnaround time becau... View full abstract»

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  • The impact of the declining cost per MIPS

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (12 KB)

    Summary form only given, as follows. The personal computer (PC) cost per million instructions per second (MIPS) is projected to decline to less than $100.00 per MIPS by 1995, and to a few dollars per MIPS by 2010. This cost reduction will be achieved through very large scale integration, multi-chip modules, and operating voltage reduction. Cheap computing power will allow many problems currently h... View full abstract»

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  • Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2)

    Publication Year: 1992
    Request permission for commercial reuse | |PDF file iconPDF (66 KB)
    Freely Available from IEEE
  • HASP-1002: a hybrid wafer scale associative string processor

    Publication Year: 1992, Page(s):124 - 133
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (476 KB)

    The authors introduce and evaluate a multichip module produced in hybrid-WSI (wafer scale integration) technology embedded for real-time signal and data processing. The benefits and potential of the technologies of the HASP-1002 hybrid-WSI device are shown. The combination of improvements of the size-performance and the cost-performance trade-offs underlines the vitality of hybrid-WSI technologies... View full abstract»

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  • The application of yield modelling to the WASP parallel processing architecture

    Publication Year: 1992, Page(s):115 - 123
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    The authors address yield modeling considerations and their impact upon the floorplanning and defect tolerance strategies of the WSI Associative String Processor (WASP) architecture. A fully parameterized, detailed yield model for the WASP architecture has been presented previously. This yield model has been developed further and applied to the various design options for future WASP devices. Using... View full abstract»

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  • WASP 3: A real time signal and data processor

    Publication Year: 1992, Page(s):105 - 114
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (560 KB)

    The WASP (WSI Associative String Processor) project is aimed at the production of embedded wafer-scale MPC (massively parallel computer) components, with performance, size, weight, power dissipation, and reliability parameters that are far superior to those obtained using conventional technology. WASP 3 heralds the progression to the WASP experimental program into its application demonstrator phas... View full abstract»

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  • A 3-D WASP module for real-time signal and data processing

    Publication Year: 1992, Page(s):95 - 104
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (532 KB)

    Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost a... View full abstract»

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  • Fault tolerant tree using adaptive operational redundancy

    Publication Year: 1992, Page(s):85 - 94
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (268 KB)

    The authors describe the architecture of fault-tolerant trees. This fault tolerant architecture is based on a majority decision of redundant operations. It shows that low-area redundancy and dynamic fault recovery are possible. This fault tolerant architecture is suitable for binary trees. Two basic types of fault tolerant architecture are presented: clustered architecture by a node-oriented appro... View full abstract»

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  • A rule-based reconfiguration of WSI processor arrays

    Publication Year: 1992, Page(s):75 - 84
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    The authors propose a formal approach to the reconfiguration of WSI (wafer scale integration) processor arrays. They propose to set up assignment rules based on the available interconnection resources. The assignment rules determine the assignment of a logical cell to a fault-free cell, such that logical cells are always connected through the available interconnection resources. The advantage of t... View full abstract»

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  • Wafer scale integration of one- and two-dimensional linear arrays

    Publication Year: 1992, Page(s):65 - 74
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Practical methods are presented for constructing one- and two-dimensional linear arrays. it is shown that, with a given probability, a square two-dimensional array can be constructed from most of the live cells on an n×n cell wafer using wires of length θ(√log n) and channels of width O(√log n). By applying recent research result... View full abstract»

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  • Processor array self-reconfiguration by neural networks

    Publication Year: 1992, Page(s):55 - 64
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    The authors introduce a novel type of neural network which can be intelligently employed for controlling the reconfiguration circuits within a VLSI/WSI chip. In this implementation, the neural network is interconnected and programmed such that it can readily execute a maximum matching algorithm in order to assign fault-free spare elements to faulty components. This approach has been compared with ... View full abstract»

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  • WSI architecture of FFT

    Publication Year: 1992, Page(s):45 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (308 KB)

    The authors propose a parallel FFT (fast Fourier transform) architecture based on an N-point FFT decomposition. Performance evaluation is performed with respect to the total area of the architecture. It is clear that the architecture is simple and the execution time is faster than that of a single FFT chip. The authors also propose a fault tolerance interconnection for the FFT butterfly n... View full abstract»

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  • A wafer scale dynamic thermal scene generator

    Publication Year: 1992, Page(s):300 - 309
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (548 KB)

    As a prototype WSTA (wafer scale transducer array), a wafer scale dynamic thermal scene generator is being developed to generate a controllable infrared (IR) image for use in calibrating IR detector arrays. The basic array consists of two cell types, one being a thermal pixel containing a poly Si resistor sitting on a suspended oxide bridge. The second cell contains the addressing, intensity regis... View full abstract»

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  • High-level design of algorithm-driven architectures: The testability and diagnosability issue

    Publication Year: 1992, Page(s):271 - 280
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (516 KB)

    Testability and diagnosability represent a mandatory step to be evaluated in the design of complex WSI (wafer scale integration) architectures before restructuring of the architecture to overcome defects can be performed. The authors propose a solution to such issues based on the analysis of testability and diagnosability of the data flow graph derived from the algorithm that has to be implemented... View full abstract»

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  • Design and analysis of defect tolerant hierarchical sorting networks

    Publication Year: 1992, Page(s):240 - 249
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (484 KB)

    A novel hierarchical defect-tolerant sorting network is presented. The design achieves a balance in area-time cost between the odd-even transposition sort and the bitonic sort. It uses less hardware than a single-level odd-even transposition sorter and reduces the wire complexity of the bitonic sorter in VLSI or WSI (wafer scale integration) implementation. The optimal number of levels in the hier... View full abstract»

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  • A WSI rapid prototyping architecture

    Publication Year: 1992, Page(s):35 - 44
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    Describes a generalized architecture, the WSI architecture for rapid prototyping (WARP), which attempts to map a large class of algorithms with only two types of processing cells. These are (a) the universal multiply-subtract-add cell (UMSA), and (b) the universal nonlinear cell (UNL). Using these cells, the authors have mapped a radix-8 FFT (fast Fourier transform) algorithm to a wafer architectu... View full abstract»

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  • Reconfiguration of two-dimensional VLSI arrays by time-redundancy

    Publication Year: 1992, Page(s):210 - 219
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    The authors present various approaches for reconfiguring two-dimensional VLSI arrays using pure time-redundancy, i.e., no spare cells are employed. This technique is based on the full processing utilization of fault free cells. The basic principles of the proposed time-redundancy technique are discussed. The first approach is based on a distributed execution of the reconfiguration process. The sec... View full abstract»

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  • RF-wafer scale integration: a new approach to active phased arrays

    Publication Year: 1992, Page(s):291 - 299
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    Describe a recently completed Westinghouse /DARPA effort in which many T/R (transmitter/receiver) modules are fabricated simultaneously on a single 3-inch GaAs wafer. Redundancy in circuit elements is utilized to obtain high yield. The resulting wafer of GaAs T/R cells is utilized as a layer within a more complex package that includes the individual radiating element. The authors update the progre... View full abstract»

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  • DFGs for synthesis of alternative architectures: Node activation synthesis

    Publication Year: 1992, Page(s):261 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    High-level synthesis systems are becoming one of the necessary standards in digital design of complex architectures since they allow a high degree of freedom to the designers in exploring and evaluating architectural alternatives. This possibility is particularly interesting when complex VLSI/WSI (wafer scale integration) architectures are considered. Synthesis and evaluation of alternative archit... View full abstract»

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  • Applying WSI methods to emitter de-interleaving

    Publication Year: 1992, Page(s):232 - 239
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (336 KB)

    Examines the application of WSI (wafer scale integration) to a computationally intensive problem-emitter de-interleaving. In the context of an electronic battlefield, both friendly and hostile RF emitters must be identified and sorted. This formidable task is expected to require a computer power of 7 Gb/s. A reconfigurable WSI technique quilted logic array is used to map this problem onto a wafer.... View full abstract»

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  • Implementation of a defect-tolerant large area monolithic multiprocessor system

    Publication Year: 1992, Page(s):28 - 34
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (296 KB)

    A defect-tolerant large area integrated circuit 16 cm2 in size was implemented. It contains the test and configuration frame for a MIMD (multiple instruction, multiple data) multiprocessor architecture for video signal processing. The emphasis was on the development of a new automatic configuration network for the interconnection of functional modules. The straightforward test and confi... View full abstract»

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  • Yield optimization of redundant multimegabit RAM's using the center-satellite model

    Publication Year: 1992, Page(s):200 - 209
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    Redundant wafer scale memories are analyzed using the center satellite model to determine the optimal redundancy organization for yield enhancement. It is suggested that the degree of redundancy for a memory module be determined depending on its distance from the periphery, as defect density increases as one moves toward the periphery. New analytical expressions for the yield of memory modules wit... View full abstract»

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  • Process characterization and yield assessment in hybrid wafer scale integration

    Publication Year: 1992, Page(s):155 - 164
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB)

    Functional yield in the hybrid approach to wafer scale integration (HWSI) is a product of the individual component yields in the HWSI assembly, including the contributions from the interconnection substrate and the pretested ICs mounted onto the substrate, and of the assembly processes employed to construct the HWSI circuit or module. The authors report process characterization and yield results f... View full abstract»

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  • SuperChip packaging issues for advanced signal processors

    Publication Year: 1992, Page(s):14 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (628 KB)

    TRW is developing a miniaturized microelectronic, high-performance vector signal processor (VSP) for use in next-generation spaceborne processors and computer workstations. The VSP consists of a monolithic very-high-speed integrated circuit (VHSIC) wafer scale device, the CPUAX (Central Processing Unit Arithmetic eXtended) SuperChip, and two very complex multichip modules, the Control Memory and t... View full abstract»

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  • A wafer scale optical bus interconnection prototype

    Publication Year: 1992, Page(s):182 - 191
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    Prototypes of a wafer wide optical bus interconnection technology are described. By optically coupling subsystems on the wafer, faults normally found in electrically based interconnection topologies are avoided. Wire buses are more prone to errors than waveguides due to the nature of the material involved and requirements for connectivity. This is accomplished through the incorporation of a planar... View full abstract»

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