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Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on

Date 22-24 Jan. 1992

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  • Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2)

    Publication Year: 1992
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    Freely Available from IEEE
  • Applying WSI methods to emitter de-interleaving

    Publication Year: 1992 , Page(s): 232 - 239
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    Examines the application of WSI (wafer scale integration) to a computationally intensive problem-emitter de-interleaving. In the context of an electronic battlefield, both friendly and hostile RF emitters must be identified and sorted. This formidable task is expected to require a computer power of 7 Gb/s. A reconfigurable WSI technique quilted logic array is used to map this problem onto a wafer. In this approach, an array of several hundred processors is used to solve the emitter de-interleaving problem. The form of the panels may be optimized for the particular application with processors, memory, or floating point functional units. Flexible interconnections allows varying numbers of processor panels to be applied to the signal processing functions. It is shown how the emitter de-interleaving problem can be solved using one 6-in wafer View full abstract»

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  • Fault tolerant tree using adaptive operational redundancy

    Publication Year: 1992 , Page(s): 85 - 94
    Cited by:  Papers (1)
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    The authors describe the architecture of fault-tolerant trees. This fault tolerant architecture is based on a majority decision of redundant operations. It shows that low-area redundancy and dynamic fault recovery are possible. This fault tolerant architecture is suitable for binary trees. Two basic types of fault tolerant architecture are presented: clustered architecture by a node-oriented approach and pipeline architecture by a branch-oriented approach View full abstract»

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  • A WSI rapid prototyping architecture

    Publication Year: 1992 , Page(s): 35 - 44
    Cited by:  Papers (4)
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    Describes a generalized architecture, the WSI architecture for rapid prototyping (WARP), which attempts to map a large class of algorithms with only two types of processing cells. These are (a) the universal multiply-subtract-add cell (UMSA), and (b) the universal nonlinear cell (UNL). Using these cells, the authors have mapped a radix-8 FFT (fast Fourier transform) algorithm to a wafer architecture as well as the L-U decomposition onto the prototyping architecture. The authors report on reconfiguration using pooled redundancy, a compromise between completely global redundancy and completely local redundancy. They also discuss a harvesting model which quickly leads to an estimate of wafer yield. Using this tool the designer can make tradeoffs between the provisioning of needed functional cells and spares, and the desired yield View full abstract»

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  • Design and analysis of defect tolerant hierarchical sorting networks

    Publication Year: 1992 , Page(s): 240 - 249
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    A novel hierarchical defect-tolerant sorting network is presented. The design achieves a balance in area-time cost between the odd-even transposition sort and the bitonic sort. It uses less hardware than a single-level odd-even transposition sorter and reduces the wire complexity of the bitonic sorter in VLSI or WSI (wafer scale integration) implementation. The optimal number of levels in the hierarchy is evaluated and the sorting capability of each level is derived to minimize the hardware overhead. The hierarchical sorting network is very regular in structure and hence it is easy to provide redundancy at every level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the defective cells with spare cells at the bottom level first, and goes to the next higher level to perform reconfiguration if there is not enough redundancy at the current level. Simulation results show that the defect tolerant hierarchical sorting network considered achieves a significant yield increase over a nonredundant sorting network View full abstract»

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  • Design and evaluation of wafer scale clock distribution

    Publication Year: 1992 , Page(s): 168 - 175
    Cited by:  Papers (8)  |  Patents (1)
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    The authors describe a computer program which is used for simulating the performance of large wafer scale integration clock distribution networks, made up of both passive transmission line elements and active buffers. The theoretical basis for the model is briefly reviewed. The authors present several example networks for 4-in wafers, comparing the AC performances as a function of power dissipation, layout area, and harvesting yield. The sensitivity of performance (as measured by propagation delays and clock skew) to random or systematic process-related fluctuations and defects is calculated using the model. A new measurement system is introduced for electrically characterizing the performance of clock distribution networks on fabricated wafers and within multichip modules View full abstract»

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  • A 3-D WASP module for real-time signal and data processing

    Publication Year: 1992 , Page(s): 95 - 104
    Cited by:  Papers (7)
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    Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost are discussed, and cost-effectiveness figures-of-merit on the order of 100 tera-OPS/ft 3, 100 tera-OPS/lb, 1 giga-OPS/W, and 10 mega-OPS/$ are forecast View full abstract»

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  • WSI architecture of FFT

    Publication Year: 1992 , Page(s): 45 - 54
    Cited by:  Papers (2)
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    The authors propose a parallel FFT (fast Fourier transform) architecture based on an N-point FFT decomposition. Performance evaluation is performed with respect to the total area of the architecture. It is clear that the architecture is simple and the execution time is faster than that of a single FFT chip. The authors also propose a fault tolerance interconnection for the FFT butterfly network by considering the complexity of the number of primitive cells View full abstract»

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  • An enhanced one-step C-testable design of two-dimensional iterative logic arrays

    Publication Year: 1992 , Page(s): 331 - 340
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    The authors present an improved approach to one-step C-testability of orthogonal two-dimensional iterative logic arrays. This is an improvement of the approach of W. Huang and F. Lombardi (1988) and H. Elhuni et al. (1986). A group of sufficient conditions to test two-dimensional iterative logic arrays with a constant number of test vectors independent of the array size (C-testability) is stated. It is proved that the proposed approach requires a smaller number of test vectors than in previous works View full abstract»

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  • A wafer scale optical bus interconnection prototype

    Publication Year: 1992 , Page(s): 182 - 191
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    Prototypes of a wafer wide optical bus interconnection technology are described. By optically coupling subsystems on the wafer, faults normally found in electrically based interconnection topologies are avoided. Wire buses are more prone to errors than waveguides due to the nature of the material involved and requirements for connectivity. This is accomplished through the incorporation of a planar waveguide which couples emitter/detector pairs. This waveguide supports an omnidirectional emission from an optical diode to all receivers on the wafer. The authors emphasize the emitter properties of the light emitting diode (LED) and its coupling to the waveguide. Details of the current prototypes are given along with data on the output of the waveguide. A photograph of the light emitted from the edge of the waveguide along with analysis and waveforms is included. The 5-micron waveguide provided improved coupling and quite flat output along the edge as compared to a 0.3-micron device. Current work utilizes a single wavelength source from a LED transmitting at 1.4 Gbit/second View full abstract»

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  • Optimizing adders for WSI

    Publication Year: 1992 , Page(s): 251 - 260
    Cited by:  Papers (5)
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    The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders. The adders are constructed with inverters and two-to-four-input AND and OR gates. A figure of merit is presented that can be used to compare the adders based on their delay and relative dynamic power consumption. This figure of merit provides a common ground for ranking the adders in terms of their utility for WSI (wafer scale integration) applications. Extensive simulation was used to evaluate the switching characteristics, and the results are used to rank the adders in terms of speed, size, and the number of logic transitions (a measure of the dynamic power consumption for static CMOS circuits). According to the figure of merit, the carry lookahead adder is the best design for word sizes between 16 and 64 bits, inclusive View full abstract»

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  • High density metal cross-point laser linking

    Publication Year: 1992 , Page(s): 176 - 181
    Cited by:  Papers (3)  |  Patents (5)
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    Laser-programmed inter-level metal connections have been developed as a means of achieving high-density linking for additive redundancy in restructurable logic and in wafer scale integration. The authors report on the successful linking of 8×8 cross-points of aluminium alloy lines separated by SiNx insulation. Both processing and linking issues are addressed. The processing issues are extensions of the problems associated with any reliable two-level metal process with the added concerns of making structures for laser linking. The linking issues involve aiming a laser and forming a link with minimum peripheral damage to either the connecting metal lines or the underlying oxide and silicon View full abstract»

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  • Optimal group diagnosis procedures for VLSI/WSI array architectures

    Publication Year: 1992 , Page(s): 352 - 361
    Cited by:  Papers (1)
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    Addresses the problem of partitioning VLSI/WSI (wafer scale integration) array architectures into disjoint maximal diagnosis blocks (MDBs) and finding an optical group diagnosis policy for testing and locating faulty elements (modules) in these MDBs. The optimization criterion is to minimize the accumulated diagnosis cost in deriving a feasible reconfiguration solution. The technique for partitioning an array is based on the parallel partition approach. The problem of finding an optimal group diagnosis procedure is modeled as a (t+1)-ary decision tree, where t is the size of an MDB. Instead of dealing with a (t+1)-ary decision tree directly, the problem is further reduced to that of handling a binary decision tree or a block-walking representation. Properties related to the group diagnosis procedures and binary decision trees are derived. Simulation results are provided to further support the effectiveness of the proposed approach over other approaches View full abstract»

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  • The impact of the declining cost per MIPS

    Publication Year: 1992
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    Summary form only given, as follows. The personal computer (PC) cost per million instructions per second (MIPS) is projected to decline to less than $100.00 per MIPS by 1995, and to a few dollars per MIPS by 2010. This cost reduction will be achieved through very large scale integration, multi-chip modules, and operating voltage reduction. Cheap computing power will allow many problems currently handled by workstations and minicomputers to be handled on a PC, such as advanced graphics and extensive financial analysis programs. PCs will become highly specialized to address these markets View full abstract»

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  • Process characterization and yield assessment in hybrid wafer scale integration

    Publication Year: 1992 , Page(s): 155 - 164
    Cited by:  Papers (6)
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    Functional yield in the hybrid approach to wafer scale integration (HWSI) is a product of the individual component yields in the HWSI assembly, including the contributions from the interconnection substrate and the pretested ICs mounted onto the substrate, and of the assembly processes employed to construct the HWSI circuit or module. The authors report process characterization and yield results for a high interconnection density silicon substrate technology, and for wire bonding and flip chip solder bonding chip connection technologies that are being developed to support HWSI module construction. The design of a SPARC CPU circuit module for parallel computing applications that uses this technology is also described View full abstract»

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  • Hierarchical redundancy for orthogonal arrays

    Publication Year: 1992 , Page(s): 220 - 229
    Cited by:  Papers (4)
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    Hierarchical redundancy using defect-tolerant replacement circuits is proposed for increasing the yield of large-area LSIs (WSIs) with mesh-connected array structures. The defect-tolerant replacement circuits can be constructed by using direct-connection paths and distributed switches in basic k-out-of-n redundancy schemes. When the proposed redundancy configurations are applied to two-dimensional orthogonal-array WSIs (wafer-scale-integrated circuits), they reduce the number of switches not covered by any spare replacements. An estimate of defect tolerance indicates that the proposed redundancy configurations can increase the integration scale under 1-micron CMOS design about 256 times over that of general nonredundant LSIs View full abstract»

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  • Processor array self-reconfiguration by neural networks

    Publication Year: 1992 , Page(s): 55 - 64
    Cited by:  Papers (3)
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    The authors introduce a novel type of neural network which can be intelligently employed for controlling the reconfiguration circuits within a VLSI/WSI chip. In this implementation, the neural network is interconnected and programmed such that it can readily execute a maximum matching algorithm in order to assign fault-free spare elements to faulty components. This approach has been compared with the traditional reconfiguration algorithms, and by intensive simulation it is shown that the proposed neural net approach provides superior quality performance (i.e., higher survivability rates). It is also shown that the intrinsic fault-tolerant nature of neural networks maintains a degradable reconfiguration control even in the presence of faulty neural network components. The speed of neural networks provides an added advantage for online reconfiguration, where the chip can be quickly repaired by itself, thus reducing the system down-time View full abstract»

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  • Efficient fault diagnosis of switches in wafer arrays

    Publication Year: 1992 , Page(s): 341 - 351
    Cited by:  Papers (1)
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    Considers an abstract model of a wafer-scale system where functional modules are connected by connections which run over wiring channels. Programmable switches are located at the junction of these wiring channels. The proposed technique is based on recursively finding progressive fault-free paths across regions of the wafer whose boundaries have been diagnosed to be fault-free. It is shown that such a technique will work with high probability and could be performed in time polynomial in the size of the array. The division of the wafer requires paths of short lengths and it is shown that these paths exist with high probability View full abstract»

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  • Yield optimization of redundant multimegabit RAM's using the center-satellite model

    Publication Year: 1992 , Page(s): 200 - 209
    Cited by:  Papers (2)  |  Patents (1)
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    Redundant wafer scale memories are analyzed using the center satellite model to determine the optimal redundancy organization for yield enhancement. It is suggested that the degree of redundancy for a memory module be determined depending on its distance from the periphery, as defect density increases as one moves toward the periphery. New analytical expressions for the yield of memory modules with extra rows and/or extra columns, coding, and coding with extra rows are formulated. Results suggest that coding can be more effective than extra rows and columns for higher levels of defect densities. On the other hand, for lower levels of defect densities, having only extra rows and columns may be sufficient. Using the model it is shown that, by taking into account the precise distributions of clusters on the wafer, defects in a cluster, and the radial variation of these defects, an optimal account of redundancy can be found to achieve the highest possible yield View full abstract»

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  • Optimal spare allocation for defect-tolerant VLSI

    Publication Year: 1992 , Page(s): 193 - 199
    Cited by:  Papers (2)
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    The authors study the problem of allocating spares to specific fault-tolerant VLSI/WSI (wafer scale integration) designs to maximize the global yield. Four problems are examined: (1) the optimal yield problem for k-out-of-n systems; (2) the optimal partition of elements; (3) spare allocation for trees; and (4) spare allocations for row/column reconfiguration systems View full abstract»

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  • DFGs for synthesis of alternative architectures: Node activation synthesis

    Publication Year: 1992 , Page(s): 261 - 270
    Cited by:  Papers (1)
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    High-level synthesis systems are becoming one of the necessary standards in digital design of complex architectures since they allow a high degree of freedom to the designers in exploring and evaluating architectural alternatives. This possibility is particularly interesting when complex VLSI/WSI (wafer scale integration) architectures are considered. Synthesis and evaluation of alternative architectures is performed, adopting the data flow graph (DFG) model. In particular, the problem of optimal scheduling of node activities and delay minimization is examined. Procedures for graph balancing and optimal delay distribution are provided. The balancing and minimization procedures proposed identify the optimal scheduling for node activation synthesis both in terms of the timing parameters proper to the graph (latency and throughput) and in terms of the amount of delay added to the arcs to grant correct synchronization View full abstract»

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  • The application of yield modelling to the WASP parallel processing architecture

    Publication Year: 1992 , Page(s): 115 - 123
    Cited by:  Papers (5)
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    The authors address yield modeling considerations and their impact upon the floorplanning and defect tolerance strategies of the WSI Associative String Processor (WASP) architecture. A fully parameterized, detailed yield model for the WASP architecture has been presented previously. This yield model has been developed further and applied to the various design options for future WASP devices. Using the improved model, the impact of these design options on the yield of WASP devices is assessed, leading to a set of recommendations as the optimum WASP floorplan View full abstract»

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  • Architecture and performance of a large area multiprocessor system for real-time video processing

    Publication Year: 1992 , Page(s): 19 - 27
    Cited by:  Papers (6)
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    The performance of multiprocessor architectures for real-time video processing applications, consisting of bus connected identical processing elements, is discussed. The regular structure of such architectures supports a large area integration. The performance of a large area implementation of the architectures is analyzed and discussed dependent on the controlling mode with respect to the processing of basic video coding algorithms. The main problems are data supply, controlling, and processing of data dependent algorithms. Due to the specific I/O constraints of large area circuits and for computation intensive video coding applications it is shown that MIMD (multiple instruction, multiple data) controlling provides a higher utilization of the arithmetic resources than SIMD (single instruction, multiple data) View full abstract»

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  • The legacy of WSI research in MCM test/repair strategies

    Publication Year: 1992 , Page(s): 135 - 144
    Cited by:  Papers (7)
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    It is pointed out that, as MCMs (multi-chip modules) develop, a suitable design-for-manufacturability strategy will need to emerge, reducing MCM costs while retaining the performance advantages of MCMs. Three issues are considered: (1) a suitable analytic model of defects (and their generation of faults) suitable for application of `design for defect avoidance' and `design for fault avoidance' approaches; (2) the detectability of faults and localization of repairable faults; and (3) approaches for in-process physical repair of fault-producing defects. It is noted that MCMs offer conditions quite different from traditional WSI (wafer scale integration), particularly in the absence of active circuitry which may fail. In this sense, techniques which have not yet proved practical for successful production of WSI circuits may have considerable application for MCMs View full abstract»

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  • Lithographic manufacturing techniques for wafer scale integration

    Publication Year: 1992 , Page(s): 4 - 13
    Cited by:  Papers (2)  |  Patents (1)
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    A methodology utilizing a mix-and-match approach of optical 1×lithography and e-beam lithography currently used at TRW for WSI (wafer scale integration) technologies is discussed. Field stitching techniques, design considerations, and macrocell grouping techniques which enhance field stitching capability and impact design rules are described for this mix and match e-beam and 1×optical stepper lithography process. A comparative cost analysis of WSI tooling costs, WSI wafer throughput, and WSI tooling requirements is presented to illustrate the tradeoffs among the various lithography systems. The proposed lithography process has been experimentally verified using test chip field stitching structures View full abstract»

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