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[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems

18-20 Nov. 1991

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Displaying Results 1 - 25 of 36
  • Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (Cat. No.91TH0395-4)

    Publication Year: 1991
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    Freely Available from IEEE
  • Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement

    Publication Year: 1991, Page(s):67 - 80
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called `MONGOS' due to their size (~300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance a... View full abstract»

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  • Circuit-level modeling of spot defects

    Publication Year: 1991, Page(s):63 - 66
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. The authors discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catas... View full abstract»

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  • Applications of a mechanistic yield model for MOSIC chips

    Publication Year: 1991, Page(s):60 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    A mechanistic random-defect yield model has been extended to several CMOS technologies and applied to several types of circuit forms. Inputs to the model include critical geometries for yield analysis obtained from detailed layout analysis, and defect density values obtained from large area test structures, with both inputs being needed for each mechanism. A generally applicable yield model metric... View full abstract»

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  • A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

    Publication Year: 1991, Page(s):157 - 160
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI... View full abstract»

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  • Improved yield models for fault-tolerant random-access memory chips

    Publication Year: 1991, Page(s):46 - 59
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip faults eliminates the need for yield-model formulas, making possible accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. This results in loosely coupled distributions ... View full abstract»

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  • Reliability evaluation of FUSS and other reconfiguration schemes

    Publication Year: 1991, Page(s):153 - 156
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    One objective in the design of VLSI/WSI fault-tolerant processor arrays (FTPA), is to increase the probability of successful reconfiguration in the presence of one or more faults given that a fault has occurred (survivability). This paper reports a comparison of FUSS (Full-Use-of-Suitable-Spares), a recently proposed reconfiguration scheme, with other two well reconfiguration schemes. The results ... View full abstract»

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  • Some results and open problems concerning memory reconfiguration under clustered fault models

    Publication Year: 1991, Page(s):292 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Reconfiguration of memory arrays using spare rows and spare columns has been shown to be a useful technique for yield enhancement. This problem is NP-hard in general and hence, previous work has focused on branch-and-bound algorithms for smaller problems and approximation algorithms for larger problems. Recently, the performances of several algorithms have been evaluated under a probabilistic mode... View full abstract»

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  • Efficient and optimal fault-to-spare assignments in doubly fault tolerant arrays

    Publication Year: 1991, Page(s):247 - 259
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Given a doubly fault tolerant system with m faults, the authors present an algorithm for finding a fault-to-spare assignment for the m faults in O(m) time. This improvement over the O(m1.5) bi-partite graph technique for finding an assignment is obtained by partitioning the problem into independent regions and proving that, in each region, an assignment may be found in linear time. The ... View full abstract»

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  • Circuit design for a large area high-performance crossbar switch

    Publication Year: 1991, Page(s):32 - 45
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    The methodology for circuit design of large area ICs (LAICs) is discussed. The partitioning and layout strategies for a self-testing, self-reconfigurating LAIC are formulated. It is shown that by proper layout design the circuit sensitivity to the manufacturing defects can be drastically decreased. A LAIC crossbar switch chip, which served as a vehicle for the experimental verification of the desc... View full abstract»

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  • Harvest rate of reconfigurable pipelines

    Publication Year: 1991, Page(s):93 - 102
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are... View full abstract»

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  • Monolithic VLSI vs. MCM a perspective on performance, yield, and manufacturing

    Publication Year: 1991, Page(s):116 - 119
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    MCMs are touted as the emerging challenge to monolithic VLSIs. The purported driving forces are performance and economics. While the potentials are attractive, many practical problems remain before MCMs become viable. Furthermore, it is not at clear that MCMs will replace monolithic VLSIs as suggested. The author contrasts these technologies. Using the implementation of a CPU function as an exampl... View full abstract»

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  • Overview of fault handling for the chaos router

    Publication Year: 1991, Page(s):124 - 127
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. This randomization, however, greatly complicates the fault detection because... View full abstract»

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  • Concurrent error diagnosis in mesh array architectures based on overlapping H-processes

    Publication Year: 1991, Page(s):139 - 152
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Unlike other methods for concurrent error detection and location (CED), the one proposed is not application specific and does not require fault free comparators and custom VLSI design for the processing cells. It is suitable for any algorithm that can be decomposed in block operations of the format [(a op1 b) op2 (c op3 d)], where a, b, c, d are arbitrary operands ... View full abstract»

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  • Hex-repair: a new approach to hexagonal array reconfiguration

    Publication Year: 1991, Page(s):288 - 291
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    Presents a new approach to the reconfiguration problem for regular hexagonal arrays that find numerous applications in VLSI and WSI designs such as multipliers, signal processing circuits, etc. Efficient heuristics are used to obtain a fast solution that has excellent fault-coverage characteristics even in the presence of multiple faults View full abstract»

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  • Physical boundaries of performance: the interconnection perspective

    Publication Year: 1991, Page(s):227 - 246
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    Several interconnection issues relating to faults and reliability are reviewed. Whereas the occurrence of opens in interconnections or shorts between interconnections is well understood within conventional models of digital systems, the faults originating from the analog characteristics of signals propagating across interconnection lines (particularly long lines) is less often discussed. However, ... View full abstract»

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  • A method for the consistent reporting of fault coverage

    Publication Year: 1991, Page(s):195 - 198
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    A standard procedure has been developed for fault coverage measurement. Procedure 5012 of MIL-STD-883 governs the reporting of fault coverage for digital microcircuits for military applications. It describes requirements for the development of the logic model for an IC, fault universe, fault simulation, and reporting of results. Procedure 5012 provides a consistent means of measuring fault coverag... View full abstract»

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  • A bottom-up methodology to characterize delay faults

    Publication Year: 1991, Page(s):183 - 186
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect ... View full abstract»

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  • Current-mode techniques for analog VLSI: technology and defect tolerance issues

    Publication Year: 1991, Page(s):28 - 31
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    Future large scale analog computational systems will have to cope with manufacturing defects and mismatch in individual components. The author argues that current-mode design techniques, and in particular minimal designs at the transistor level are consistent with future manufacturing requirements for wafer scale analog systems View full abstract»

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  • A model for enhanced manufacturability of defect tolerant integrated circuits

    Publication Year: 1991, Page(s):81 - 92
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model al... View full abstract»

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  • On the modeling and testing of gate oxide shorts in CMOS logic gates

    Publication Year: 1991, Page(s):161 - 174
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be depen... View full abstract»

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  • State-of-the-art of the wafer scale ELSA project

    Publication Year: 1991, Page(s):296 - 299
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor... View full abstract»

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  • Fast search algorithms for reconfiguration problems

    Publication Year: 1991, Page(s):260 - 273
    Cited by:  Papers (13)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A number of reconfiguration strategies have been proposed for increasing the yield of VLSI chips. In most cases the associated reconfiguration problems are NP-complete. Therefore, exhaustive search algorithms are generally used in order to find a solution when one exists. In this paper we present the notion of admissible sets and show how such sets can be used to significantly reduce the running t... View full abstract»

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  • Neural networks on silicon: the mapping of hardware faults onto behavioral errors

    Publication Year: 1991, Page(s):103 - 115
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The problem of defect- and fault-tolerance in neural networks becomes increasingly important as a growing number of silicon implementations become available and mission-critical applications are envisioned. As an alternative to architecture-specific policies, intrinsic characteristics of the neural paradigm with respect to a functional error model are considered. In particular, this has been done ... View full abstract»

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  • Key issues in the design of a fault-tolerant core avionics computer based on the mesh architecture

    Publication Year: 1991, Page(s):120 - 123
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    Greater integration of avionics and flight control electronics with the need for higher reliability while maintaining or improving safety and availability and the need for reduced line maintenance costs are key drivers for the examination of a fault tolerant core computer architecture. The authors' approach is to develop a computer using commercially available microprocessors and memory with an AS... View full abstract»

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