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Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Date 18-20 Nov. 1991

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  • Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (Cat. No.91TH0395-4)

    Publication Year: 1991
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    Freely Available from IEEE
  • A model for enhanced manufacturability of defect tolerant integrated circuits

    Publication Year: 1991, Page(s):81 - 92
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model al... View full abstract»

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  • Some results and open problems concerning memory reconfiguration under clustered fault models

    Publication Year: 1991, Page(s):292 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Reconfiguration of memory arrays using spare rows and spare columns has been shown to be a useful technique for yield enhancement. This problem is NP-hard in general and hence, previous work has focused on branch-and-bound algorithms for smaller problems and approximation algorithms for larger problems. Recently, the performances of several algorithms have been evaluated under a probabilistic mode... View full abstract»

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  • Physical fault injection: a suitable method for the evaluation of functional test efficiency

    Publication Year: 1991, Page(s):179 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    The last generation of 32-bit microprocessors seems `to ring the knell' of functional test methods. Indeed, those based on fault hypothesis cannot cope with the technological reality; the other ones (ad hoc tests, systematic test, . . .) are overwhelmed by the very large number of cases (instructions) to be analyzed. The authors present a pragmatic approach that attempts to resolve this critical p... View full abstract»

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  • State-of-the-art of the wafer scale ELSA project

    Publication Year: 1991, Page(s):296 - 299
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor... View full abstract»

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  • A bottom-up methodology to characterize delay faults

    Publication Year: 1991, Page(s):183 - 186
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect ... View full abstract»

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  • Concurrent built-in self-test with reduced fault latency

    Publication Year: 1991, Page(s):199 - 212
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Presents various new approaches for concurrent built-in self-test (CBIST). These new approaches have a low latency in fault detection. Two approaches are proposed. The first approach is applicable to combinational logic circuits which can be designed using iterative logic arrays (ILAs). Two methods namely the HIT-COMPRESS and HIT-IDENTICAL, are discussed. These methods employ different hardware st... View full abstract»

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  • A method for the consistent reporting of fault coverage

    Publication Year: 1991, Page(s):195 - 198
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    A standard procedure has been developed for fault coverage measurement. Procedure 5012 of MIL-STD-883 governs the reporting of fault coverage for digital microcircuits for military applications. It describes requirements for the development of the logic model for an IC, fault universe, fault simulation, and reporting of results. Procedure 5012 provides a consistent means of measuring fault coverag... View full abstract»

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  • Array architecture for ATG with 100% fault coverage

    Publication Year: 1991, Page(s):213 - 226
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design imp... View full abstract»

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  • Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement

    Publication Year: 1991, Page(s):67 - 80
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called `MONGOS' due to their size (~300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance a... View full abstract»

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  • Effects of fault tolerance on the reliability of memory array supports

    Publication Year: 1991, Page(s):128 - 138
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    For future-generation large-scale computers, memory reliability is independent of the memory chip failures due to low failure rates and fault-tolerant techniques. When failures do occur, they are masked, using such techniques as single error correction (SEC), page deallocation, and array chip sparing. The two remaining sources of failures are card(s) and logic support modules. This paper describes... View full abstract»

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  • Monolithic VLSI vs. MCM a perspective on performance, yield, and manufacturing

    Publication Year: 1991, Page(s):116 - 119
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    MCMs are touted as the emerging challenge to monolithic VLSIs. The purported driving forces are performance and economics. While the potentials are attractive, many practical problems remain before MCMs become viable. Furthermore, it is not at clear that MCMs will replace monolithic VLSIs as suggested. The author contrasts these technologies. Using the implementation of a CPU function as an exampl... View full abstract»

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  • Harvest rate of reconfigurable pipelines

    Publication Year: 1991, Page(s):93 - 102
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are... View full abstract»

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  • Delay fault simulation of self-checking error checkers

    Publication Year: 1991, Page(s):187 - 190
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    A robustly-tested gate-delay fault model is proposed using 7-valued logic, and applied to the delay fault simulation of self-checking error checkers. The simulated results are compared with those obtained using either a nonrobustly-tested gate-delay fault model or a path-delay fault model. Experiments show that the robustly-tested gate-delay fault model gives the most pessimistic evaluation for de... View full abstract»

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  • Optimization of parametric yield

    Publication Year: 1991, Page(s):1 - 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    Yield loss can be characterized as either catastrophic or parametric. Catastrophic yield loss is primarily do to local, or spot, defects that occur in a manufacturing process. On the other hand, parametric yield loss is due to global disturbances, such as mask misalignment. In this paper the author explores these two different types of yield loss and then reviews some methods that have been develo... View full abstract»

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  • Hex-repair: a new approach to hexagonal array reconfiguration

    Publication Year: 1991, Page(s):288 - 291
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    Presents a new approach to the reconfiguration problem for regular hexagonal arrays that find numerous applications in VLSI and WSI designs such as multipliers, signal processing circuits, etc. Efficient heuristics are used to obtain a fast solution that has excellent fault-coverage characteristics even in the presence of multiple faults View full abstract»

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  • A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

    Publication Year: 1991, Page(s):157 - 160
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI... View full abstract»

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  • Circuit design for a large area high-performance crossbar switch

    Publication Year: 1991, Page(s):32 - 45
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    The methodology for circuit design of large area ICs (LAICs) is discussed. The partitioning and layout strategies for a self-testing, self-reconfigurating LAIC are formulated. It is shown that by proper layout design the circuit sensitivity to the manufacturing defects can be drastically decreased. A LAIC crossbar switch chip, which served as a vehicle for the experimental verification of the desc... View full abstract»

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  • Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing

    Publication Year: 1991, Page(s):20 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme View full abstract»

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  • Circuit-level modeling of spot defects

    Publication Year: 1991, Page(s):63 - 66
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. The authors discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catas... View full abstract»

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  • Current-mode techniques for analog VLSI: technology and defect tolerance issues

    Publication Year: 1991, Page(s):28 - 31
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    Future large scale analog computational systems will have to cope with manufacturing defects and mismatch in individual components. The author argues that current-mode design techniques, and in particular minimal designs at the transistor level are consistent with future manufacturing requirements for wafer scale analog systems View full abstract»

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  • Concurrent error diagnosis in mesh array architectures based on overlapping H-processes

    Publication Year: 1991, Page(s):139 - 152
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Unlike other methods for concurrent error detection and location (CED), the one proposed is not application specific and does not require fault free comparators and custom VLSI design for the processing cells. It is suitable for any algorithm that can be decomposed in block operations of the format [(a op1 b) op2 (c op3 d)], where a, b, c, d are arbitrary operands ... View full abstract»

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  • Reconfiguration of time-multiplexed binary trees for satellite communication

    Publication Year: 1991, Page(s):274 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    A time-multiplexed version of a binary tree channeliser can be implemented as a pipelined structure. Reconfiguration aspects of such a pipeline are considered in this paper. By developing a serial-module scheme for reconfiguration it is shown that the SM scheme offers better reliability than its equivalent binary trees. A digital filter is assumed as the basic processing element of the pipeline an... View full abstract»

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  • Overview of fault handling for the chaos router

    Publication Year: 1991, Page(s):124 - 127
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. This randomization, however, greatly complicates the fault detection because... View full abstract»

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  • Neural networks on silicon: the mapping of hardware faults onto behavioral errors

    Publication Year: 1991, Page(s):103 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The problem of defect- and fault-tolerance in neural networks becomes increasingly important as a growing number of silicon implementations become available and mission-critical applications are envisioned. As an alternative to architecture-specific policies, intrinsic characteristics of the neural paradigm with respect to a functional error model are considered. In particular, this has been done ... View full abstract»

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