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Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on

Date 29-31 May 1996

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Displaying Results 1 - 25 of 52
  • Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

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  • Multi-valued decoder based on resonant tunneling diodes in current tapping mode

    Page(s): 230 - 234
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    A multiple valued decoder based on RTDs is proposed and the functionality is verified via both simulation and experiment. The proposed circuit is simulated and tested with several single peaked RTD sections connected in series (stacked RTDs). The design uses current tapping techniques to switch on only one RTD section exclusively in order to create a single literal function. The number of RTD sections connected in series therefore determines the radix of signals used in the decoder View full abstract»

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  • Interband RTDs with nanoelectronic HBT-LED structures for multiple-valued computation

    Page(s): 80 - 85
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    For future nanoelectronic arrays, complex signal processing methods and highly efficient computation are required. A proposed new family of HBT-LED-RTD circuitry chiefly addresses the latter with multiple-valued logic. We use internal optical methods of signal summation in otherwise electronic circuitry. Precision photon streams are generated and summed that are equivalent to electron currents in conventional circuitry. These strictly local interactions of HBTs and LEDs are combined with the folding and thresholding functions of vertically integrated RTDs. Power-of-two bit patterns implement the positive-digit radix-2 MVL. The same circuitry with a summation range of seven also facilitates nanoelectronic signal processing with its innate A/D conversion capability. Our new circuitry is aimed at very high packing density on the order of 104 to 106 gates per IC die. For this purpose it is resistor free and requires no signal-level shifting subcircuits, the HBT-RTD structure is 3-dimensional, and parasitic electrostatic interaction of densely packed circuits is prevented by the optical isolation and the buried optical interconnects. Non-local (especially vertical free-space) optical interconnects are also feasible with our approach using LEDs or microcavity lasers View full abstract»

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  • As you like them: connectives in fuzzy logic

    Page(s): 2 - 7
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    We review the question of which connectives (conjunctions, disjunctions and negations) may be of interest in fuzzy logic. Several alternative structures to the classical Boolean algebras are presented and discussed. We show how techniques from the theory of functional equations may help to clarify the problem of choosing appropriate connectives or refusing inadequate operations View full abstract»

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  • Testability of generalized multiple-valued Reed-Muller circuits

    Page(s): 56 - 61
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    The testability of generalized Reed-Muller circuits realizing m-valued functions in module m sum-of-product form, with m being a prime greater than two, is investigated. Two aspects of the problem are considered-the number of tests required for fault detection, and the generation of tests. We prove that just four tests are sufficient to detect all single stuck-at faults on internal lines in the circuit. Furthermore, this set of tests is independent of the function being realized and therefore universal. We give two alternative techniques for testing primary inputs-one by generating a test set of maximum length 2n, where n is the number of primary inputs and the other by adding to the circuit an extra multiplication mod m gate with an observable output to ensure that the four tests for internal lines also detect all single stuck-at faults on primary inputs View full abstract»

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  • Planarity in ROMDDs of multiple-valued symmetric functions

    Page(s): 236 - 241
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    We show that a multiple-valued symmetric function has a planar ROMDD (reduced ordered multiple-valued decision diagram) if and only if it is a pseudo-voting function. We show that the number of such functions is (r-1)(n+r, n+1) where r is the number of logic values and n is the number of variables. It follows from this that the fraction of symmetric multiple-valued functions that have planar ROMDDs approaches 0 as n approaches infinity. Further, we show that the worst case and average number of nodes in planar ROMDDs of symmetric functions is n2(1/2-1/2r) and n2(1/2-1/(r+1)), respectively, when n is large View full abstract»

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  • A necessary and sufficient condition for Lukasiewicz logic functions

    Page(s): 37 - 42
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    The literal, TSUM, min and max operations employed in multiple-valued logic design can be expressed in terms of the implication and the negation of Lukasiewicz logic. We can easily show that the set of multiple-valued functions composed of the above four operations and the negation is equivalent to the set of all multiple-valued functions composed of the Lukasiewicz implication and the negation. This implies that from the viewpoint of the multiple-valued logic design, Lukasiewicz multiple-valued logic is a fundamental system. In this paper, we clarify a necessary and sufficient condition for a multiple-valued function to be a Lukasiewicz logic function, which is defined as a function in terms of the Lukasiewicz implication and the negation View full abstract»

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  • Design of one-vector testable binary systems based on ternary logic

    Page(s): 62 - 66
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    A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method View full abstract»

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  • Commodious axiomatization of quantifiers in multiple-valued logic

    Page(s): 118 - 123
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    We provide a concise axiomatization of a broad class of generalized quantifiers in many-valued logic, so-called distribution quantifiers. Although sound and complete axiomatizations for such quantifiers exist, their size renders them virtually useless for practical purposes. We show that for certain lattice-based quantifiers relatively small axiomatizations can be obtained in a schematic way. This is achieved by providing an explicit link between skolemized signed formulas and filters/ideals in Boolean set lattices View full abstract»

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  • New MVL-PLA structures based on current-mode CMOS technology

    Page(s): 98 - 103
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    Programmable logic arrays (PLAs) are being used to implement complex multi-valued logic (MVL) circuits. In this paper we introduce three new current-mode CMOS MVL-PLA structures for the implementation of MVL functions. These PLA structures use four current-mode CMOS building blocks namely, cycle, min, tsum and constants. Comparison between the introduced architectures is made based on their respective ability to realize all possible r-valued one-variable functions. Simulation results are provided to show that the third type of PLA, called type-C PLA, is superior to the other two types, called type-A PLA and type-B PLA respectively, in terms of the total number of functions realized using a given number of columns. However, this comes at the expense of an increased hardware overhead in the form of extra cyclic generator blocks added at the input of the PLA View full abstract»

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  • Reasoning in inconsistent stratified knowledge bases

    Page(s): 184 - 189
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    This paper proposes a discussion of inconsistency-tolerant consequence relations in prioritized knowledge bases. These inference techniques extend methods for reasoning from inconsistent, non-stratified, knowledge bases to the case where priorities between formulas are available. Priorities between formulas are handled in the framework of possibility theory and allow for the use of pieces of information having various levels of confidence. A comparative analysis of several approaches is carried out, namely, the possibilistic inference and its extensions, three inference methods based on a selection of maximal consistent subsets of formulas, and two inference methods based on arguments View full abstract»

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  • Low-energy logic circuit techniques for multiple valued logic

    Page(s): 86 - 90
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    Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of MVL techniques into specific VLSI design applications, these MVL designers may be able to take advantage of new energy saving circuit design techniques that may have tradeoffs that complement those of MVL. Low-energy (adiabatic) logic circuits have been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional dc power supply, these logic circuits use “ac” power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. It is possible to integrate all power switches and control circuitry on the chip with the low-energy logic. This results in better system efficiency and simpler power distribution. In this paper, concepts of adiabatic circuit design and the use of a high-frequency resonant power clock generator for adiabatic circuits will be summarized and then their possible application to low-energy, adiabatic multiple valued logic is discussed View full abstract»

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  • The deepest repetition-free decompositions of nonsingular functions of finite-valued logics

    Page(s): 279 - 282
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    A superposition is called repetition-free if every variable appears in it at most once. Two terms are said to almost coincide if the second term can be obtained from the first one in a finite number of steps: isotopy change, commutation change and associative change. The main result: every two deepest repetition-free decompositions of a nonsingular function of a finite-valued logics almost coincide. As a corollary we have the corresponding Kuznetaov's results for Boolean functions and Sosinsky's result for functions of three-valued logics View full abstract»

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  • A method to represent multiple-output switching functions by using multi-valued decision diagrams

    Page(s): 248 - 254
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    Multiple-output switching functions can be simulated by multiple-valued decision diagrams (MDDs) at a significant reduction in computation time. analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued decision diagrams (MTMDDs), and shared multi-terminal multiple-valued decision diagrams(SMTMDDs). For example, we show that SMDDs fend to be compact, while SMTMDDs tend to be fast. We present an algorithm for grouping input variables and output functions in the MDDs View full abstract»

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  • Design of multivalued circuits using genetic algorithms

    Page(s): 216 - 221
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    This paper describes an evolutionary algorithm for the design of good multivalued logic (MVL) circuits based on genetic algorithms. A method for deriving low-cost realizations, based on the cost-table technique, is presented. A new cost-table is also proposed that results in better realizations than that obtained in the past. With genetic algorithms the design of MVL circuits can be handled as an optimization problem View full abstract»

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  • Propositional skew Boolean logic

    Page(s): 43 - 48
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    A non-commutative propositional logic is described. A Hilbert-style axiomatisation is given for the logic, and a multiple-valued interpretation is constructed. The logic is shown to be sound and complete with respect to this interpretation. We also show that the logic has no finite complete models. An application includes the specification and design of multiple-valued switching circuits View full abstract»

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  • Several remarks on the complexity of set-valued switching functions

    Page(s): 166 - 170
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    We explore the complexity of circuits that implement set-valued logic functions on a complete basis that we propose in this paper. This basis is related to the bases used in the main sources on this subject, as we show in Section 2. After discussing properties of the constituents of this basis (which consist of both Boolean and non-Boolean components) we prove that almost all set-valued functions require a large number of Boolean components View full abstract»

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  • Complex spectral decision diagrams

    Page(s): 255 - 260
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    Different decision diagrams for representations of binary and multiple-valued functions in the form of Complex Hadamard Transforms and Spectra are introduced in this paper. Since Complex Hadamard Transform matrix can be recursively expanded through Kronecker products, complex hybrid decision diagrams can be easily derived. Other types of decision diagrams introduced are: complex multi-terminal decision diagrams, complex algebraic decision diagrams, real and imaginary decision diagrams and complex edge-valued decision diagrams. The latter decision diagrams are derived from partial Complex Hadamard Transform. Introduction of different efficient representations of Complex Hadamard Transforms and spectra in the form of decision diagrams with their useful properties as the discrete transformations should open the possibility of new applications of spectral techniques based on such transformations in the design of binary and multiple-valued logic systems View full abstract»

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  • The incidence propagation method

    Page(s): 124 - 129
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    Incidence calculus is a probabilistic logic developed from propositional logic which associates probabilities with sets of possible worlds rather than with formulae directly. The probability of a formula is defined as the probability of the set of possible worlds in which this formula is true. This set of possible worlds is named as the incidence set of this formula. So the task of calculating probabilities of formulae relies on the task of obtaining incidence sets for formulae. In this paper, we present an approach for manipulating incidences in extended incidence calculus in the situation that, the language set is large. We will show how to decompose this large set into small, but coherent sets and then how to propagate incidences among these sets. In this way incidence sets can be calculated efficiently View full abstract»

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  • Design of highly parallel linear digital circuits based on symbol-level redundancy

    Page(s): 104 - 109
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    In the non-linear digital system, it is difficult to design systematically highly parallel digital circuits whose output digit depends on a small number of input digits. On the other hand, the concept of linearity in digital systems is very attractive because analytical methods can be utilized to design highly parallel circuits. One of the most important problems in the design is to transform an original specification to a linear one. The design method of highly parallel circuits based on a necessary condition has been discussed. However, we cannot always find the solution even if the necessary condition is satisfied. To solve the problem, a sufficient condition for linearity is derived. If the sufficient condition is satisfied, we can design the linear circuit from the specification by the use of multiplicated redundant symbols View full abstract»

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  • New interpolation algorithms for multiple-valued Reed-Muller forms

    Page(s): 16 - 23
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    This paper presents new algorithms for the sparse multivariate polynomial interpolation over finite fields, which can be used for optimizing Reed-Muller forms for MVL functions. Starting with a quadratic time interpolation algorithm for Boolean functions, we develop a method that decomposes the problem into several smaller problems for the MVL case. We then show how each of these problems can be solved by a practical probabilistic algorithm. The approach is extended to fixed polarity RM forms, in which the complexity of the resulting forms becomes simpler and also the running lime of the algorithm is reduced View full abstract»

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  • A ternary systolic product-sum circuit for GF(3m) using neuron MOSFETs

    Page(s): 92 - 97
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    In this paper, we present a ternary systolic product-sum computation circuit for GF(3m) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic cell. The overall design which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. SPICE simulations of the central part of the basic cell are presented which demonstrate its proper behaviour. The ternary circuit for GF(32 ) is compared to the binary circuit for GF(23) and is shown to be superior both in terms of the number of transistors and the number of connections View full abstract»

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  • Helena Rasiowa-a view of the academic trajectory and the influence upon Polish and international scientific community

    Page(s): 144 - 146
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    The death of H. Rasiowa was a big loss for both, the Polish and the international scientific community. The life of Professor Rasiowa was passionately devoted to the development of logic, algebra and computer science and brought the fruits already reckoned among the results of the highest importance. The influence of her personality goes far beyond Poland and the group of logicians, mathematicians and computer scientists View full abstract»

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  • Technique of computing logic derivatives for MVL-functions

    Page(s): 267 - 272
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    A technique to compute logic derivatives of MVL-functions is considered based on four algorithms, two of them are new. At first these are symbolic and matrix algorithms to find logic derivatives with respect to variables, and, secondly, partial direct and inverse derivatives. The algorithms are compared by using an example of testing a MVL switching circuit. The matrix approach allows to extract the appropriatenesses of computing process and to come to some simple operators of logic processing truth vectors of MVL functions View full abstract»

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