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[1991] Proceedings Pacific Rim International Symposium on Fault Tolerant Systems

26-27 Sept. 1991

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Displaying Results 1 - 25 of 40
  • A 2-rail logic combinational circuit with easy detection of stuck-open and stuck-on faults in FETs

    Publication Year: 1991, Page(s):252 - 257
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (413 KB)

    A design method for a 2-rail logic combinational circuit is proposed, where stuck-open and stuck-on faults in FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, OR and AND, are also added to the circuit as fault observing gates. A test can be easily generated and fault observation is easy. Stuck-at f... View full abstract»

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  • An approach to optimal DFT using partial parallel scan

    Publication Year: 1991, Page(s):246 - 251
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB)

    Because traditional scan design techniques such as LSSD, scan path, and random access scan suffer from the drawback that the extra test application effort is quite significant, the partial parallel scan technique has been presented. This new technique reduces test application effort by 1 or 2 orders of magnitude. A way to get a circuit design which best improves testability greatly by using the pa... View full abstract»

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  • An optimal design for parallel testing

    Publication Year: 1991, Page(s):240 - 245
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB)

    An integer linear programming (ILP) model is presented for the design of optimal parallel testing, which minimizes the index number of the maximal complete subgraph (MCS) in the parallel testing graph (PTG), therefore, making the index coloring number of the PTG minimal. The whole test time of a partitioned circuit is thus minimal. An optimal testing scheduling algorithm of a partitioned circuit i... View full abstract»

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  • Fault tolerant IC chip for crystal oscillators

    Publication Year: 1991, Page(s):232 - 237
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Some applications of multiprocessor systems require the system to synchronize their clocks with each other. There are many studies on fault-tolerant clock synchronization methods. However. algorithms proposed in previous work cannot achieve both tight synchronization and cost-effectiveness. To solve these two problems, the authors have proposed a construction method for a highly reliable clock gen... View full abstract»

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  • Critical issues in the design of a fault-tolerant multiprocessor database server

    Publication Year: 1991, Page(s):226 - 231
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (563 KB)

    HypRa is a database server designed to meet extreme requirements from e.g. telecom applications. Fault-tolerance has been designed into HypRa by: (1) taking it into account at all hard-ware and software levels, (2) using a shared-nothing, coarse grained hardware platform with homogeneous nodes, basic fault detection, and a multiway interconnection network with dynamic rerouting, (3) doing fault ma... View full abstract»

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  • Develop a real-time fault-tolerant computer

    Publication Year: 1991, Page(s):220 - 225
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB)

    The 980FT86 is a real-time fault-tolerant computer. Its development, objectives, system structure, fault-tolerant characteristics and reliability evaluation are discussed.<> View full abstract»

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  • Test generation for combinational circuits with multiple faults

    Publication Year: 1991, Page(s):212 - 217
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB)

    A test generated under the single-fault assumption may be invalid for the combinational circuit with multiple faults because of masking among them. The authors propose a new test generation algorithm for combinational circuits with multiple faults. A property of a valid test which can detect a target fault regardless of the presence of any other fault is studied and it is shown that a pair of inpu... View full abstract»

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  • Test generation algorithm for incomplete scan design circuits with tri-state devices

    Publication Year: 1991, Page(s):206 - 211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB)

    The paper describes a heuristic algorithm, DALG-EX18, for generating test patterns of incomplete scan design circuits with tri-state devices. The algorithm is based on the philosophy of the extended D-algorithm. Logic circuits consisting of gates, flip-flops and functional modules can be treated. Testability measures are utilized to accelerate D-drive and reduce the number of conflicts in the cons... View full abstract»

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  • Generation of test sequences for current testing

    Publication Year: 1991, Page(s):200 - 205
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB)

    In current testing, measuring the current with a rapid clock rate is a difficult problem, because a CMOS circuit causes a dynamic current. To overcome this problem, a testing circuit which measures the current, including the dynamic current, is proposed. Moreover, the authors describe a test generation method which generates suitable test sequences for proposed circuit. Generated test sequences ha... View full abstract»

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  • A new approach to specify real-time behavior of distributed systems

    Publication Year: 1991, Page(s):194 - 198
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB)

    Specification of real-time behavior of a system requires a significantly different approach compared to specification of the system's non-real-time behavior. Also, a specification formalism should be easy to use, conceptually simple, and should lead to an intuitive understanding about the specified behavior of the system. With these objectives, the authors develop an event-based approach to specif... View full abstract»

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  • Fault tolerance assurance methodology of the SXO operating system for continuous operation

    Publication Year: 1991, Page(s):182 - 187
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (559 KB)

    In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, the authors aimed to create an unprecedentedly high software and hardware fault tolerance. They devised a fault tolerant architecture and various methodologies to ensure fault tolerance. They implemented these techniques systematically throughout operating system development. In the design stage, they deve... View full abstract»

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  • A design method for cost-effective self-testing checker for optimal d-unidirectional error detecting codes

    Publication Year: 1991, Page(s):174 - 179
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB)

    Unidirectional/asymmetric error codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error detecting (d-UED) codes. The paper shows a design method for a cost-effective self-testing checker for... View full abstract»

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  • A design method of SFS and SCD combinational circuits

    Publication Year: 1991, Page(s):168 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Strongly fault-secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. The paper presents a new generalized design method for the SFS and SCD realization of combi... View full abstract»

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  • Designing multi-level quorum schemes for highly replicated data

    Publication Year: 1991, Page(s):154 - 159
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (531 KB)

    The authors present and analyze multi-level quorum schemes for maintaining the consistency of replicated data in the presence of concurrency and failures in a large distributed environment. The multi-level method operates on a logical hierarchy of replicas and applies well known flat voting algorithms in a layered fashion. They show how the number of hierarchy levels, the number of logical entitie... View full abstract»

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  • Incorporation of multiple errors in reliability modeling of fault-tolerant systems

    Publication Year: 1991, Page(s):148 - 153
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB)

    Many experiments have shown that most hardware faults do not cause immediately detectable errors. A significant proportion of the faults injected during experiments remained latent. The system operations, in which a hardware fault occurs, will remain error-free until the latent errors become effective. An effective error may, and in general does, propagate from component to another; and by propaga... View full abstract»

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  • A probabilistic diagnostic model in malicious environments and its algorithms

    Publication Year: 1991, Page(s):142 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Presents a new model, noted as (p,m)-diagnosable, which can probabilistically model malicious environments in a uniform manner. A heuristic-inference algorithm, an approximate diagnosability algorithm and two characterization theorems of (p,m)-diagnosable systems are given. The complexity of (p,m)-diagnosability is examined to be co-NP-complete. An example (p,m)-diagnosable system is given.<> View full abstract»

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  • Fault diagnosis for analog integrated circuits based on the circuit layout

    Publication Year: 1991, Page(s):134 - 139
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB)

    An approach to the fault diagnosis for analog integrated circuits is proposed. It uses fault models from the defect statistics to generate faulty circuits. Fault simulations are then applied to those faulty circuits to generate different fault classes which can be used for the fault diagnosis for analog integrated circuits. An example is also given to demonstrate this approach.<> View full abstract»

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  • Structural analysis of large digital circuits

    Publication Year: 1991, Page(s):128 - 133
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB)

    Structural analysis of large circuits is very important for circuit design and test. The paper gives a generic structural model of large circuits and proposes a new concept of separated-cone. An algorithm is given to partition a circuit into separated-cones, and to find all the maximal-supergates in each separated-cone. After partitioning, the circuit fits for the generic structural model. This ki... View full abstract»

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  • A tool for computation of output code spaces in complex self-checking systems

    Publication Year: 1991, Page(s):122 - 127
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (582 KB)

    In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of ... View full abstract»

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  • Minimum number of links needed for fault-tolerance in cluster-based network

    Publication Year: 1991, Page(s):114 - 119
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    One of the most difficult problems in network management for large computer networks is to manage a huge amount of network information. The way to overcome the difficulty is to introduce hierarchical control for network management. Additionally, it is said that a locality has a very important role for the design of hierarchical computer networks. The paper proposes a new fault-tolerant topology in... View full abstract»

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  • Spare channel assignment for restoration in fault-tolerant loop network

    Publication Year: 1991, Page(s):108 - 113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB)

    The authors consider a computer network, which provides working channels and spare channels for each link, and restores working channels on a faulty link by spare channels on other links. For such a fault-tolerant network, spare channels must be carefully assigned on each link beforehand. However, it is said that finding an efficient assignment for a general network is time consuming, since it is ... View full abstract»

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  • Fault tolerant multi-processor communication systems using bank memory switching

    Publication Year: 1991, Page(s):188 - 193
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB)

    The paper proposes a new fault tolerant communication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed communication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element o... View full abstract»

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  • Self-testing checkers for arithmetic codes with any check base A

    Publication Year: 1991, Page(s):162 - 167
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The design of self-testing checkers (STCs) for all arithmetic codes (AN codes, residue codes, and inverse residue codes) with any odd check base A is presented. The design of these checkers is based on the use of recently proposed highly-parallel schemes of the generators modulo A using carry-save adders and/or ROM. The new STCs cover a significantly larger spectrum of check bases A than the desig... View full abstract»

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  • C/sub 3/-a powerful connection network for fault tolerance

    Publication Year: 1991, Page(s):102 - 107
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB)

    A new connection network is presented to provide fault tolerance through reconfiguration in WSI. The connection network C/sub k/-gives a high probability of survival in the presence of faults with little delay and a small hardware overhead. C/sub k/ is a switched bus network implementing a mesh-connected array. It is flexible, powerful, and has small hardware overhead cost in comparison to two oth... View full abstract»

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  • A method of shuffling compactor inputs in VLSI self-testing

    Publication Year: 1991, Page(s):96 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB)

    Shuffling interconnections between CUT outputs and the output response compactor inputs is proposed as a scheme to decrease aliasing probability. A spot error is defined as a multiple bit error adjacent in space and in time. The condition for preventing aliasing for a predetermined size of single spot error is presented. Block based shuffling and the shortened one are proposed to realize the requi... View full abstract»

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