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Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on

Date 26-27 Sept. 1991

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  • Proceedings. Pacific Rim International Symposium on Fault Tolerant Systems (Cat. No.91TH0384-8)

    Publication Year: 1991
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  • Incorporation of multiple errors in reliability modeling of fault-tolerant systems

    Publication Year: 1991, Page(s):148 - 153
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Many experiments have shown that most hardware faults do not cause immediately detectable errors. A significant proportion of the faults injected during experiments remained latent. The system operations, in which a hardware fault occurs, will remain error-free until the latent errors become effective. An effective error may, and in general does, propagate from component to another; and by propaga... View full abstract»

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  • Designing multi-level quorum schemes for highly replicated data

    Publication Year: 1991, Page(s):154 - 159
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors present and analyze multi-level quorum schemes for maintaining the consistency of replicated data in the presence of concurrency and failures in a large distributed environment. The multi-level method operates on a logical hierarchy of replicas and applies well known flat voting algorithms in a layered fashion. They show how the number of hierarchy levels, the number of logical entitie... View full abstract»

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  • Data level fault tolerance in demultiplexer filter banks

    Publication Year: 1991, Page(s):63 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    An efficient method for demultiplexing frequency slotted channels employs multirate filter banks which contain fast Fourier transform processing. All numerical processing is performed at a lower rate commensurate with the small bandwidth of each baseband channel. The paper demonstrates methods for protecting the integrity of the demultiplexing operations by using real number convolutional codes to... View full abstract»

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  • Fault tolerant IC chip for crystal oscillators

    Publication Year: 1991, Page(s):232 - 237
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Some applications of multiprocessor systems require the system to synchronize their clocks with each other. There are many studies on fault-tolerant clock synchronization methods. However. algorithms proposed in previous work cannot achieve both tight synchronization and cost-effectiveness. To solve these two problems, the authors have proposed a construction method for a highly reliable clock gen... View full abstract»

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  • A design method of SFS and SCD combinational circuits

    Publication Year: 1991, Page(s):168 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Strongly fault-secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. The paper presents a new generalized design method for the SFS and SCD realization of combi... View full abstract»

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  • Fault-tolerant attribute evaluation in distributed software environments

    Publication Year: 1991, Page(s):76 - 81
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A formal description of distributed software environments can be specified naturally by applying attribute grammars. In this approach, how to update efficiently attribute values of subproducts is a key problem. Although many algorithms have been proposed to solve this problem, most of them are no longer applicable when some workstations become inaccessible from others by certain faults. The paper ... View full abstract»

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  • An optimal design for parallel testing

    Publication Year: 1991, Page(s):240 - 245
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    An integer linear programming (ILP) model is presented for the design of optimal parallel testing, which minimizes the index number of the maximal complete subgraph (MCS) in the parallel testing graph (PTG), therefore, making the index coloring number of the PTG minimal. The whole test time of a partitioned circuit is thus minimal. An optimal testing scheduling algorithm of a partitioned circuit i... View full abstract»

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  • A design method for cost-effective self-testing checker for optimal d-unidirectional error detecting codes

    Publication Year: 1991, Page(s):174 - 179
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Unidirectional/asymmetric error codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error detecting (d-UED) codes. The paper shows a design method for a cost-effective self-testing checker for... View full abstract»

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  • Comparison of aliasing probability for multiple MISRs and M-stage MISRs with m inputs

    Publication Year: 1991, Page(s):90 - 95
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    MISRs are widely used as signature circuits for VLSI built-in self-tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is greater than m. The aliasing probability as a function of the test length for these signature circuits is analyzed for a binary symmetric channel. It is shown that the peak aliasing probability of the double... View full abstract»

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  • An approach to optimal DFT using partial parallel scan

    Publication Year: 1991, Page(s):246 - 251
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Because traditional scan design techniques such as LSSD, scan path, and random access scan suffer from the drawback that the extra test application effort is quite significant, the partial parallel scan technique has been presented. This new technique reduces test application effort by 1 or 2 orders of magnitude. A way to get a circuit design which best improves testability greatly by using the pa... View full abstract»

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  • On fault tolerance of reconfigurable arrays using spare processors

    Publication Year: 1991, Page(s):10 - 15
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Addresses fault tolerance of a processor array that is reconfigurable by replacing faulty processors with spare processors. The fault tolerance of such a reconfigurable processor array depends on not only an algorithm for spare processor assignment but also an organization of spare processors in the reconfigurable array. The paper discusses a relationship between fault tolerance of reconfigurable ... View full abstract»

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  • Structural analysis of large digital circuits

    Publication Year: 1991, Page(s):128 - 133
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Structural analysis of large circuits is very important for circuit design and test. The paper gives a generic structural model of large circuits and proposes a new concept of separated-cone. An algorithm is given to partition a circuit into separated-cones, and to find all the maximal-supergates in each separated-cone. After partitioning, the circuit fits for the generic structural model. This ki... View full abstract»

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  • An O(N log22N) fault-tolerant decentralized commit protocol

    Publication Year: 1991, Page(s):44 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A new decentralized commit protocol is proposed for distributed database systems. This protocol can be applied to any size of systems and is [log2N]-2 resilient to site failures where N is the number of sites in the system. In addition, the number of messages sent among N sites is O(N log22N) which is only a fac... View full abstract»

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  • An algebraic specification of a daisy chain arbiter

    Publication Year: 1991, Page(s):24 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    There have been few studies on formal approaches to the specification and realization of asynchronous digital circuits. The paper describes an algebraic method of specifying the abstract behavior of an asynchronous daisy chain arbiter as an example of them. In asynchronous circuits, changes of inputs cause state transitions. Thus the states after transitions are determined by the states before the... View full abstract»

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  • Fault tolerance assurance methodology of the SXO operating system for continuous operation

    Publication Year: 1991, Page(s):182 - 187
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, the authors aimed to create an unprecedentedly high software and hardware fault tolerance. They devised a fault tolerant architecture and various methodologies to ensure fault tolerance. They implemented these techniques systematically throughout operating system development. In the design stage, they deve... View full abstract»

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  • Test generation algorithm for incomplete scan design circuits with tri-state devices

    Publication Year: 1991, Page(s):206 - 211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    The paper describes a heuristic algorithm, DALG-EX18, for generating test patterns of incomplete scan design circuits with tri-state devices. The algorithm is based on the philosophy of the extended D-algorithm. Logic circuits consisting of gates, flip-flops and functional modules can be treated. Testability measures are utilized to accelerate D-drive and reduce the number of conflicts in the cons... View full abstract»

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  • A method of shuffling compactor inputs in VLSI self-testing

    Publication Year: 1991, Page(s):96 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Shuffling interconnections between CUT outputs and the output response compactor inputs is proposed as a scheme to decrease aliasing probability. A spot error is defined as a multiple bit error adjacent in space and in time. The condition for preventing aliasing for a predetermined size of single spot error is presented. Block based shuffling and the shortened one are proposed to realize the requi... View full abstract»

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  • A probabilistic diagnostic model in malicious environments and its algorithms

    Publication Year: 1991, Page(s):142 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Presents a new model, noted as (p,m)-diagnosable, which can probabilistically model malicious environments in a uniform manner. A heuristic-inference algorithm, an approximate diagnosability algorithm and two characterization theorems of (p,m)-diagnosable systems are given. The complexity of (p,m)-diagnosability is examined to be co-NP-complete. An example (p,m)-diagnosable system is given View full abstract»

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  • Error propagation codes

    Publication Year: 1991, Page(s):58 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    An <m> error at bit i causes bits i , i+1, . . ., and i+m-1 (or up to the end of the word) to be in error, inflicting m consecutive errors. An <m>t-ec/d-ed code denotes a code which is able to correct any t<m> errors and detect any d<... View full abstract»

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  • Critical issues in the design of a fault-tolerant multiprocessor database server

    Publication Year: 1991, Page(s):226 - 231
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    HypRa is a database server designed to meet extreme requirements from e.g. telecom applications. Fault-tolerance has been designed into HypRa by: (1) taking it into account at all hard-ware and software levels, (2) using a shared-nothing, coarse grained hardware platform with homogeneous nodes, basic fault detection, and a multiway interconnection network with dynamic rerouting, (3) doing fault ma... View full abstract»

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  • A 2-rail logic combinational circuit with easy detection of stuck-open and stuck-on faults in FETs

    Publication Year: 1991, Page(s):252 - 257
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A design method for a 2-rail logic combinational circuit is proposed, where stuck-open and stuck-on faults in FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, OR and AND, are also added to the circuit as fault observing gates. A test can be easily generated and fault observation is easy. Stuck-at f... View full abstract»

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  • Experimental validation of distributed recovery block

    Publication Year: 1991, Page(s):82 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents the experimental validation of distributed execution of recovery blocks, in short distributed recovery blocks (DRB). The experiment was conducted on a tightly coupled network (TCN) and a time-critical application was used as a testbed for the experiment. The concept of the DRB is the combination of distributed processing and RB (recovery block). It is also an approach for unified treatmen... View full abstract»

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  • A tool for computation of output code spaces in complex self-checking systems

    Publication Year: 1991, Page(s):122 - 127
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of ... View full abstract»

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  • Evaluation of a new algorithm for fault-tolerant clock synchronization

    Publication Year: 1991, Page(s):38 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Synchronous clocks are an essential requirement for a variety of distributed system applications. Many of these applications are safety-critical and require fault tolerance. The paper presents a general probabilistic clock synchronization model. This model is uniformly probabilistic, incorporating random message delays, random clock drifts; and random fault occurrences. The model allows faults in ... View full abstract»

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