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IEEE Standard for VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification

  • IEEE Standard for VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification

    Publication Year: 1996
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    The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate efficient simulation models for ASIC components in VHDL. View full abstract»

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