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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

14-16 Oct. 1991

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Displaying Results 1 - 25 of 129
  • How to design a parallel computer

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (18 KB)

    Summary form only given, as follows. Computer designers of the 1990s will be able to exploit many years of research into the design of parallel computers. The demands of embedded processing, general purpose computing and supercomputing in the 1990s are far beyond the capabilities of sequential computers. Component designers will use VLSI to produce supercomponents for processing, memory and interc... View full abstract»

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  • Neural networks update

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (18 KB)

    Summary form only given, as follows. Neural networks have been intensively studied as a discipline in their own right in the last five years (late 1980s, early 1990s). Initial claims were extremely ambitious; by using the brain's computing principles, networks would eliminate programming, revolutionize computer architecture and sensor interfacing, make analog VLSI a reality, and give guidance to a... View full abstract»

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  • Design and test-the two sides of a coin

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB)

    Summary form only given. The automation of the design and test of VLSI circuits is discussed. Principles that the author believes will guide the design and test methodology of the future are stated. They are: the principle of hierarchy, the principle of orthogonality, the principle of standardization, and computing resource sharing. The principles apply equally to design and test, strengthening th... View full abstract»

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  • Gigascale integration (GIS) in the 21st century

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (35 KB)

    Summary form only given. Opportunities for incorporation of more than one billion transistors and associated interconnections with a single silicon chip or for gigascale integration (GSI) are governed by a hierarchy of limits whose levels can be codified as fundamental, material, device, circuit, and system. Each level of this hierarchy includes both theoretical and practical limits. Theoretical l... View full abstract»

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  • IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (389 KB)
    Freely Available from IEEE
  • The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order

    Publication Year: 1991, Page(s):524 - 527
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a power... View full abstract»

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  • Aliasing probability in multiple input linear signature automata for q-ary symmetric errors

    Publication Year: 1991, Page(s):352 - 355
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The aliasing probability in single and multiple input linear automata signature registers (LASRs: linear feedback shift registers (LFSRs) and linear cellular automata) has been widely studied under the independent bit error model. Aliasing in a class of multiple-input LASRs (MILASRs) under the q-ary symmetric error model is examined. By modeling the signature analyzer as a two state Marko... View full abstract»

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  • Area optimization for higher order hierarchical floorplans

    Publication Year: 1991, Page(s):520 - 523
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a... View full abstract»

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  • Design considerations for digital circuit interconnections in a multilayer printed circuit board

    Publication Year: 1991, Page(s):472 - 478
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The design considerations of signal lines in a multilayer printed circuit board are discussed. The effect of the orthogonal lines on the impedance, delay, and signal cross-talk is investigated for a single line and two coupled lines. The effect of loading and cross-over lines in the memory card design is also discussed View full abstract»

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  • Enhanced chip/package design for the IBM ES/9000

    Publication Year: 1991, Page(s):544 - 549
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    The automatic placement and wiring programs used for design of the gate array bipolar chips, the TCM logical design optimization for timing, and the automated module wiring programs of the ES/9000 machines are described. An overview of related aspects of the chip and module technologies is given View full abstract»

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  • An optical multichip module

    Publication Year: 1991, Page(s):490 - 493
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    As integrated circuit technology improvements result in increased device speed, designers are forced to adopt new forms of packaging and interconnect such as multichip modules. A description is given of how planar optical interconnect techniques may be combined with a multichip module process to provide optical interconnect within the substrate. Several possible applications of the technology are ... View full abstract»

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  • A formally verified system for logic synthesis

    Publication Year: 1991, Page(s):346 - 350
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The correctness of a logic synthesis system is implemented and proved. The algorithm is based on the weak division algorithm for Boolean simplification previously presented. The implementation is in the programming language ML; and the proof is in the Nuprl proof development system. This study begins with a proof of the algorithm previously presented and extends it to a level of detail sufficient ... View full abstract»

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  • Implicit manipulation of equivalence classes using binary decision diagrams

    Publication Year: 1991, Page(s):81 - 85
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    A novel representation called an equivalence class characterization function is defined. It can implicitly represent all equivalence classes with a compact characteristic function that will have at most n outputs. Using binary decision diagrams (BDDs) and the concept of the equivalence class characterization function, very large problem instances can be represented. For manipulating equiv... View full abstract»

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  • A built-in self-testing approach for minimizing hardware overhead

    Publication Year: 1991, Page(s):282 - 285
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques View full abstract»

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  • Partitioning sequential circuits for logic optimization

    Publication Year: 1991, Page(s):70 - 76
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The concepts of corolla partitioning based on an analysis of signal reconvergence to cyclic sequential circuits are extended. The sequential circuit is partitioned into corollas that will contain latches but can be peripherally retimed and resynthesized using combinational techniques. Cycles are broken in the circuit by ensuring that the partitions that are formed are acyclic. Application of the p... View full abstract»

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  • An optimal algorithm for spiral floorplan designs

    Publication Year: 1991, Page(s):516 - 519
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    An improved algorithm for solving the area optimization problem of spiral floorplans is presented. Each of the five basic rectangles of a spiral floorplan have O(n) implementations. The algorithm takes O(n2logn) time, and requires O(n2) space to solve the area optimization problem. The best previously known algori... View full abstract»

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  • Accessibility analysis on data flow graph: an approach to design for testability

    Publication Year: 1991, Page(s):463 - 466
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nod... View full abstract»

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  • Self-timed logic using current-sensing completion detection (CSCD)

    Publication Year: 1991, Page(s):187 - 191
    Cited by:  Papers (19)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encodi... View full abstract»

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  • Verification techniques for a MIPS compatible embedded control processor

    Publication Year: 1991, Page(s):329 - 332
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The methods used in the verification of a MIPS-1 architecture-compatible embedded control processor are described. This single-chip processor contains 700000 transistors, operates at 50 MHz, and consists of a CPU core, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, a write buffer, three timers, and a bus interface unit (BIU). Individual module testing and integrated system testi... View full abstract»

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  • Concurrent error detection in array dividers by alternating input data

    Publication Year: 1991, Page(s):114 - 117
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Concurrent error detection (CED) schemes utilizing time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using an alternating logic (AL) approach is proposed. The key to the detection of faults using the AL approach is determining th... View full abstract»

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  • IBM ES/9000 system architecture and hardware

    Publication Year: 1991, Page(s):540 - 543
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    A description is given how IBM's Enterprise Systems requirements for data management are implemented in the ES/9000 process series. The ES/9000 processor family is the next step in efficient data movement/management for data that reside anywhere in the Enterprise. To manage this vast amount of data, certain high end ES/9000 models utilize four levels of memory (L1 or first level cache, L2 or secon... View full abstract»

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  • A simulator for general purpose optical arrays

    Publication Year: 1991, Page(s):486 - 489
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Architectures based on optical arrays offer the promise of massive parallelism and three-dimensional computing. The design of an integrated general purpose optical or electrooptical machine is a formidable task. The simulation of these technologies using electronic computers allows a number of designs for such machines to be explored. The general purpose simulator for electrooptical arrays present... View full abstract»

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  • A fast division algorithm for VLSI

    Publication Year: 1991, Page(s):560 - 563
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A novel and fast method for VLSI division is presented. The method is based on Svoboda's algorithm and uses the radix-2 signed-digit number system to give a divider in which quotient bit selection is a function of the two most significant digits of the current partial remainder. An n-bit divider produces an n-bit quotient in redundant form in 3n gate delays using n View full abstract»

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  • F-RISC/G: AlGaAs/GaAs HBT standard cell library

    Publication Year: 1991, Page(s):297 - 300
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps View full abstract»

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  • Specifying system behavior in CPA

    Publication Year: 1991, Page(s):342 - 345
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    CPA (conditions, precedence relations and assertions), a framework for specifying the behavior of control-oriented digital systems, is described. CPA allows the expression of sequential behavior, data transformations and timing constraints in an integrated representation. It supports the abstract, declarative specification of behavior independent of any particular implementation. Thus it is especi... View full abstract»

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