[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

14-16 Oct. 1991

Filter Results

Displaying Results 1 - 25 of 129
  • How to design a parallel computer

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (18 KB)

    Summary form only given, as follows. Computer designers of the 1990s will be able to exploit many years of research into the design of parallel computers. The demands of embedded processing, general purpose computing and supercomputing in the 1990s are far beyond the capabilities of sequential computers. Component designers will use VLSI to produce supercomponents for processing, memory and interc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Neural networks update

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (18 KB)

    Summary form only given, as follows. Neural networks have been intensively studied as a discipline in their own right in the last five years (late 1980s, early 1990s). Initial claims were extremely ambitious; by using the brain's computing principles, networks would eliminate programming, revolutionize computer architecture and sensor interfacing, make analog VLSI a reality, and give guidance to a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and test-the two sides of a coin

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (69 KB)

    Summary form only given. The automation of the design and test of VLSI circuits is discussed. Principles that the author believes will guide the design and test methodology of the future are stated. They are: the principle of hierarchy, the principle of orthogonality, the principle of standardization, and computing resource sharing. The principles apply equally to design and test, strengthening th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Gigascale integration (GIS) in the 21st century

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (35 KB)

    Summary form only given. Opportunities for incorporation of more than one billion transistors and associated interconnections with a single silicon chip or for gigascale integration (GSI) are governed by a hierarchy of limits whose levels can be codified as fundamental, material, device, circuit, and system. Each level of this hierarchy includes both theoretical and practical limits. Theoretical l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3)

    Publication Year: 1991
    Request permission for commercial reuse | |PDF file iconPDF (389 KB)
    Freely Available from IEEE
  • Technologies for rapid prototyping of multi-chip modules

    Publication Year: 1991, Page(s):588 - 592
    Cited by:  Papers (16)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (588 KB)

    Component technologies are described to be used in the maskless customization of multi-chip modules (MCMs) including: laser processes for linking and cutting conductors; an interconnect net routing tool; and MCM assembly, test, and electrical characterization methods. Each component technology was successfully demonstrated through independent tests. The first integrated demonstration of these tech... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a self-testing checker for Borden code

    Publication Year: 1991, Page(s):582 - 585
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (308 KB)

    A Borden code is an optimal code capable of detecting t-unidirectional errors. A new self-testing checker (STC) for Borden code is proposed. It is built of two blocks: a self-testing code-disjoint translator of the Borden code onto the one-out-of-r code (r⩾4) and a well-known STC for the one-out-of- r code. The translator is built of two multi-output thresh... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Object caching for performance in object-oriented systems

    Publication Year: 1991, Page(s):379 - 385
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (632 KB)

    Object-oriented systems exhibit a very high rate of object creation, but most objects are short-lived. As a result, memory-management overhead is significant. An application-specific coprocessor architecture to speed up object creation and memory reclamation in object-oriented systems is described. The architecture supports a bit-vector approach to dynamic storage allocation and liberation. Novel ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and synthesis of self-checking VLSI circuits and systems

    Publication Year: 1991, Page(s):578 - 581
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    Self-checking circuits and systems can detect the presence of both transient and permanent faults. The advantage of such a system is that errors can be caught as soon as they occur, and thus data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient pattern match architecture for production systems using content-addressable memory

    Publication Year: 1991, Page(s):374 - 378
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    A novel and efficient content-addressable pattern match architecture (CAPMA) is proposed to speed up the execution time of the match process of a production system. CAPMA compiles the left-hand side (LHS) of each production into an efficient symbolic form, and creates an effective symbolic accessing mechanism based on a two-level content-addressable memory (CAM) structure for computing the conflic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DesignFab: a methodology for ULSI microprocessor design

    Publication Year: 1991, Page(s):136 - 139
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    A novel design methodology and CAD tool set are described and successfully used in the design of a 100 MIPS superscalar ULSI microprocessor with DSP capabilities for embedded applications. The design process starts with the architecture definition, and a high level behavioral model is written. This model is then synthesized into a gate level description which is translated into a description to be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel event-driven waveform relaxation

    Publication Year: 1991, Page(s):101 - 104
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (432 KB)

    The implementation of asynchronous waveform relaxation on parallel processors is discussed. Three different approaches, all based on event-driven scheduling techniques, are compared to the standard data-flow scheme. Issues involving the use of priority queues and preemptive scheduling are described. Circuit examples are used to demonstrate that good speedup can be achieved by using the event-drive... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Enhanced chip/package design for the IBM ES/9000

    Publication Year: 1991, Page(s):544 - 549
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (652 KB)

    The automatic placement and wiring programs used for design of the gate array bipolar chips, the TCM logical design optimization for timing, and the automated module wiring programs of the ES/9000 machines are described. An overview of related aspects of the chip and module technologies is given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New classes of unidirectional error-detecting codes

    Publication Year: 1991, Page(s):574 - 577
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    Unidirectional errors arise as a result of common VLSI failure modes and certain connection faults, particularly with serial data transmission. A totally ordered set of symbols to be encoded in an order-preserving manner for unidirectional error detection is considered. General order-preserving encoding and the special case of difference-preserving encoding, (when the value ν is encoded with it... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simulator for general purpose optical arrays

    Publication Year: 1991, Page(s):486 - 489
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    Architectures based on optical arrays offer the promise of massive parallelism and three-dimensional computing. The design of an integrated general purpose optical or electrooptical machine is a formidable task. The simulation of these technologies using electronic computers allows a number of designs for such machines to be explored. The general purpose simulator for electrooptical arrays present... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A tag coprocessor architecture for symbolic languages

    Publication Year: 1991, Page(s):370 - 373
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    A novel architecture is presented for the efficient execution of symbolic languages on conventional von Neumann, register-based machines. Unlike other symbolic processing architectures, this is based on a tag coprocessor (TC) which is designed to work in parallel with a conventional RISC CPU such as the MIPS R3000. The TC performs almost all the tag manipulation operations independently of the CPU... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations

    Publication Year: 1991, Page(s):132 - 135
    Cited by:  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    The system architecture of a low cost PA-RISC workstation is described. This architecture is implemented in Hewlett-Packard's 9000 series 700 workstations. High performance and low cost are achieved through careful system partitioning and appropriate application of integration. The system design involved the development of four ASICs: a memory I/O system controller, a mixing buffer chip, a DRAM ad... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power play-fast dynamic power estimation based on logic simulation

    Publication Year: 1991, Page(s):96 - 100
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    A fast algorithm and a tool for the estimation of dynamic power dissipation in digital circuits are presented. The logic waveforms generated by a standard logic simulator are used in order to compute an instantaneous power waveform at the gate- (cell-) level. The tool itself is technology independent; it takes parameters for the currently used cell library from a database that has been established... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IBM ES/9000 system architecture and hardware

    Publication Year: 1991, Page(s):540 - 543
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (244 KB)

    A description is given how IBM's Enterprise Systems requirements for data management are implemented in the ES/9000 process series. The ES/9000 processor family is the next step in efficient data movement/management for data that reside anywhere in the Enterprise. To manage this vast amount of data, certain high end ES/9000 models utilize four levels of memory (L1 or first level cache, L2 or secon... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed VLSI arithmetic processor architectures using hybrid number representation

    Publication Year: 1991, Page(s):564 - 571
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    The design of high-speed architectures is addressed for fixed-point, two's-complement, bit-parallel, pipelined, multiplication, division and square-root operations. The architectures presented make use of hybrid number representations (i.e. the input and output numbers are presented using two's complement representation, and the internal numbers are represented using radix-2 redundant representati... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast capacitance extraction of general three-dimensional structures

    Publication Year: 1991, Page(s):479 - 484
    Cited by:  Papers (10)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    Several improvements to the multipole-accelerated 3-D capacitance extraction program previously described are presented. A new adaptive multipole algorithm is given, and a preconditioning strategy for accelerated iterative method convergence is described. Results using these algorithms to compute the capacitance of general three-dimensional structures are presented, and they demonstrate that the m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stafan algorithms for MOS circuits

    Publication Year: 1991, Page(s):56 - 59
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    Novel models and algorithms for MOS transmission gates, buses and functional memories for use in statistical fault analysis (Stafan) are described. A bus is modeled as a multiple input multiplexer with feedback to account for its memory state. A CMOS transmission gate, modeled as a unidirectional device, always feeds into a bus that processes the high impedance state. Novel algorithms are devised ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • I/O pad assignment based on the circuit structure

    Publication Year: 1991, Page(s):314 - 318
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    An algorithm is presented for assigning off-chip I/O pads for a logic circuit. The technique, which is based on the analysis of the circuit structure and path delay constraints, uses linear placement, goal-programming, linear-sum assignment and I/O pad clustering to assign locations to I/O pads. The I/O pad assignment is then used by placement tools. Experimental data show that as a result of usin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Operation method in fuzzy set operation processor

    Publication Year: 1991, Page(s):366 - 369
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB)

    A VLSI for diverse fuzzy set operations (FSP: fuzzy set processor) uses a single instruction multiple data stream (SIMD) architecture that is composed of four basic operation units and a variable microprogram control circuit. Speed increases of 50 times over a RISC-type CPU are possible when executing fuzzy set operations using a 16 basic operation unit (four processor) SIMD architecture View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A built-in self-testing approach for minimizing hardware overhead

    Publication Year: 1991, Page(s):282 - 285
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.