Proceedings ED&TC European Design and Test Conference

11-14 March 1996

Filter Results

Displaying Results 1 - 25 of 120
  • Proceedings of European Design and Test Conference

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (629 KB)
    Freely Available from IEEE
  • Silicon technology: risks, opportunities, and challenges

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (113 KB)

    The impressive progress in microelectronics technology over the last two decades has delivered an enormous increase in computational power and storage capacity at ever decreasing cost per function. The general consensus an industry and academia is that this exponential growth in complexity will continze for at least 15 more years. Further progress will require an interdiscaplinary approach compris... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Future of testing: Reintegration of design, testing and manufacturing

    Publication Year: 1996
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB)

    For at least last 20 years dkroelectronics has been evolving rapidly tracking - almost without a single deviation - Moore's Law. At the beginning of nineteen nineties some level of concern was expressed whether continuing along Moore?????????s prediction makes economic sense. As a response to the above and other concerns in 1993 and 1994 the Semiconductor Industry Association (SIA) has proposed ??... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Addressing the Challenges of System-On-A-Chip Design

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    Summary form only given, as follows. While systems-on-silicon (SOS) products can range from cellular phones to 200-pound avionics communications and navigation systems, they present common problems to the EDA and semiconductor industries. First, SOS applications demand very high levels of integration and functionality, which can only be met through new sub-micron IC technologies. Second, they embr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The use of microelectronics for future telecom and multimedia systems

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (46 KB)

    Summary form only given, as follows. As a world-leader in telecommunication and multimedia system developments, Alcatel-Bell will present the main trends and challenges for the coming years for microelectronic system design in these domains. Political objectives stimulate competition today: privatization and liberalization are currently changing the world telecom market. The continuous evolution i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Perturb and simplify: optimizing circuits with external don't cares

    Publication Year: 1996, Page(s):402 - 406
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Earlier optimization techniques based on Automatic Test Pattern Generation could not handle external don't cares. We propose a technique that uses external don't cares during the ATPG guided logic optimization. This technique transforms external don't cares into internal don't cares. Thus, the optimization can utilize the external don't cares to obtain better results. Additionally, we also discuss... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI design of a high speed soft decision Viterbi detector

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Summary form only given. The design of a Viterbi detector for high speed disk drive channels is presented. The detector is a soft decision detector that operates on a time varying trellis based on a matched spectral null code. The design was developed by creating a high-level model of the system to resolve high-level design issues. Standard design tools were used for logic simulation and layout ge... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal specification of a reactive system: an exercise in VHDL, LOTOS and UNITY

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (103 KB)

    Summary form only given. We are developing a specification and proof environment, called PREVAIL, which is to support several input languages (currently, only VHDL is supported) and which proposes a set of proof tools to verify appropriate descriptions/specifications. Nqthm is one of these tools, and we are working at defining an induction-based method to validate concurrent systems using this pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generalized Recognition Of Gates: a VLSI abstraction tool

    Publication Year: 1996
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Summary form only given. The Generalized Recognition Of Gates is an innovative and technology independent tool of abstraction. It translates any VLSI or ASIC microelectronic circuit from its netlist format into both VHDL and VERILOG descriptions which express its behavior. The CMOS, NMOS, bipolar and BiCMOS technologies can all be handled. One of the most important characteristics of the tool is t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A combined pairing and chaining algorithm for CMOS layout generation

    Publication Year: 1996
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (99 KB)

    Summary form only given. As CMOS VLSI circuits increment, their complexity and specifications become more aggressive, automatic layout generators gain popularity. These tools divide their task into a set of steps that include transistor pairing, chaining, sizing, placement of diffusion strips and routing. In each of these steps a high optimization degree is required in order to achieve good result... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-checking and fault tolerant approaches can help BIST fault coverage: a case study

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (109 KB)

    Summary form only given. We describe the design of an FIFO component with BIST capabilities. The component is now being used in the Italtel standard library and is exploited in several industrial designs. Our main contribution is to show how the effectiveness of complex BIST design can be improved, and brought to acceptable fault coverage levels, through the coupling with more advanced test archit... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Applying behavioural level test generation to high-level design validation

    Publication Year: 1996
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (118 KB)

    Summary form only given. The methods for verifying an implementation with respect to the specified behavioural VHDL description are not sufficiently developed yet. Therefore the correct behaviour of the implementation has to be validated by simulation. Since it is impossible to simulate the implementation completely, suitable simulation patterns have to be selected for executing statements, operat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of test modules for the analysis of MCM interconnects

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB)

    Summary form only given. A thin-film Multichip Module (MCM-D) switching unit, specifically designed for performance analysis of interconnection substrates, is described. A test approach is presented for the characterisation of a given device technology as a function of geometrical, physical and electrical quantities-in this particular case, a MCM-D technology and a 0.7 /spl mu/m CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System fault diagnosis based on a fuzzy qualitative approach

    Publication Year: 1996
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (117 KB)

    Summary form only given. A novel automated approach combining structural description and fuzzy logic for both sequential and combinational system fault diagnosis is presented. It does not use any specific fault model. The software implementing this method is described, and some experimental results are provided. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An automated design environment for micromechanical sensors

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB)

    Summary form only given. In this paper, we present a computer-aided design system for MicroMechanical Sensors (MMS). Moreover, it allows designer to improve automatically MMS response by the means of dimensions or shape modification of their design. Our system has a modular architecture centered around a widespread Finite-Element (FE) code, Ansys. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Methods and tools for the design of electrostatic micromotors

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB)

    Summary form only given. In this paper the methodology of the design of electrostatic micromotors is discussed. Field computation is performed by the finite element method (FEM). Automated modelling and evaluation of the quantities of the electrostatic field in combination with an equivalent circuit technique leads to an efficient design tool. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (215 KB)
    Freely Available from IEEE
  • Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations

    Publication Year: 1996, Page(s):186 - 193
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    Parity prediction arithmetic operator schemes have the advantage that they are compatible with data paths and memory systems checked by parity codes. Nevertheless, the basic drawback of these schemes is that they may not be fault secure for single faults, since they propagate multiple output errors that are undetectable by the parity code. In this paper we derive necessary and sufficient condition... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designing self-testable multi-chip modules

    Publication Year: 1996, Page(s):181 - 185
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This paper addresses the problem of Multi-Chip Module (MCM) testing, and specifically testing assembled MCM performance. The presented solution is based-on self-test. It augments the conventional single-chip BIST approach, which is needed to produce known-good-dies, to a new multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. This self-test mode not only provi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A specification invariant technique for regularity improvement between flow-graph clusters

    Publication Year: 1996, Page(s):138 - 143
    Cited by:  Papers (11)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In this paper, we present a new technique that improves the regularity between two or more flow-graph clusters (partitions) by means of algebraic transformations, operating at the word-level. Regularity improvement is aimed at decreasing the sharing overhead incurred by sharing clusters of flow-graph on the same resource. It is modelled as an operator cost minimization problem. The technique consi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in self test architectures for multistage interconnection networks

    Publication Year: 1996, Page(s):176 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A novel built-in self test architecture for locally controlled cube-type N×N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel analog module generator environment

    Publication Year: 1996, Page(s):388 - 392
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    This paper describes a novel analog module generator environment for the automatic layout development of analog circuits. The C++ tool features a novel procedural layout description language that drastically eases the creation of analog modules. Due to the object oriented programming the designer can specify the modules in a hierarchical way using elementary geometrical primitives and conditional ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Relay propagation scheme for testing of MCMs on large area substrates

    Publication Year: 1996, Page(s):131 - 135
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    This paper addresses the issue of testing MCMs on large area substrates. The cost of testing MCMs may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a parallel and pipelined relay propagation scheme for the testing of MCMs on la... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Economics modelling and optimisation of MCM test strategies

    Publication Year: 1996
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    This paper presents a decision support system for the objective evaluation and optimisation of MCM test options, including boundary scan provision. The system is driven by a detailed cost model of the MCM manufacture and test process. The cost modelling can be extended to model the partial scan provision View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design kit for microsystems design for an enhanced CMOS process

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    We propose a design methodology and CAD tools for microsystems fabrication based on the 1.0 mm CMOS process from ES2. In order to profit from vendor cell libraries, tools have to enhance their own design kit. Main contributions are, sensor dependent technology file, device modeling and automatic generation for different ranges, and adaptation of semi-custom tools (simulation environment and P&... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.