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Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on

Date 12-14 Feb. 1996

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  • Proceedings of Fifth International Conference on Microelectronics for Neural Networks

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (260 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (100 KB)
    Freely Available from IEEE
  • Adaptive two-dimensional neuron grids

    Publication Year: 1996, Page(s):246 - 250
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    In the last decade many early-vision tasks have been cast into the form of global optimization principles: their solution is obtained by the minimization of appropriate cost functions. The minimization procedure, which consists in most cases of a simple gradient descent, often yields a two-dimensional particle model with local exchange interaction. Our starting point is a quite general representat... View full abstract»

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  • Spectral analysis and synthesis of three-layered feed-forward neural networks for function approximation

    Publication Year: 1996, Page(s):239 - 245
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The universal approximation capability exhibited by one-hidden-layer neural network is explored to create a new synthesis method for minimized architectures suited for VLSI implementation. The development is based on the spectral analysis of the network, which focuses their capability of combining single neurons spectra to obtain the spectrum of the function to approximate. In this paper, we propo... View full abstract»

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  • A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN)

    Publication Year: 1996, Page(s):232 - 237
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    We present the architecture of a a neurocomputer for the simulation of spike-processing biological neural networks (NESPINN). It consists mainly of a neuron state memory, two connectivity units, a spike-event list, a sector unit and the NESPINN chip with a control unit, and eight PEs with 2 kB local on-chip memory each. In order to increase the performance features such as mixed SIMD/dataflow mode... View full abstract»

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  • A current mode CMOS multi-layer perceptron chip

    Publication Year: 1996, Page(s):103 - 106
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the t... View full abstract»

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  • SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training

    Publication Year: 1996, Page(s):227 - 231
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We report on the development of a high-performance system for neural network and other signal processing applications. We have designed and implemented a vector microprocessor and packaged it as an attached processor for a conventional workstation. We present performance comparisons with workstations on neural network backpropagation training. The SPERT-II system demonstrates roughly 15 times the ... View full abstract»

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  • Neuron-MOS-based association hardware for real-time event recognition

    Publication Year: 1996, Page(s):94 - 101
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Neuron MOS transistor (υMOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a ful... View full abstract»

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  • Design of a low-cost and high-speed neurocomputer system

    Publication Year: 1996, Page(s):221 - 226
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    This paper presents a new parallel computer architecture for high-speed emulation of any neural network model. The system is based on a new ASIC (Application Specific Integrated Circuit) that performs all required arithmetical operations. The essential feature of this ASIC is its ability to adapt the internal parallelism dynamically to the data precision for achieving an optimal utilization of the... View full abstract»

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  • A Hindmarsh and Rose-based electronic burster

    Publication Year: 1996, Page(s):39 - 44
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The design of an electronic oscillator based on the Hindmarsh and Rose model of bursting neurons is presented. Because of hardware area requirements, the original model is reduced to a system of two coupled differential equations by means of a hysteresis function. The phase plane analysis of the Hindmarsh and Rose model emphasizes the dynamical properties underlying the bursts generation. These fu... View full abstract»

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  • Low-power analog fuzzy rule implementation based on a linear MOS transistor network

    Publication Year: 1996, Page(s):86 - 93
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An analog fuzzy rule circuit is proposed, which is based on a network of MOS transistors exploited as linear resistive elements. A low number of transistors are needed for each rule circuit, because the same devices cumulate several processing steps of the computation. Another property of the circuit is that the power consumed by a given rule is nearly zero when the weight of that rule is zero. Th... View full abstract»

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  • A scalable architecture for binary couplings attractor neural networks

    Publication Year: 1996, Page(s):213 - 220
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    This paper presents a digital architecture with on-chip learning for Hopfield attractor neural networks with binary weights. A new learning rule for the binary weights network is proposed that allows pattern storage up to capacity α=0.4 and incurs very low hardware overhead. Due to the use of binary couplings the network has minimal storage requirements. A flexible communication structure al... View full abstract»

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  • Analog VLSI circuits for covert attentional shifts

    Publication Year: 1996, Page(s):30 - 37
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    In this paper we present analog very large-scale integrated (aVLSI) circuits that facilitate the selection process for initiating and mediating attentive visual processing. We demonstrate the performance of these circuits within a system that implements covert attentional shifts based on an input array that represents saliency across the visual field. The selection process, which enables the trans... View full abstract»

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  • Implementation of time-multiplexed CNN building block cell

    Publication Year: 1996, Page(s):80 - 85
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    We have proposed an area efficient implementation of Cellular Neural Network by using the time-multiplexed method. This paper describes the underlying theory, method, and the circuit architecture of a VLSI implementation. Spice simulation results have been obtained to illustrate the circuit operation. A building block cell of a time-multiplexed cellular neural network has been completed and is cur... View full abstract»

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  • On-line hand-printing recognition with neural networks

    Publication Year: 1996, Page(s):201 - 212
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    The need for fast and accurate text entry on small handheld computers has led to a resurgence of interest in on-line word recognition using artificial neural networks. Classical methods have been combined and improved to produce robust recognition of hand-printed English text. The central concept of a neural net as a character classifier provides a good base for a recognition system; long-standing... View full abstract»

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  • An efficient handwritten digit recognition method on a flexible parallel architecture

    Publication Year: 1996, Page(s):355 - 362
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large applicatio... View full abstract»

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  • The FAST architecture: a neural network with flexible adaptable-size topology

    Publication Year: 1996, Page(s):337 - 340
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    One of the central problems in the application of neural networks is finding the optimal network topology. This paper introduces the FAST architecture (flexible adaptable-size topology), an on-line, evolving neural network that dynamically adapts its topology through interactions with a problem-specific environment. We present a fully digital implementation of the network and demonstrate its viabi... View full abstract»

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  • Topological mapping formation in a neural network with variations of device characteristics

    Publication Year: 1996, Page(s):277 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The neural network of a human brain can well perform higher-order-information processing which could not be achieved by Neuman-type computers. In order to perform the processing, it is necessary to fabricate artificial neural systems which can form the topological mapping through learning. A new learning algorithm and a new network model have been proposed for fabrication by means of CMOS analog c... View full abstract»

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  • Motion detection silicon retina based on event correlations

    Publication Year: 1996, Page(s):23 - 29
    Cited by:  Papers (4)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    This article reports on a functional two-dimensional analog silicon retina performing motion detection along three directions at 120 degrees of each other and 2 speed channels per direction. The output of each channel is binary, however integration of this information over time yields an analog value. Motion detection is performed by correlation of events, which are the disappearance of edges. A r... View full abstract»

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  • Array-based analog computation: principles, advantages and limitations

    Publication Year: 1996, Page(s):68 - 79
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    Analog implementations of neural networks and other computing architectures have gained increasing interest over the last decade. The field is at a critical juncture: continued interest will depend on the ability to demonstrate a clear advantage over digital solutions to problems of commercial interest. The neural network design group at SGS-Thomson Microelectronics has been working to explore the... View full abstract»

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  • A digital neural network LSI using sparse memory access architecture

    Publication Year: 1996, Page(s):139 - 148
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    A sparse memory access architecture is proposed to achieve a high-computational-speed neural network LSI. The architecture uses two key techniques, compressible synapse weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neurons. Calculations without an accuracy penalty. In a pattern recognition example, the num... View full abstract»

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  • A low-power Neuro-Fuzzy pulse stream system

    Publication Year: 1996, Page(s):191 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit View full abstract»

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  • A CMOS implementation of fuzzy controllers based on adaptive membership function ranges

    Publication Year: 1996, Page(s):317 - 321
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    This paper presents a compact current-mode CMOS design for the implementation of fuzzy controllers, using membership functions with variable output ranges. This design aims to avoid the division operation required to obtain the final crisp output. A feedback block is included, whose complexity does not depend on the number of rules of the fuzzy controller, thus the circuit can be applied to very c... View full abstract»

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  • Direct synthesis of neural networks

    Publication Year: 1996, Page(s):257 - 264
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    The paper overviews recent developments of a VLSI-friendly, constructive algorithm as well as detailing two extensions. The problem is to construct a neural network when m examples of n inputs are given (classification problem). The two extensions discussed are: (i) the use of analog comparators; and (ii) digital as well as analog solution to XOR-like problems. For a simple example (the two-spiral... View full abstract»

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  • Low power, low voltage conductance-mode CMOS analog neuron

    Publication Year: 1996, Page(s):111 - 115
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Analog implementations of neural networks have been used for a wide variety of tasks especially in the area of image processing. Typically, implementations of analog neural networks have been based on the use of either current or charge as the variable of computation. This work introduces a new class of analog neural network circuits based on the concept of conductance-mode computation. In this cl... View full abstract»

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