Proceedings of Fifth International Conference on Microelectronics for Neural Networks

12-14 Feb. 1996

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  • Proceedings of Fifth International Conference on Microelectronics for Neural Networks

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (260 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (100 KB)
    Freely Available from IEEE
  • The FAST architecture: a neural network with flexible adaptable-size topology

    Publication Year: 1996, Page(s):337 - 340
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    One of the central problems in the application of neural networks is finding the optimal network topology. This paper introduces the FAST architecture (flexible adaptable-size topology), an on-line, evolving neural network that dynamically adapts its topology through interactions with a problem-specific environment. We present a fully digital implementation of the network and demonstrate its viabi... View full abstract»

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  • VIP: an FPGA-based processor for image processing and neural networks

    Publication Year: 1996, Page(s):330 - 336
    Cited by:  Papers (10)  |  Patents (53)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    The present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture, together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware de... View full abstract»

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  • Implementation of a biologically inspired neuron-model in FPGA

    Publication Year: 1996, Page(s):322 - 329
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    This paper presents the implementation of a biologically inspired neuron-model. Learning is performed on-line in special synapses based on the biologically proved Hebbian learning algorithm. This algorithm is implemented on-chip allowing an architecture of autonomous neural units. The algorithm is transparent so connections between the neurons can easily be engineered. Due to their functionality a... View full abstract»

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  • On-line hand-printing recognition with neural networks

    Publication Year: 1996, Page(s):201 - 212
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    The need for fast and accurate text entry on small handheld computers has led to a resurgence of interest in on-line word recognition using artificial neural networks. Classical methods have been combined and improved to produce robust recognition of hand-printed English text. The central concept of a neural net as a character classifier provides a good base for a recognition system; long-standing... View full abstract»

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  • A CMOS implementation of fuzzy controllers based on adaptive membership function ranges

    Publication Year: 1996, Page(s):317 - 321
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    This paper presents a compact current-mode CMOS design for the implementation of fuzzy controllers, using membership functions with variable output ranges. This design aims to avoid the division operation required to obtain the final crisp output. A feedback block is included, whose complexity does not depend on the number of rules of the fuzzy controller, thus the circuit can be applied to very c... View full abstract»

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  • A correlation-based network for hardware implementations

    Publication Year: 1996, Page(s):251 - 256
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    An architecture and learning rules for a correlation-based network are proposed. Hidden activity predictors dynamically compute local temporal receptive field centres through a decorrelation process. Temporal feedback loops between units in the hidden layer are then used to synchronise the activities of similar near by units. The simultaneous activation of different topologically overlapping unit ... View full abstract»

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  • A low-power Neuro-Fuzzy pulse stream system

    Publication Year: 1996, Page(s):191 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit View full abstract»

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  • A BiCMOS implementation of the Hodgkin-Huxley formalism

    Publication Year: 1996, Page(s):311 - 316
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper presents an analog design of a biologically inspired neuron model: the conductance-based Hodgkin-Huxley formalism. After a description of the model equations set, the corresponding subcircuits are detailed. ASICs were fabricated in a 2 μm BiCMOS technology, and have a block structure allowing the constitution of complex cells or small networks. As an application, numerical and analog... View full abstract»

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  • L-Neuro 2.3: a VLSI for image processing by neural networks

    Publication Year: 1996, Page(s):157 - 160
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Real-time and embedded applications of image processing like pattern recognition, shape analysis etc. (using classical or less classical methods such as neural networks) are computer intensive tasks that lead to complex systems. Furthermore, the skyrocketting demand for those techniques has led to a flurry of algorithms that must be rapidly implemented, evaluated and finally tuned to real-world ca... View full abstract»

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  • Adaptive two-dimensional neuron grids

    Publication Year: 1996, Page(s):246 - 250
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    In the last decade many early-vision tasks have been cast into the form of global optimization principles: their solution is obtained by the minimization of appropriate cost functions. The minimization procedure, which consists in most cases of a simple gradient descent, often yields a two-dimensional particle model with local exchange interaction. Our starting point is a quite general representat... View full abstract»

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  • PANNE: a parallel computing engine for connectionist simulation

    Publication Year: 1996, Page(s):363 - 368
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    PANNE (Parallel Artificial Neural Network Engine) is a parallel computing engine aimed at delivering super-computing power to numerical applications such as connectionist simulation and signal processing. The PANNE system exploits the features of the TMS320C40 DSP chip which make it suitable for building parallel computing systems. PANNE has been built with flexibility in mind; it is expandable in... View full abstract»

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  • Teaching pulsed integrated neural systems: a psychobiological approach

    Publication Year: 1996, Page(s):185 - 190
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    In this paper, we present a continuous time version of a differential Hebbian learning algorithm for pulsed neural systems with non-linear synapses. We argue that future analogue integrated implementations of artificial neural networks with on-chip learning must take as a starting point the basic properties of the technology. In particular asynchronous and inherently offset free, simple circuit st... View full abstract»

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  • Low-power analog fuzzy rule implementation based on a linear MOS transistor network

    Publication Year: 1996, Page(s):86 - 93
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An analog fuzzy rule circuit is proposed, which is based on a network of MOS transistors exploited as linear resistive elements. A low number of transistors are needed for each rule circuit, because the same devices cumulate several processing steps of the computation. Another property of the circuit is that the power consumed by a given rule is nearly zero when the weight of that rule is zero. Th... View full abstract»

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  • Application of terminal dynamics in cellular neural networks

    Publication Year: 1996, Page(s):305 - 310
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Terminal dynamics is a new nonlinear phenomenon based on the violation of the Lipschitz-condition. The characteristic features, like terminal attractors and repellers, are interesting for artificial neural networks. Because this subject was only discussed in a theoretical way, VLSI system concepts with terminal dynamics have not yet been developed. Therefore we combine the principles of terminal d... View full abstract»

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  • On-chip backpropagation training using parallel stochastic bit streams

    Publication Year: 1996, Page(s):149 - 156
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    It is proposed to use stochastic arithmetic computing for all arithmetic operations of training and processing backpropagation nets. In this way it is possible to design simple processing elements which fulfil all the requirements of information processing using values coded as independent stochastic bit streams. Combining such processing elements silicon saving and full parallel neural networks o... View full abstract»

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  • A current mode CMOS multi-layer perceptron chip

    Publication Year: 1996, Page(s):103 - 106
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the t... View full abstract»

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  • Spectral analysis and synthesis of three-layered feed-forward neural networks for function approximation

    Publication Year: 1996, Page(s):239 - 245
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The universal approximation capability exhibited by one-hidden-layer neural network is explored to create a new synthesis method for minimized architectures suited for VLSI implementation. The development is based on the spectral analysis of the network, which focuses their capability of combining single neurons spectra to obtain the spectrum of the function to approximate. In this paper, we propo... View full abstract»

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  • An efficient handwritten digit recognition method on a flexible parallel architecture

    Publication Year: 1996, Page(s):355 - 362
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large applicatio... View full abstract»

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  • SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training

    Publication Year: 1996, Page(s):227 - 231
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We report on the development of a high-performance system for neural network and other signal processing applications. We have designed and implemented a vector microprocessor and packaged it as an attached processor for a conventional workstation. We present performance comparisons with workstations on neural network backpropagation training. The SPERT-II system demonstrates roughly 15 times the ... View full abstract»

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  • Pulsed VLSI for RBF neural networks

    Publication Year: 1996, Page(s):177 - 184
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    This paper presents simulation and hardware results from cascadable circuits for pulsed Radial Basis Function (RBF) neural network chips. The functionality of each circuit is clearly demonstrated from the hardware results and consideration is also given to the practical issues affecting the development of a pulsed RBF demonstrator chip View full abstract»

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  • Implementation of time-multiplexed CNN building block cell

    Publication Year: 1996, Page(s):80 - 85
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    We have proposed an area efficient implementation of Cellular Neural Network by using the time-multiplexed method. This paper describes the underlying theory, method, and the circuit architecture of a VLSI implementation. Spice simulation results have been obtained to illustrate the circuit operation. A building block cell of a time-multiplexed cellular neural network has been completed and is cur... View full abstract»

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  • Computational image sensors for on-sensor-compression

    Publication Year: 1996, Page(s):297 - 304
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    In this paper, we propose novel image sensors which compress image signal. By making use of very fast analog processing on the imager plane, the compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging.... View full abstract»

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  • An analogue electronic model of Ventral Cochlear Nucleus neurons

    Publication Year: 1996, Page(s):52 - 59
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    This paper proposes a simple analogue electronic spiking neuron circuit, which can be used to create hardware models of biological neural systems. In spite of its simplicity, the circuit is able to simulate a variety of different neuron types. Measurements of the neuron model in various settings am compared with the physiological response of certain neuron types in the Ventral Cochlear Nucleus, i.... View full abstract»

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