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Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on

Date 12-14 Feb. 1996

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  • Proceedings of Fifth International Conference on Microelectronics for Neural Networks

    Publication Year: 1996
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996
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    Freely Available from IEEE
  • An analogue electronic model of Ventral Cochlear Nucleus neurons

    Publication Year: 1996 , Page(s): 52 - 59
    Cited by:  Papers (8)
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    This paper proposes a simple analogue electronic spiking neuron circuit, which can be used to create hardware models of biological neural systems. In spite of its simplicity, the circuit is able to simulate a variety of different neuron types. Measurements of the neuron model in various settings am compared with the physiological response of certain neuron types in the Ventral Cochlear Nucleus, i.e., part of the first relay station in the brainstem of the auditory pathway. A good analogy between the response of the circuit and the different neurons has been obtained View full abstract»

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  • Direct synthesis of neural networks

    Publication Year: 1996 , Page(s): 257 - 264
    Cited by:  Papers (4)
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    The paper overviews recent developments of a VLSI-friendly, constructive algorithm as well as detailing two extensions. The problem is to construct a neural network when m examples of n inputs are given (classification problem). The two extensions discussed are: (i) the use of analog comparators; and (ii) digital as well as analog solution to XOR-like problems. For a simple example (the two-spirals), we are able to show that the algorithm does a very “efficient” encoding of a given problem into the neural network it “builds”-when compared to the entropy of the given problem and to other learning algorithms. We are also able to estimate the number of bits needed to solve any classification problem for the general case. Being interested in the VLSI implementation of such networks, the optimum criteria are not only the classical size and depth, but also the connectivity and the number of bits for representing the weights-as such measures are closer estimates of the area and lead to better approximations of the AT2 View full abstract»

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  • Single electron tunneling technology for neural networks

    Publication Year: 1996 , Page(s): 125 - 130
    Cited by:  Papers (7)
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    A new neural network hardware concept based on single electron tunneling is presented. Single electron tunneling transistors have some advantageous properties which make them very attractive to make neural networks, among which their very small size, extremely low power consumption and potentially high speed. After a brief description of the technology, the relevant properties of SET transistors are described. Simulations have been performed on some small circuits of SET transistors that exhibit functional properties similar to those required for neural networks. Finally, interconnecting the building blocks to form a neural network is analyzed View full abstract»

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  • On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation

    Publication Year: 1996 , Page(s): 168 - 175
    Cited by:  Papers (3)
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    A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation View full abstract»

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  • A variable-precision systolic architecture for ANN computation

    Publication Year: 1996 , Page(s): 347 - 354
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    When Artificial Neural Networks (ANNs) are implemented in VLSI with fixed precision arithmetic, the accumulation of numerical errors may lead to results which are completely inaccurate. To avoid this, we propose a variable-precision arithmetic in which the precision of the computation is specified by the user at each layer in the network. This paper presents a top-down approach for designing an efficient bit-level systolic architecture for variable precision neural computation View full abstract»

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  • Topological mapping formation in a neural network with variations of device characteristics

    Publication Year: 1996 , Page(s): 277 - 284
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    The neural network of a human brain can well perform higher-order-information processing which could not be achieved by Neuman-type computers. In order to perform the processing, it is necessary to fabricate artificial neural systems which can form the topological mapping through learning. A new learning algorithm and a new network model have been proposed for fabrication by means of CMOS analog circuits with variations of device characteristics. The functions of those circuits were confirmed by means of SPICE simulations and the functions of PDM (pulse density modulator) were confirmed experimentally. The learning simulations of the network consisting of the circuits have also been carried out. The results show that the topological mapping is almost formed, even when variations of device characteristics exist in the neural network. The results also reveal that calculating the weighted sum of each neuron's potential and potentials of its surrounding neurons as the output of each neuron and adding proper number of redundant neurons to the output layer are effective mechanisms for the network with variations of device characteristics View full abstract»

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  • Neuron-MOS-based association hardware for real-time event recognition

    Publication Year: 1996 , Page(s): 94 - 101
    Cited by:  Papers (1)
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    Neuron MOS transistor (υMOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry View full abstract»

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  • Computational image sensors for on-sensor-compression

    Publication Year: 1996 , Page(s): 297 - 304
    Cited by:  Papers (1)  |  Patents (4)
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    In this paper, we propose novel image sensors which compress image signal. By making use of very fast analog processing on the imager plane, the compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging. The compression sensor consists of three parts; transducer, memory and processor. Two architectures for on-sensor-compression are discussed in this paper that are pixel parallel architecture and column parallel architecture. In the former architecture, the three parts are put together in each pixel, and processing is pixel parallel. In the latter architecture, transducer, processor and memory areas are separated, and processing is column parallel. We also describe a prototype chip of pixel-parallel-type sensor with 32×32 pixels which has been fabricated using 2 μm CMOS technology. Some results of examinations are shown in this paper View full abstract»

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  • Low-power analog fuzzy rule implementation based on a linear MOS transistor network

    Publication Year: 1996 , Page(s): 86 - 93
    Cited by:  Papers (4)
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    An analog fuzzy rule circuit is proposed, which is based on a network of MOS transistors exploited as linear resistive elements. A low number of transistors are needed for each rule circuit, because the same devices cumulate several processing steps of the computation. Another property of the circuit is that the power consumed by a given rule is nearly zero when the weight of that rule is zero. This property enables an efficient use of power in integrated circuits containing fuzzy rule arrays, since normally only a few rules are active simultaneously. In addition, the proposed circuit features an analog center-of-gravity defuzzification circuit which can process digitally stored parameters without local D/A conversion. A completely functional research prototype with 80 rules was fabricated in a 2 μm CMOS technology. The chip core area is 1.32 mm2, the power consumption is 850 nW with a 1.8 V supply, and the 90% settling time in response to an input step is less than 400 μs View full abstract»

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  • Simulated annealing of binary fields using an optoelectronic circuit

    Publication Year: 1996 , Page(s): 131 - 137
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    A new approach to the VLSI implementation of stochastic cellular networks is demonstrated. Arrays of high throughput Gaussian noise sources are obtained thanks to the transduction of random patterns imaged onto an opto-electronic analog-digital circuit. A 4×4 cells prototype chip was implemented in a 1 μm CMOS technology. It was successfully tested and operated at 100 kHz. This led us to the design of a 24×24 prototype View full abstract»

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  • Analog VLSI circuits for covert attentional shifts

    Publication Year: 1996 , Page(s): 30 - 37
    Cited by:  Papers (8)
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    In this paper we present analog very large-scale integrated (aVLSI) circuits that facilitate the selection process for initiating and mediating attentive visual processing. We demonstrate the performance of these circuits within a system that implements covert attentional shifts based on an input array that represents saliency across the visual field. The selection process, which enables the transition from preattentive to attentive processing, uses knowledge of previous selections and appropriate duration of selections to perform its task. The circuitry uses local feedback to create a hysteretic effect in the switching from one location of attention to the next. We also include an inhibition-of-return mechanism to facilitate shifting the location of attention even when the input array remains constant. We present test data from a one-dimensional version of the system View full abstract»

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  • On-line hand-printing recognition with neural networks

    Publication Year: 1996 , Page(s): 201 - 212
    Cited by:  Papers (4)  |  Patents (1)
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    The need for fast and accurate text entry on small handheld computers has led to a resurgence of interest in on-line word recognition using artificial neural networks. Classical methods have been combined and improved to produce robust recognition of hand-printed English text. The central concept of a neural net as a character classifier provides a good base for a recognition system; long-standing issues relative to training generalization, segmentation, probabilistic formalisms, etc., need to resolved, however, to get adequate performance. A number of innovations in how to use a neural net as a classifier in a word recognizer are presented: negative training, stroke warping, balancing, normalized output error, error emphasis, multiple representations, quantized weights, and integrated word segmentation all contribute to efficient and robust performance View full abstract»

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  • A BiCMOS implementation of the Hodgkin-Huxley formalism

    Publication Year: 1996 , Page(s): 311 - 316
    Cited by:  Papers (5)
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    This paper presents an analog design of a biologically inspired neuron model: the conductance-based Hodgkin-Huxley formalism. After a description of the model equations set, the corresponding subcircuits are detailed. ASICs were fabricated in a 2 μm BiCMOS technology, and have a block structure allowing the constitution of complex cells or small networks. As an application, numerical and analog computations of the action potentials are compared, and the effects of some model parameters modifications are shown View full abstract»

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  • Pulsed VLSI for RBF neural networks

    Publication Year: 1996 , Page(s): 177 - 184
    Cited by:  Papers (5)
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    This paper presents simulation and hardware results from cascadable circuits for pulsed Radial Basis Function (RBF) neural network chips. The functionality of each circuit is clearly demonstrated from the hardware results and consideration is also given to the practical issues affecting the development of a pulsed RBF demonstrator chip View full abstract»

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  • An efficient handwritten digit recognition method on a flexible parallel architecture

    Publication Year: 1996 , Page(s): 355 - 362
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    This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large application spectrum to the machine, making it possible to implement heterogeneous algorithms efficiently involving both low level (computing intensive) and high level (control intensive) tasks. We first introduce the ArMenX project and the main architecture features. Then, after giving details on the computing of propagation and back-propagation of the multi-layer perceptron on ArMenX, we will focus on a handwritten digit (issued from a zip code data base) recognition application. An original and efficient method, involving three neural networks, is developed. The first two neural networks deal with the `reading process', and the last neural network, which learned to write, helps to make decisions on the first two network outputs, when they are not confident. Before concluding, the paper presents the work of integration of ArMenX into a high level programming environment, designed to make it easier to take advantage of the architecture flexibility View full abstract»

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  • A scalable processor array for self-organizing feature maps

    Publication Year: 1996 , Page(s): 285 - 291
    Cited by:  Papers (4)
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    Selforganizing Feature Maps (SOFMs) can be applied for data analysis, controlling problems and pattern matching. In many cases the requirements of a system using these maps are high performance and small physical size. This leads to the necessity of custom chip designs. In this paper two chips are presented, that realize a scalable processor array for self-organizing feature maps. First the design and test results of a single processor chip are described. Based on these results a second chip has been developed implementing a 5 by 5 array of elements. Each processor has on-chip memory to store 64 weights of 8 bit. The calculation unit has an internal precision of 14 bit. An input pattern can have 64 vector components of 8 bit. In order to achieve high speed, all elements work in parallel. Several of this chips can be cascaded to larger map sizes in a system View full abstract»

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  • Retinomorphic vision systems

    Publication Year: 1996 , Page(s): 2 - 14
    Cited by:  Papers (14)
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    The new generation of silicon retinae has two defining characteristics. First, these synthetic retinae are morphologically equivalent to their biological counterparts-at an appropriate level of abstraction. Second, they accomplish all four major operations performed by biological retinae using neurobiological principles: (1) continuous sensing for detection, (2) local automatic gain control for amplification, (3) spatiotemporal bandpass filtering for preprocessing, and (4) adaptive sampling for quantization. The author introduces the term retinomorphic to refer to this subclass of the neuromorphic electronic systems. Their design principles are compared and contrasted with the standard practice in imager design. It is argued that neurobiological principles are best suited to perceptive systems that go beyond reproducing the dynamic scene, like a conventional video camera does, to extracting salient information in real time. The results from a fully operational retinomorphic vision system are presented and the trade-offs involved in its design are discussed View full abstract»

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  • Analog VLSI system for active drag reduction

    Publication Year: 1996 , Page(s): 45 - 51
    Cited by:  Papers (2)
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    We describe an analog CMOS VLSI system that can process real-time signals from surface-mounted shear stress sensors to detect regions of high shear stress along a surface in an airflow. The outputs of the CMOS circuit are used to actuate micromachined flaps with the goal of reducing this high shear stress on the surface and thereby lowering the total drag. We have designed, fabricated, and tested parts of this system in a wind tunnel in laminar and turbulent flow regimes View full abstract»

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  • A current mode CMOS multi-layer perceptron chip

    Publication Year: 1996 , Page(s): 103 - 106
    Cited by:  Papers (2)
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    An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the total average power consumption is around 200 mW. This is equivalent to a computational power of about 2.5×109 connections per second. The chip can be employed in a chip-in-the-loop neural architecture View full abstract»

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  • A modified RBF neural network for efficient current-mode VLSI implementation

    Publication Year: 1996 , Page(s): 265 - 270
    Cited by:  Papers (12)
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    A modified RBF neural network model is proposed allowing efficient VLSI implementation in both analog or digital technology. This model is based essentially on replacing the standard Gaussian basis function with a piece-wise linear one and on using a fast allocation unit learning algorithm for determination of unit centers. The modified RBF approximates optimally Gaussians for the whole range of parameters (radius and distance). The learning algorithm is fully on-line and easy to be implemented in VLSI using the proposed neural structures for on-line signal processing tasks. Applying the standard test problem of the chaotic time series prediction, the functional performances of different RBF networks were compared. Experimental results show that the proposed architecture outperforms the standard RBF networks, the main advantages being related with low hardware requirements and fast learning while the learning algorithm can be also efficient embedded in silicon. A suggestion for current-mode implementation is presented together with considerations regarding the computational requirements of the proposed model for digital implementations View full abstract»

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  • Application of terminal dynamics in cellular neural networks

    Publication Year: 1996 , Page(s): 305 - 310
    Cited by:  Papers (1)
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    Terminal dynamics is a new nonlinear phenomenon based on the violation of the Lipschitz-condition. The characteristic features, like terminal attractors and repellers, are interesting for artificial neural networks. Because this subject was only discussed in a theoretical way, VLSI system concepts with terminal dynamics have not yet been developed. Therefore we combine the principles of terminal dynamics with cellular neural networks and illustrate our idea by means of a first application. An analog CMOS circuit operating in the subthreshold region is presented for a future VLSI implementation View full abstract»

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  • A scalable architecture for binary couplings attractor neural networks

    Publication Year: 1996 , Page(s): 213 - 220
    Cited by:  Papers (1)
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    This paper presents a digital architecture with on-chip learning for Hopfield attractor neural networks with binary weights. A new learning rule for the binary weights network is proposed that allows pattern storage up to capacity α=0.4 and incurs very low hardware overhead. Due to the use of binary couplings the network has minimal storage requirements. A flexible communication structure allows cascading of multiple chips in order to build fully connected, block connected, or feed-forward networks. System performance and communication bandwidth scale linear with the number of chips. A prototype chip has been fabricated and is fully functional. A pattern recognition application shows the performance of the binary couplings network View full abstract»

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  • A low-power Neuro-Fuzzy pulse stream system

    Publication Year: 1996 , Page(s): 191 - 199
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    This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit View full abstract»

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