By Topic

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date 3-6 Jan. 1996

Filter Results

Displaying Results 1 - 25 of 96
  • 1995 IEEE Fellowship Awards

    Publication Year: 1996
    Request Permissions | PDF file iconPDF (294 KB)  
    Freely Available from IEEE
  • 1995 Awards

    Publication Year: 1996
    Request Permissions | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 1996
    Request Permissions | PDF file iconPDF (167 KB)  
    Freely Available from IEEE
  • Behavioral modeling of an ATM switch using SpecCharts

    Publication Year: 1996 , Page(s): 19 - 22
    Request Permissions | Click to expandAbstract | PDF file iconPDF (304 KB)  

    ATM networking promises to usher in a new era in network technology by providing an integrated network that can be used to transmit voice, video, image, interactive data and bulk data at very high speeds. An ATM switch enables the routing of data packets through the ATM network. In this paper, we describe the development of a behavioral model for an ATM switch using SpecCharts. The SpecCharts lang... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Instruction level power analysis and optimization of software

    Publication Year: 1996 , Page(s): 326 - 328
    Cited by:  Papers (115)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (368 KB)  

    Software constitutes a major component of today's systems, and its role is projected to continue to grow. This motivates the need for analyzing power consumption from the point of view of software-something that circuit and gate level power analysis tools are inadequate for. This paper describes an alternative, measurement based instruction level power analysis approach that provides ran accurate ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel allocation strategy for control and memory intensive telecommunication circuits

    Publication Year: 1996 , Page(s): 23 - 28
    Cited by:  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (528 KB)  

    Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to seve... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VaWiRAM: a variable width random access memory module

    Publication Year: 1996 , Page(s): 219 - 224
    Cited by:  Patents (50)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (548 KB)  

    Presents the design of a variable width RAM (VaWiRAM) which will be extremely useful in building flexible memory systems. Principles of reconfigurability of programmable logic and programmable interconnect is incorporated into random access memories to achieve this flexibility. The chip can be reconfigured by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between wid... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Retiming with logic duplication transformation: theory and an application to partial scan

    Publication Year: 1996 , Page(s): 296 - 302
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (664 KB)  

    Retiming when performed in conjunction with logic duplication results in many different circuit configurations that are not obtainable by retiming alone. These circuit configurations (we call RLD configurations) have significantly different area, performance and testability characteristics. We develop a formal framework that allows consideration of all configurations that can be designed using the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wiresizing with buffer placement and sizing for power-delay tradeoffs

    Publication Year: 1996 , Page(s): 346 - 351
    Cited by:  Papers (6)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (520 KB)  

    With the increasing influence of the resistive effects of interconnects on the performance of VLSI systems, a greater stress is being laid on careful interconnect design. One prominent technique is the approach of sizing wires for long interconnects to achieve the desired speed and power characteristics. It has also been suggested that one may appropriately insert repeaters for significant delay r... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design tradeoffs in high speed multipliers and FIR filters

    Publication Year: 1996 , Page(s): 29 - 32
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (400 KB)  

    In this paper, we study the effects of modified Booth recoding, pipeline granularity and clocking on the speed, power dissipation and transistor count of different types of multipliers and FIR filters. Detailed simulations show that recoding may not always result in an improvement in delay. We propose a way of reducing the activity factor of a Booth multiplier by guarded evaluation. As systems bec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Node-covering based defect and fault tolerance methods for increased yield in FPGAs

    Publication Year: 1996 , Page(s): 225 - 229
    Cited by:  Papers (18)  |  Patents (19)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (524 KB)  

    Fault tolerant techniques are proposed which make use of the reconfigurability of SRAM-based field programmable gate arrays (FPGAs). Based on the principle of node-covering, a routing discipline is developed that reserves unused wiring in the routing channels to allow each cell to cover (to be able to replace) its neighbor in a row. If testing identifies a faulty cell, switches are set to reconfig... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultra low power digital signal processing

    Publication Year: 1996 , Page(s): 352 - 357
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (516 KB)  

    The explosive growth of portable wireless devices has elevated power consumption to be one of the most critical design parameters. This paper presents several techniques to implement DSP functions with the lowest possible power consumption. Since power is consumed only when capacitance is being switched, power can be reduced by minimizing this capacitance through operation reduction, choice of dat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimation of power from module-level netlists

    Publication Year: 1996 , Page(s): 324 - 325
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (208 KB)  

    Existing power estimation tools work on gate-level netlists and cannot be readily adapted for module-level circuits. Flattening the module-level netlist to gate level for purposes of power estimation and subsequent application of a gate-level estimation algorithm are both cumbersome tasks, demanding excessive amounts of CPU time and memory. We present a Module-level Power Estimation tool called MO... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Does retiming affect redundancy in sequential circuits?

    Publication Year: 1996 , Page(s): 260 - 263
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (352 KB)  

    Retiming is used to optimize logic and improve the speed of operation in sequential circuits keeping the circuit behavior unchanged. In this paper, we show with various examples that retiming affects redundancy of faults. It may change an operationally redundant fault to a partially one, and a combinationally redundant fault to an irredundant but sequentially untestable fault. Many novel transform... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On test coverage of path delay faults

    Publication Year: 1996 , Page(s): 418 - 421
    Cited by:  Papers (10)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB)  

    We propose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called “line delay test”, is a path delay test for the longest sensiti... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-cost DC built-in self-test of linear analog circuits using checksums

    Publication Year: 1996 , Page(s): 230 - 233
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (340 KB)  

    DC testing of analog circuits is inexpensive compared to AC testing and provides high coverage of many fault classes including some that are not detected by AC tests. It is also particularly effective in detecting catastrophic failures such as line opens and shorts. In this paper, we present an efficient low-cost built-in self-test (BIST) methodology for linear analog circuits that is targeted tow... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cubical CAMP for minimization of Boolean functions

    Publication Year: 1996 , Page(s): 264 - 269
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (504 KB)  

    The paper presents QCAMP, a cube-based algorithm for minimization of single Boolean functions. The algorithm does not generate all the prime cubes, nor does it require the Off-set of the function. Two significant contributions of QCAMP are the UNATE TEST which tests if a given function is a unate function, and the BISECT procedure which minimizes a cyclic function without taking recourse to branch... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Geometric bipartitioning problem and its applications to VLSI

    Publication Year: 1996 , Page(s): 400 - 405
    Cited by:  Papers (1)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB)  

    We identify a new problem called geometric bipartitioning that is useful in VLSI layout design. Given a floorplan with rectilinear modules, the problem is to partition the floor by a staircase (monotone increasing) channel from one corner of the floor to its diagonally opposite corner, such that the numbers of modules in the two halves become equal. As the partition is heavily dependent on the geo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power video encoder with power, memory and bandwidth scalability

    Publication Year: 1996 , Page(s): 358 - 363
    Cited by:  Papers (7)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (596 KB)  

    This paper presents a low power video encoder with power, memory and bandwidth scalability for use in portable video applications. The encoder uses generic block transform based vector quantizer encoders implemented by table lookups. In these table lookup encoders, input vectors to the encoders are used directly as addresses in code tables to choose the codewords. There is no need to perform the f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Elimination of dynamic hazards from signal transition graphs

    Publication Year: 1996 , Page(s): 382 - 388
    Request Permissions | Click to expandAbstract | PDF file iconPDF (696 KB)  

    In this paper we present a novel method to eliminate logic hazards, in particular dynamic hazards, in asynchronous circuits synthesized from the signal transition graph (STG) specifications. The existing hazard removal techniques work with the logic implementation derived from the STG specifications. This paper describes algorithms to detect and eliminate dynamic hazards without implementing the l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An enhanced macromodel for a CMOS operational amplifier for HDL implementation

    Publication Year: 1996 , Page(s): 331 - 332
    Request Permissions | Click to expandAbstract | PDF file iconPDF (196 KB)  

    In this paper, an enhanced macromodel for an operational amplifier is presented which takes into account the second order effects such as the gain-nonlinearity, the noise, the d.c. power-supply rejection and the slew-rate limitations. Implementation of the macromodel in one of the commercial HDLAs, and its comparison with a device level simulation illustrates the accuracy of the macromodel View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Maximum power estimation for CMOS circuits using deterministic and statistic approaches

    Publication Year: 1996 , Page(s): 364 - 369
    Cited by:  Papers (16)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (628 KB)  

    Excessive instantaneous power consumption in VLSI circuits may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is essential to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent input-pattern dependence of the problem, it is intractable to conduct an exhaustive search for circuits with... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A VLSI architecture for cellular automata based parallel data compression

    Publication Year: 1996 , Page(s): 270 - 275
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (556 KB)  

    Analytical study of three neighbourhood two state per cell Cellular Automata (CA) behaviour is a comparatively recent phenomenon. A wide variety of applications have been developed utilizing the elegant structure of group CA. In this paper some of the characterizations of the state transition behaviour of non-group CA are reported. These results are subsequently utilized to develop an efficient pa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A rule-based approach for improving allocation of filter structures in HLS

    Publication Year: 1996 , Page(s): 133 - 139
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB)  

    A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designer... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of testable pipelined datapaths using genetic search

    Publication Year: 1996 , Page(s): 205 - 210
    Cited by:  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.