Proceedings of 9th International Conference on VLSI Design

3-6 Jan. 1996

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Displaying Results 1 - 25 of 96
  • 1995 IEEE Fellowship Awards

    Publication Year: 1996
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  • 1995 Awards

    Publication Year: 1996
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996
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    Freely Available from IEEE
  • A low power video encoder with power, memory and bandwidth scalability

    Publication Year: 1996, Page(s):358 - 363
    Cited by:  Papers (7)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    This paper presents a low power video encoder with power, memory and bandwidth scalability for use in portable video applications. The encoder uses generic block transform based vector quantizer encoders implemented by table lookups. In these table lookup encoders, input vectors to the encoders are used directly as addresses in code tables to choose the codewords. There is no need to perform the f... View full abstract»

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  • A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications

    Publication Year: 1996, Page(s):69 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    In this paper, an efficient algorithm for concurrent computation of two real multiplications and/or two real additions usually required for high-throughput image and video coding applications is described. The proposed algorithm is mapped onto a novel concurrent dual multiplier-dual adder cell based on carry-save 4:2 compressors. A detailed performance analysis of the the proposed cell shows reduc... View full abstract»

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  • Ultra low power digital signal processing

    Publication Year: 1996, Page(s):352 - 357
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The explosive growth of portable wireless devices has elevated power consumption to be one of the most critical design parameters. This paper presents several techniques to implement DSP functions with the lowest possible power consumption. Since power is consumed only when capacitance is being switched, power can be reduced by minimizing this capacitance through operation reduction, choice of dat... View full abstract»

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  • Fast algorithms for computing IDDQ tests for combinational circuits

    Publication Year: 1996, Page(s):103 - 106
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A system to generate IDDQ tests for bridging faults (BFs) and leakage faults in combinational CMOS circuits is described. Experimental results for different sets of BPs demonstrates the efficiency and flexibility of the approach View full abstract»

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  • Statistical path delay fault coverage estimation for synchronous sequential circuits

    Publication Year: 1996, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    We present the first technique to statistically estimate path delay-fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multi-valued algebra and accumulate signal statistics, which we use to calculate path delay-fault coverage. The detectability of a path delay-fault is the product of observabilities from primary or pseudo-primary outputs to primary or pseu... View full abstract»

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  • A rule-based approach for improving allocation of filter structures in HLS

    Publication Year: 1996, Page(s):133 - 139
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designer... View full abstract»

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  • Hierarchical probabilistic diagnosis of MCMs on large-area substrates

    Publication Year: 1996, Page(s):65 - 68
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper addresses the issue of testing MCMs fabricated on large-area substrates. The cost of testing MCMs may be as high as 40% of the manufacturing cost. In order to reduce test costs, at is essential that the testing be parallelized taking advantage of the fact that all the MCMs on the large-area substrate are similar. In this paper we propose a hierarchical probabilistic test algorithm for M... View full abstract»

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  • CoDe-X: a novel two-level hardware/software co-design framework

    Publication Year: 1996, Page(s):81 - 84
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    A novel hardware/software co-design framework (CoDe-X) is presented, where an Xputer is used as universal accelerator based on a reconfigurable datapath hardware. CoDe-X accepts C-programs and carries out both, the profiling-driven host/accelerator partitioning for performance optimization, and (second level) the resource-driven sequential/structural partitioning of the accelerator source code to ... View full abstract»

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  • Wiresizing with buffer placement and sizing for power-delay tradeoffs

    Publication Year: 1996, Page(s):346 - 351
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    With the increasing influence of the resistive effects of interconnects on the performance of VLSI systems, a greater stress is being laid on careful interconnect design. One prominent technique is the approach of sizing wires for long interconnects to achieve the desired speed and power characteristics. It has also been suggested that one may appropriately insert repeaters for significant delay r... View full abstract»

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  • Synchronous controller models for synthesis from communicating VHDL processes

    Publication Year: 1996, Page(s):198 - 204
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes. These constructs lead to concise behavioral specifications but make controller generation in high level synthesis difficult. Current work on synthesis from VHDL restricts the behavioral subset, excluding or limi... View full abstract»

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  • A very high gain bandwidth product fully differential amplifier

    Publication Year: 1996, Page(s):99 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    This paper deals with a novel DC-coupled, large bandwidth, fully differential amplifier dedicated to industrial applications. A family of integrated fully differential amplifiers has been developed in a 1.2 μm, 6 GHz fT, BiCMOS technology. The stability/gain compromise is improved thanks to on-chip feedback resistors, whereas the gain is doubled by means of connecting directly on chi... View full abstract»

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  • A systolic architecture for LMS adaptive filtering with minimal adaptation delay

    Publication Year: 1996, Page(s):286 - 289
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Existing systolic architectures for the LMS algorithm with delayed coefficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of... View full abstract»

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  • Dynamic test sequence compaction for sequential circuits

    Publication Year: 1996, Page(s):170 - 173
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    This work addresses two important issues in dynamic test sequence compaction for sequential circuits: (1) extension of partially specified test sequence to detect other faults, and (2) reduction in the number of secondary faults that have to be considered while extending partially specified test sequence. We present a sliding anchor frame technique to specify unspecified signal in a test sequence.... View full abstract»

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  • Automatic synthesis of speed-independent circuits from signal transition graph specifications

    Publication Year: 1996, Page(s):389 - 392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    We propose a verification method of the complete state coding property for signal transition graph specifications with single cycle signals. We also propose an optimized logic synthesis method for generating speed-independent circuits without the state graph representation. We use a circuit model for each non-input signal, which consists of a C-element and AND-gates. The resulting circuit is optim... View full abstract»

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  • A hierarchical register optimization algorithm for behavioral synthesis

    Publication Year: 1996, Page(s):126 - 132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    In this work, we address the problem of register optimization that arises during high-level synthesis from hierarchical behavioral specifications containing a hierarchy of modules such as procedures, functions etc. Register optimization (or register sharing) is the process of grouping carriers in the specification such that each group can be safely assigned to a hardware register. Global register ... View full abstract»

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  • Parallel concurrent path-delay fault simulation using single-input change patterns

    Publication Year: 1996, Page(s):426 - 431
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    We present a new simulation-based method using single-input change (SIC) patterns to efficiently derive tests for singly-testable (ST) path-delay faults (PDFs). We assign random values to all inputs, and then propagate rising and falling transitions from each input while all other inputs are held steady. We present a sixteen-valued algebra with which rising and falling PDFs from all inputs are con... View full abstract»

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  • A multilevel factorization technique for pass transistor logic

    Publication Year: 1996, Page(s):339 - 340
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    Pass transistor logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks View full abstract»

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  • A multiplier generator for Xilinx FPGAs

    Publication Year: 1996, Page(s):322 - 323
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    In this paper, we present a module generator which can produce variety of multiplier designs for LUT based FPGAs. It incorporates algorithms for generating sequential, combinational and pipelined designs. The multiplier generator forms a part of the IDEAS synthesis system. Different types of multipliers which can be generated have been included in the IDEAS component library, along with functions ... View full abstract»

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  • Programmable cellular automata based testbed for fault diagnosis in VLSI circuits

    Publication Year: 1996, Page(s):61 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    This paper analyses the fault diagnosis capability of Programmable CA based signature analyzer. Polynomial algebraic tools have been developed for selection of a group CA of appropriate size for generation of faulty signatures due to faults in different partitions of a circuit. Further, a special class of CA termed as multiple attractor CA has been utilized for classification of faulty signatures ... View full abstract»

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  • Instruction-set modelling for ASIP code generation

    Publication Year: 1996, Page(s):77 - 80
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A main objective in code generation for ASIPs is to develop retargetable compilers in order to permit exploration of different architectural alternatives within short turnaround time. Retargetability requires that the compiler is supplied with a formal description of the target processor. This description is usually transformed into an internal instruction set model, on which the actual code gener... View full abstract»

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  • VLSI in mobile communications

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    In recent years, the demand for mobile operation of all types of electronic systems has become significant. It seems that by merely providing the same functionality of a desktop system in a mobile unit, a significant market advantage can be obtained for virtually any electronic function. Consumer electronics companies have been highly successful by creating portable televisions, video tape recorde... View full abstract»

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  • Is compiled simulation really faster than interpreted simulation?

    Publication Year: 1996, Page(s):303 - 306
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    It is commonly assumed that compiled simulation will provide significant performance improvements over interpreted event-driven simulation. This paper demonstrates that for a new algorithm called the Inversion Algorithm that this assumption is not true. The Inversion Algorithm can be run in either compiled or interpreted mode with only a slight difference in performance. Experimental data confirms... View full abstract»

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