[1991] Proceedings. First Great Lakes Symposium on VLSI

1-2 March 1991

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Displaying Results 1 - 25 of 65
  • Design and evaluation of fault tolerance techniques for highly parallel architectures

    Publication Year: 1991
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Summary form only given. The author discusses fault tolerance techniques for computer systems, including a new technique, which he calls algorithm-based fault tolerance, for error detection and correction when computations are performed using multiple processor systems. The technique uses knowledge about the algorithm to reduce the amount of overhead necessary for fault tolerance. This is done by ... View full abstract»

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  • Proceedings. First Great Lakes Symposium on VLSI (Cat. No.91TH0364-0)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (59 KB)
    Freely Available from IEEE
  • HADES-high-level architecture development and exploration system

    Publication Year: 1991, Page(s):342 - 343
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. ... View full abstract»

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  • A parallel algorithm for logic simulation on transputer networks

    Publication Year: 1991, Page(s):249 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with com... View full abstract»

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  • A poly to active region VLSI mask alignment test structure

    Publication Year: 1991, Page(s):278 - 283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Present day CMOS technologies require continuous evaluation of the technology in terms of optimizing the design rules. Electrical monitoring of mask alignment is one such evaluation tool. A VLSI test structure for monitoring the poly to active region mask misalignment is presented. The structure is designed based on 2-micron scalable CMOS (SCMOS) design rules. The issues related to sensitivity of ... View full abstract»

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  • Applying Hopfield network to find the minimum cost coverage of a Boolean function

    Publication Year: 1991, Page(s):182 - 185
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    To find a minimal expression of a Boolean function includes a step to select the minimum cost cover from a set of implicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical for large input data size. In this paper, the author tries to apply neural network approach to solve this problem. He first formulates this problem and then defines an `energy ... View full abstract»

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  • GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

    Publication Year: 1991, Page(s):296 - 300
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into l... View full abstract»

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  • Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

    Publication Year: 1991, Page(s):340 - 341
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented View full abstract»

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  • Test plan generation and concurrent scheduling of tests in the presence of conflicts

    Publication Year: 1991, Page(s):243 - 248
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    When BILBO tests are being generated and scheduled, resource conflicts between I-paths and tests present many difficulties. The authors explore: how pipelining is limited by potential internal conflicts; ways to promote pipelining during test plan generation and how to incorporate a test into a test phase already containing tests that conflict with it. They do not directly address the general prob... View full abstract»

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  • Novel digital VLSI GaAs FET circuits for low power and high functional yield

    Publication Year: 1991, Page(s):272 - 275
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    The complexity of GaAs FET VLSI circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, novel digital GaAs FET circuits are presented that eliminate the DC power dissipation, reduce the area to 50% of that of the conventional static circuit and its larger tolerance to device parameters variations, results in ... View full abstract»

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  • A test controller board for TSS

    Publication Year: 1991, Page(s):38 - 42
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    The design of a test controller board for a test support system is presented in this paper. Driven by the SCANTEST software, the test controller board exercises the boundary-scan and scan-path and built-in-self-test hardware implemented on the device under test via a dedicated test-bus. An analog test feature is also described View full abstract»

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  • Evaluation of silicon-on-sapphire enhancement JFETs for digital applications

    Publication Year: 1991, Page(s):334 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A ni... View full abstract»

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  • Dense layouts for series-parallel circuits

    Publication Year: 1991, Page(s):14 - 17
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    The authors address the question `when do three tracks suffice for the gate matrix layout of series-parallel circuits?' and demonstrate that the rather surprising answer appears to be `almost always.' This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis ch... View full abstract»

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  • CMOS output buffer waveshaping

    Publication Year: 1991, Page(s):326 - 327
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The authors report a novel design technique to reduce output switching noise in CMOS VLSI circuits. The technique is based on analysis of the RLC equivalent circuit of the output driver stage. SPICE simulations verify the method's effectiveness and a test circuit is being submitted to MOSIS for fabrication View full abstract»

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  • An architecture design using VLSI building blocks for dynamic programming neural networks

    Publication Year: 1991, Page(s):176 - 181
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An architecture for dynamic programming neural networks is presented. The architecture is based on a building block paradigm in which the network is constructed from neuron array and weight assignment chips. Because of its simple and regular structure, the architecture is a feasible implementation for dynamic programming neural networks with current VLSI technology. Moreover, this architecture can... View full abstract»

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  • Gate matrix layout based on hierarchical net-list representations

    Publication Year: 1991, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The authors propose a hierarchical gate matrix layout algorithm based on a new net-list. It has remarkable features such that logical equivalence is considered, and the drawback of the greedy method can be overcome by using special features of multiterminal nets. Experimental results for CMOS circuits are far superior to those obtained by another published method View full abstract»

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  • Design of fail-safe CMOS logic circuits

    Publication Year: 1991, Page(s):338 - 339
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    Design techniques to make CMOS logic circuits fail-safe are reported. The set of transistor stuck-on and stuck-open faults, signal lines stuck-at faults, and bridging faults is partitioned into two classes of faults. Fail-safe property is maintained for multiple faults within a class. Limited fault tolerance capability is introduced as a by-product View full abstract»

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  • Testability profile estimation of VLSI circuits from fault coverage

    Publication Year: 1991, Page(s):238 - 242
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors present a new method of estimating the testability profile of a circuit from its random fault coverage data. They have recently developed a relationship between fault coverage and testability profile. However, their testability profile estimates were based on unknown distribution of input vectors and used Bayes theorem with a priori uniform detection probability distribution. The testa... View full abstract»

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  • An experimental environment for design and analysis of global routing heuristics

    Publication Year: 1991, Page(s):225 - 230
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The authors discuss the development and implementation of an object-oriented experimental environment for global routing heuristics in VLSI layout design. This experimental environment has been implemented in both common lisp (with object-oriented extensions) and Smalltalk, providing a user-friendly graphical interface for problem input, output, interaction and modification of the heuristics. Seve... View full abstract»

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  • A new approach to timing driven partitioning of combinational logic

    Publication Year: 1991, Page(s):96 - 101
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The authors present a new approach to timing driven partitioning of combinational logic. Instead of accessing a predefined library, complex gates based on the line-of-diffusion layout style are automatically synthesized. A new timing model for complex gates is presented which permits a fast pattern independent timing analysis with a deviation of less than 10% and two to three orders of magnitude f... View full abstract»

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  • Uni-directional cube-connected cycles

    Publication Year: 1991, Page(s):266 - 271
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Cube connected cycles (CCC), a popular and layout/efficient alternative to hypercube, can emulate the performance of hypercube for many parallel algorithms. Recently, interconnection networks based on simplex links rather than duplex have been proposed. The uni-directional architectures have layout advantages and reduces complexity of each processing element (PE). The authors propose directed cube... View full abstract»

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  • I/O bound binary tree layout

    Publication Year: 1991, Page(s):31 - 36
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The authors propose a VLSI layout strategy for a full binary tree. This layout can support more border leaf processing elements (PEs) and thus can give a higher I-O bandwidth. It is superior to the H-tree layout in terms of the number of boundary leaves. The approach uses H-tree pattern for constructing subtree layouts and then combines a number of such subtrees following standard tree style to ge... View full abstract»

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  • `NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators

    Publication Year: 1991, Page(s):332 - 333
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    The authors have developed a computer simulator called `NCHIPSIM' which can be used to simulate with a microcomputer the performance indicators of an integrated circuit microprocessor chip based on silicon NMOS technology. In addition to predicting the various chip performance indicators such as its size, power consumption, maximum clock frequency, computational capacity, functional throughput and... View full abstract»

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  • Sequence invariant state machine compiler

    Publication Year: 1991, Page(s):318 - 323
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A CAD tool for automatic generation of VLSI state machines based on a sequence invariant architecture is presented. The program, which is process independent, operates on a flow table input and produces a layout archive. Using an incremental approach for layout also allows subcircuits to be generated View full abstract»

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  • A low power CMOS correlator

    Publication Year: 1991, Page(s):122 - 127
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A full custom, 25 MHz, 1.6 μm CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable. The correlator was designed to Mil Spec, 3σ Worst Case Speed parameters View full abstract»

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