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VLSI, 1991. Proceedings., First Great Lakes Symposium on

Date 1-2 March 1991

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Displaying Results 1 - 25 of 65
  • Proceedings. First Great Lakes Symposium on VLSI (Cat. No.91TH0364-0)

    Publication Year: 1991
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    Freely Available from IEEE
  • Schematic driven layout for the custom VLSI design environment

    Publication Year: 1991, Page(s):302 - 306
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The tool needs of the custom VLSI layout environment are being virtually ignored by the CAD tool community. A set of simple, schematic driven layout tools, specified to assist a human layout designer in the custom VLSI environment, is proposed in this paper. These tools include: a smart tiler; interactive channel router; and random logic layout synthesis View full abstract»

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  • GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

    Publication Year: 1991, Page(s):296 - 300
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into l... View full abstract»

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  • Implementation of fault-tolerant sequential circuits using programmable logic arrays

    Publication Year: 1991, Page(s):128 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area... View full abstract»

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  • Algorithm independent data flow mapping on a unified VLSI architecture

    Publication Year: 1991, Page(s):68 - 73
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    VLSI architectural unification at primitive hardware and interconnect structure level, is necessary, to cover the methodology of GPVLSI and SPVLSI systems synthesis. The concept of PACUBE array (Programmable Array of Array Adders) leads to this grand unification at macrocell level. The systolic and wavefront arrays have led to a major breakthrough in the design of supercomputing architectures. But... View full abstract»

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  • Gate matrix layout based on hierarchical net-list representations

    Publication Year: 1991, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The authors propose a hierarchical gate matrix layout algorithm based on a new net-list. It has remarkable features such that logical equivalence is considered, and the drawback of the greedy method can be overcome by using special features of multiterminal nets. Experimental results for CMOS circuits are far superior to those obtained by another published method View full abstract»

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  • A low power CMOS correlator

    Publication Year: 1991, Page(s):122 - 127
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A full custom, 25 MHz, 1.6 μm CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable. The correlator was designed to Mil Spec, 3σ Worst Case Speed parameters View full abstract»

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  • On the complexity of a fault-tolerance model for multicomputer systems

    Publication Year: 1991, Page(s):62 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In topological design of multicomputer systems (e.g., the hypercube), the edge- and vertex-connectivities have traditionally been used as deterministic measures of fault-tolerance. These measures have been noted to have some deficiencies and as a result several generalizations of graph connectivity have been proposed. In this paper, the authors examine some instances of the connectivity generaliza... View full abstract»

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  • Uni-directional cube-connected cycles

    Publication Year: 1991, Page(s):266 - 271
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Cube connected cycles (CCC), a popular and layout/efficient alternative to hypercube, can emulate the performance of hypercube for many parallel algorithms. Recently, interconnection networks based on simplex links rather than duplex have been proposed. The uni-directional architectures have layout advantages and reduces complexity of each processing element (PE). The authors propose directed cube... View full abstract»

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  • An approach for multilevel logic cell optimization in module generators

    Publication Year: 1991, Page(s):284 - 289
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actua... View full abstract»

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  • Applying Hopfield network to find the minimum cost coverage of a Boolean function

    Publication Year: 1991, Page(s):182 - 185
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    To find a minimal expression of a Boolean function includes a step to select the minimum cost cover from a set of implicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical for large input data size. In this paper, the author tries to apply neural network approach to solve this problem. He first formulates this problem and then defines an `energy ... View full abstract»

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  • HADES-high-level architecture development and exploration system

    Publication Year: 1991, Page(s):342 - 343
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. ... View full abstract»

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  • Designing VLSI systolic arrays with complex processing elements

    Publication Year: 1991, Page(s):207 - 212
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing elemen... View full abstract»

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  • An algebraic approach to test generation for sequential circuits

    Publication Year: 1991, Page(s):115 - 120
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors describe an algebraic algorithm for automatic test pattern generation for sequential circuits. Three innovative concepts have been introduced in order to reduce the computational time required for pattern generation. These are: firstly, circuit partitioning in fanout-free regions; then, computation of observability and excitability functions for state propagation and justification; and... View full abstract»

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  • A hierarchical multi-level test generation system

    Publication Year: 1991, Page(s):54 - 59
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The authors describe a multi-level ATPG system which handles circuits consisting of `switch' transistors, Boolean gates, and open-output gates (i.e., tristate, open-collector, open-emitter). Both combinational and synchronous sequential circuits are supported, with provision for full-scan, partial-scan, and non-scan design. The most remarkable features of the system are an unified approach to test... View full abstract»

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  • Four layer wiring using adjacent-layer vias

    Publication Year: 1991, Page(s):163 - 168
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    An algorithm is presented which, given a two-dimensional wire layout in knock-knee mode, produces a legal wiring (layer-assignment) using only adjacent-layer vias and at most four layers. The previous four-layer wiring algorithm requires technologically impractical vias between non-adjacent layers. This algorithm has important implications for practical automatic wire routing, since many knock-kne... View full abstract»

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  • Discrete Fourier transform processors using CORDIC

    Publication Year: 1991, Page(s):260 - 265
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    The author presents an analysis of the cost-effectiveness of discrete Fourier transform processors, based on CORDIC modules such as the bit-serial, parallel with non-redundant and redundant arithmetic, and pipelined. The performance of each processor is analyzed with respect to the time to process one frequency output and the number of modules required. It is shown that the CORDIC-based DFT proces... View full abstract»

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  • Transforming disfigured and disoriented areas into routable switchboxes

    Publication Year: 1991, Page(s):82 - 87
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Routing an entire VLSI circuit requires partitioning the circuit (routing area) into smaller, localized routing areas. Using non-rectangular, rotated switchbox shapes (and therefore non-Manhattan routing layout) has the potential to simplify the partitioning of the circuit into routable areas and to use `dead space' on a chip for routing. The method described in this paper for generating non-recta... View full abstract»

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  • A poly to active region VLSI mask alignment test structure

    Publication Year: 1991, Page(s):278 - 283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Present day CMOS technologies require continuous evaluation of the technology in terms of optimizing the design rules. Electrical monitoring of mask alignment is one such evaluation tool. A VLSI test structure for monitoring the poly to active region mask misalignment is presented. The structure is designed based on 2-micron scalable CMOS (SCMOS) design rules. The issues related to sensitivity of ... View full abstract»

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  • An architecture design using VLSI building blocks for dynamic programming neural networks

    Publication Year: 1991, Page(s):176 - 181
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An architecture for dynamic programming neural networks is presented. The architecture is based on a building block paradigm in which the network is constructed from neuron array and weight assignment chips. Because of its simple and regular structure, the architecture is a feasible implementation for dynamic programming neural networks with current VLSI technology. Moreover, this architecture can... View full abstract»

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  • An efficient tabu search algorithm for graph bisectioning

    Publication Year: 1991, Page(s):92 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A new algorithm for solving the graph bisectioning problem based on tabu search is proposed. The authors run the tabu search algorithm and the Kernighan-Lin algorithm on the same set of random graphs with 50 to 500 nodes and compare their performances. They demonstrate that for all of the graphs their tabu search algorithm provides lower bisection cost than the Kernighan-Lin algorithm; and for all... View full abstract»

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  • Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

    Publication Year: 1991, Page(s):340 - 341
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented View full abstract»

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  • Study of quaternary logic versus binary logic

    Publication Year: 1991, Page(s):336 - 337
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    The authors deal with the comparison of quaternary and binary logic with reference to entropy, speed of data transmission and data string length QUATLOG, computer simulator developed, demonstrates the relative advantages of employing quaternary logic for data transmission View full abstract»

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  • `NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators

    Publication Year: 1991, Page(s):332 - 333
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    The authors have developed a computer simulator called `NCHIPSIM' which can be used to simulate with a microcomputer the performance indicators of an integrated circuit microprocessor chip based on silicon NMOS technology. In addition to predicting the various chip performance indicators such as its size, power consumption, maximum clock frequency, computational capacity, functional throughput and... View full abstract»

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  • Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors

    Publication Year: 1991, Page(s):328 - 329
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The authors have developed a computer-efficient algorithm and the related CAD oriented software to calculate the transverse propagation delay in a MODFET. The model has been used to study the dependence of these delays on the various MODFET parameters. The results can be utilized for the optimization of high-speed circuits View full abstract»

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