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[1991] Proceedings. First Great Lakes Symposium on VLSI

1-2 March 1991

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Displaying Results 1 - 25 of 65
  • Design and evaluation of fault tolerance techniques for highly parallel architectures

    Publication Year: 1991
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Summary form only given. The author discusses fault tolerance techniques for computer systems, including a new technique, which he calls algorithm-based fault tolerance, for error detection and correction when computations are performed using multiple processor systems. The technique uses knowledge about the algorithm to reduce the amount of overhead necessary for fault tolerance. This is done by ... View full abstract»

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  • Proceedings. First Great Lakes Symposium on VLSI (Cat. No.91TH0364-0)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (59 KB)
    Freely Available from IEEE
  • High frequency analog circuit design using QuickChip

    Publication Year: 1991, Page(s):196 - 201
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The author describes analog circuit design methodologies and techniques required to optimize high frequency performance when operating near the upper frequency limit of BJT-based analog ASICs. The Tektronix QuickChip 2S ASIC array is used as the analysis and test vehicle. These techniques are illustrated using a series of examples including an actively shunt-peaked wideband amplifier and a multi-c... View full abstract»

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  • Transition count testing of CMOS combinational circuits

    Publication Year: 1991, Page(s):110 - 114
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An optimal, robust transition count test generation for testing stuck-open faults in CMOS combinational circuits is presented in this paper. Procedures to optimize conventional stuck-open fault test sets have been developed. The use of fault folding graphs as a tool, to generate optimal test sequences, has been illustrated. Both non-reconvergent and reconvergent, irredundant, circuits are treated, View full abstract»

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  • Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors

    Publication Year: 1991, Page(s):328 - 329
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The authors have developed a computer-efficient algorithm and the related CAD oriented software to calculate the transverse propagation delay in a MODFET. The model has been used to study the dependence of these delays on the various MODFET parameters. The results can be utilized for the optimization of high-speed circuits View full abstract»

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  • Two-dimensional multirate systolic array design for artificial neural networks

    Publication Year: 1991, Page(s):186 - 193
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper a novel design of neural networks using 2-dimensional systolic array is proposed. Two techniques are applied in the design, namely, 2-dimensional pipelining and multirate processing (2 level clocking). 2-dimensional pipelining operation gives significant improvement in computation time compared to the currently known 1D and 2D systolic implementation schemes. Besides, multirate clock... View full abstract»

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  • Optimal test set for stuck-at faults in VLSI

    Publication Year: 1991, Page(s):104 - 109
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the ... View full abstract»

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  • CMOS output buffer waveshaping

    Publication Year: 1991, Page(s):326 - 327
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The authors report a novel design technique to reduce output switching noise in CMOS VLSI circuits. The technique is based on analysis of the RLC equivalent circuit of the output driver stage. SPICE simulations verify the method's effectiveness and a test circuit is being submitted to MOSIS for fabrication View full abstract»

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  • Applying Hopfield network to find the minimum cost coverage of a Boolean function

    Publication Year: 1991, Page(s):182 - 185
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    To find a minimal expression of a Boolean function includes a step to select the minimum cost cover from a set of implicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical for large input data size. In this paper, the author tries to apply neural network approach to solve this problem. He first formulates this problem and then defines an `energy ... View full abstract»

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  • A new approach to timing driven partitioning of combinational logic

    Publication Year: 1991, Page(s):96 - 101
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The authors present a new approach to timing driven partitioning of combinational logic. Instead of accessing a predefined library, complex gates based on the line-of-diffusion layout style are automatically synthesized. A new timing model for complex gates is presented which permits a fast pattern independent timing analysis with a deviation of less than 10% and two to three orders of magnitude f... View full abstract»

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  • Testability profile estimation of VLSI circuits from fault coverage

    Publication Year: 1991, Page(s):238 - 242
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors present a new method of estimating the testability profile of a circuit from its random fault coverage data. They have recently developed a relationship between fault coverage and testability profile. However, their testability profile estimates were based on unknown distribution of input vectors and used Bayes theorem with a priori uniform detection probability distribution. The testa... View full abstract»

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  • Sequence invariant state machine compiler

    Publication Year: 1991, Page(s):318 - 323
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A CAD tool for automatic generation of VLSI state machines based on a sequence invariant architecture is presented. The program, which is process independent, operates on a flow table input and produces a layout archive. Using an incremental approach for layout also allows subcircuits to be generated View full abstract»

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  • An architecture design using VLSI building blocks for dynamic programming neural networks

    Publication Year: 1991, Page(s):176 - 181
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An architecture for dynamic programming neural networks is presented. The architecture is based on a building block paradigm in which the network is constructed from neuron array and weight assignment chips. Because of its simple and regular structure, the architecture is a feasible implementation for dynamic programming neural networks with current VLSI technology. Moreover, this architecture can... View full abstract»

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  • A massively parallel and versatile architecture for computer vision

    Publication Year: 1991, Page(s):74 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A massively parallel architecture for vision that can be efficiently implemented as a dense and regular VLSI circuit is proposed. It consists of locally connected array of simple processors possessing certain capabilities, making it possible to form a complete vision system for binary images, that can operate in real time. For low level processing both a systolic implementation on a 2D array, as w... View full abstract»

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  • A VLSI implementation of a state variable filter algorithm

    Publication Year: 1991, Page(s):138 - 143
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The authors present a digital signal processor (DSP) architecture whose powerful CPU is optimized to solve a state variable filter algorithm, but is not limited to that application. State variable filters perform low pass filtering and generate the derivatives of the filtered signal. These signals are used in systems for real-time process identification. In order to minimize the number of componen... View full abstract»

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  • The 60° grid : routing channels in width d/√3

    Publication Year: 1991, Page(s):214 - 219
    Cited by:  Papers (2)  |  Patents (106)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    The 60° grid consists of vertical columns and diagonal tracks running at slopes of ±30°. This model offers a potentially large reduction in channel width, without resorting to wire overlap. For a channel routing problem with density d, the availability of the diagonal tracks leads to a lower bound of d/√3. The authors present two near-optimal channel routing algorithm... View full abstract»

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  • Evaluation of silicon-on-sapphire enhancement JFETs for digital applications

    Publication Year: 1991, Page(s):334 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A ni... View full abstract»

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  • Proving finite state machines correct with an automaton-based method

    Publication Year: 1991, Page(s):255 - 258
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The authors present a method to prove equivalence of a pair of FSMs, described at the gate level with D-type flip-flops and a reset signal available to bring them into the all-zero initial state. This method restricts investigation to that minimum subset of states that can be reached from the reset condition and are necessary to reach the goal. The equivalence condition is expressed in theoretical... View full abstract»

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  • An efficient tabu search algorithm for graph bisectioning

    Publication Year: 1991, Page(s):92 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A new algorithm for solving the graph bisectioning problem based on tabu search is proposed. The authors run the tabu search algorithm and the Kernighan-Lin algorithm on the same set of random graphs with 50 to 500 nodes and compare their performances. They demonstrate that for all of the graphs their tabu search algorithm provides lower bisection cost than the Kernighan-Lin algorithm; and for all... View full abstract»

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  • Building block layout based on block compaction and two-adjacent-side channel router

    Publication Year: 1991, Page(s):231 - 236
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors propose a new layout method based on a block compaction and two-adjacent-side channel router for building block VLSI. In this method, the block compaction and global routing are carried out simultaneously and by introducing a new channel router it is possible to avoid unnecessary detour of the wires and reduce the dead space. The present channel routing approach has a remarkable featur... View full abstract»

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  • Genetic synthesis: performance-driven logic synthesis using genetic evolution

    Publication Year: 1991, Page(s):312 - 317
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The authors present a system for constraint-directed synthesis of logic circuits. The heart of the system is a genetic synthesis algorithm capable of searching the design space in the presence of user-specified constraints on performance attributes such as the area, critical path length, number of gates, wires and any other attribute which can be procedurally described. Three experimental results ... View full abstract»

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  • GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

    Publication Year: 1991, Page(s):296 - 300
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into l... View full abstract»

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  • A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons

    Publication Year: 1991, Page(s):170 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The authors describe a VLSI peripheral system designed for the analog recording of electric signals from a network of living neurons growing on a glass plate containing 64 microelectrodes. The chip also provides for stimulating the neurons with up to four externally generated signals that can be routed to any of the microelectrodes View full abstract»

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  • Algorithm independent data flow mapping on a unified VLSI architecture

    Publication Year: 1991, Page(s):68 - 73
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    VLSI architectural unification at primitive hardware and interconnect structure level, is necessary, to cover the methodology of GPVLSI and SPVLSI systems synthesis. The concept of PACUBE array (Programmable Array of Array Adders) leads to this grand unification at macrocell level. The systolic and wavefront arrays have led to a major breakthrough in the design of supercomputing architectures. But... View full abstract»

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  • A CAD tool for designing large, fault-tolerant VLSI arrays

    Publication Year: 1991, Page(s):132 - 137
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded... View full abstract»

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