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Test Symposium, 1995., Proceedings of the Fourth Asian

Date 23-24 Nov. 1995

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Displaying Results 1 - 25 of 59
  • Fanout fault analysis for digital logic circuits

    Publication Year: 1995, Page(s):33 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB)

    Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Im... View full abstract»

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  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • Fast fault simulation for BIST applications

    Publication Year: 1995, Page(s):93 - 99
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propa... View full abstract»

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  • Serial transistor network modeling for bridging fault simulation

    Publication Year: 1995, Page(s):100 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor netw... View full abstract»

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  • Sequential logic path delay test generation by symbolic analysis

    Publication Year: 1995, Page(s):353 - 359
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Many test generation algorithms for path delay faults assume a special methodology for application of the test sequence. The two-vector test sequences are valid under the assumption that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such vectors may be acceptable for combinational circuits, their use for testing a non-scan sequ... View full abstract»

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  • Deterministic test generation for non-classical faults on the gate level

    Publication Year: 1995, Page(s):244 - 251
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pat... View full abstract»

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  • Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing

    Publication Year: 1995, Page(s):107 - 111
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficient. In comparison to two different dataflow computation schemes and their hardware-accelerated implement... View full abstract»

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  • A parallel sequential test generation system DESCARTES based on real-valued logic simulation

    Publication Year: 1995, Page(s):252 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '... View full abstract»

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  • Unified scan design with scannable memory arrays

    Publication Year: 1995, Page(s):153 - 159
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can g... View full abstract»

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  • Fast computation of C-MISR signatures

    Publication Year: 1995, Page(s):293 - 297
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Cellular automata based signature analyzers are becoming very popular for compressing test responses in built-in self-test applications. Off-line determination of signatures (both good circuit signature and faulty circuit signatures) is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we investigate a technique for speeding up the simula... View full abstract»

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  • Module level weighted random patterns

    Publication Year: 1995, Page(s):274 - 278
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signatur... View full abstract»

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  • Software transformations for sequential test generation

    Publication Year: 1995, Page(s):266 - 272
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    This paper presents software (model) transformations that can be used to effectively generate high fault coverage test sets. Unlike synthesis or design for testability methods which involve hardware modifications, this approach does not modify the hardware design. Instead, it transforms a software model of the design into a new software model that has desirable testability properties. A sequential... View full abstract»

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  • An SBus Multi Tracer and its applications

    Publication Year: 1995, Page(s):9 - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    An SBus Multi Tracer (MT) is described, which is based on our previously developed SBus monitoring board (SMB), which can provide timing diagrams for all SBus signals. However, just like any other logic analyzer or a bus analyzer its trace length is limited by the board memory and it is difficult to cope with multi occurrences of trigger patterns in a single application. An effective answer to thi... View full abstract»

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  • A new method for testing mixed analog and digital circuits

    Publication Year: 1995, Page(s):127 - 132
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper a new method is proposed for observing analog test points inside integrated circuits that enables the simultaneous observation of a large number of points. The method permits the removal of the analog multiplexer from the signal path and a reduction of the load introduced at the observed test points. A charge coupled device analog shift register is used to sample input voltage and sh... View full abstract»

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  • Theory and applications of cellular automata for synthesis of easily testable combinational logic

    Publication Year: 1995, Page(s):146 - 152
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    Characterization of a special class of nongroup CA termed as D1*CA has been proposed previously (1993) along with its application for synthesis of easily testable FSM. This paper extends application of the D1*CA as an ideal test machine for testing combinational logic (CL) blocks and registers of a circuit. Such a test machine can be conveniently embedded in the data path synthesis phase around th... View full abstract»

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  • An effective BIST design for PLA

    Publication Year: 1995, Page(s):298 - 302
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper, we describe a new design of built-in self test for programmable logic arrays (PLAs). The idea is to use a simple deterministic test pattern generator to generate test patterns such that each cross point in the AND array can be evaluated one after another. The simplest multiple input signature register which uses XQ+1 as its characteristic polynomial is used to evaluate th... View full abstract»

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  • A simple technique for locating gate-level faults in combinational circuits

    Publication Year: 1995, Page(s):65 - 70
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper presents a simple technique for locating single gate-level faults in combinational circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to eval... View full abstract»

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  • An efficient comparative concurrent Built-In Self-Test technique

    Publication Year: 1995, Page(s):309 - 315
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test... View full abstract»

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  • A cellular array designed from a Multiple-valued Decision Diagram and its fault tests

    Publication Year: 1995, Page(s):20 - 24
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper, we discuss easily testable cellular arrays that are constructed from Multiple-valued Decision Diagrams (MDD's). The cellular arrays consist of cells having simple switch functions. Since control inputs that specify switches of cells are determined easily by tracing paths activated in MDD's, our method for constructing cellular arrays is simple. We propose fault tests for multiple st... View full abstract»

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  • An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits

    Publication Year: 1995, Page(s):237 - 243
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    An improved hierarchical testing algorithm for combinational circuits with repetitive sub-circuits using the bus fault model has been proposed. This model exploits the regularity of a circuit by grouping together identical gate-level sub-circuits into high-level sub-circuits. Though the existing test generation techniques using this model reduces the required time substantially in many cases, it f... View full abstract»

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  • Low power design and its testability

    Publication Year: 1995, Page(s):361 - 366
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In this paper, we propose a power reduction tool named PORT, which evaluates the power dissipation factor Φ by utilizing the transition probability, and which reduces Φ by utilizing sets of permissible functions. Experimental results show the usefulness of PORT. Next, we will consider on the testability of circuits transformed by PORT. The size of the test set generated by compact test set... View full abstract»

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  • A programmable multiple-sequence generator for BIST applications

    Publication Year: 1995, Page(s):279 - 285
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, a programmable multiple-sequence generation scheme, which is constructed from a two-dimension-like feedback shift register structure, to generate a set of deterministic sequence of vectors followed by pseudo-random vectors is presented. A sequence segmentation method is employed to handle a long sequence of vectors. The proposed scheme has a regular structure, and the sequences so g... View full abstract»

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  • Generation of tenacious tests for small gate delay faults in combinational circuits

    Publication Year: 1995, Page(s):332 - 338
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious test ⟨V1, V2⟩ for a small gate delay fault on line L. The tenacious test... View full abstract»

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  • A graph coloring based approach for self-checking logic circuit design

    Publication Year: 1995, Page(s):327 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outp... View full abstract»

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  • On the development of power supply voltage control testing technique for analogue circuits

    Publication Year: 1995, Page(s):133 - 139
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    This paper discusses a novel testing technique for analogue circuits. The theory behind its success in exposing defects normally unexposed by other testing techniques is presented. This is supported by simulation results and real IC tests. Due to its modest requirement to perform the test, this testing scheme is more attractive and beneficial. Methods of data analysis are also proposed to expose h... View full abstract»

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