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Proceedings of the Fourth Asian Test Symposium

23-24 Nov. 1995

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Displaying Results 1 - 25 of 59
  • Fanout fault analysis for digital logic circuits

    Publication Year: 1995, Page(s):33 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB)

    Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Im... View full abstract»

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  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • Sequential logic path delay test generation by symbolic analysis

    Publication Year: 1995, Page(s):353 - 359
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Many test generation algorithms for path delay faults assume a special methodology for application of the test sequence. The two-vector test sequences are valid under the assumption that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such vectors may be acceptable for combinational circuits, their use for testing a non-scan sequ... View full abstract»

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  • Boolean process-an analytical approach to circuit representation. II

    Publication Year: 1995, Page(s):26 - 32
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    For pt. I see ibid. (1994). Incorporating performance factors in the physical and logical design of VLSI circuits is necessary for performance enhancement. Boolean process provides an analytical approach to circuit representation to precisely describe logical and timing behavior simultaneously. It allows input and output of circuits be described by waveform functions, which is consistant with comm... View full abstract»

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  • Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

    Publication Year: 1995, Page(s):346 - 352
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential... View full abstract»

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  • A design-for-test technique for multistage analog circuits

    Publication Year: 1995, Page(s):113 - 119
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog ... View full abstract»

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  • Testing of a parallel ternary multiplier using I2L logic

    Publication Year: 1995, Page(s):387 - 391
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    A generalized model for faults in multivalued I2L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I2L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The gene... View full abstract»

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  • An effective BIST scheme for carry-save and carry-propagate array multipliers

    Publication Year: 1995, Page(s):286 - 292
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces a very effective BIST scheme for carry-propagate and carry-save array multipliers. The deterministic BIST patterns produced by the Test Pattern ... View full abstract»

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  • A cellular array designed from a Multiple-valued Decision Diagram and its fault tests

    Publication Year: 1995, Page(s):20 - 24
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper, we discuss easily testable cellular arrays that are constructed from Multiple-valued Decision Diagrams (MDD's). The cellular arrays consist of cells having simple switch functions. Since control inputs that specify switches of cells are determined easily by tracing paths activated in MDD's, our method for constructing cellular arrays is simple. We propose fault tests for multiple st... View full abstract»

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  • Functional test generation for path delay faults

    Publication Year: 1995, Page(s):339 - 345
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    We present a novel test generation technique for path delay faults, based on the growth (G) and disappearance (D) faults of programmable logic arrays (PLA). The circuit is modeled as a PLA that is prime and irredundant with respect to every output. Certain tests for G faults, generated by using known efficient methods are transformed into tests for path delay faults. Our algorithm generates tests ... View full abstract»

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  • Training diploma students on ATE-related module

    Publication Year: 1995, Page(s):184 - 187
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    This paper presents the approach adopted by a tertiary institution in teaching ATE-related module to final year students. The Automated Test Systems module is one of the three core subjects taught in the Microelectronics option of a Diploma offered by the Electronics and Communication Engineering (EC) Department of the Singapore Polytechnic. The module aims, teaching methods and means of assessmen... View full abstract»

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  • Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing

    Publication Year: 1995, Page(s):107 - 111
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficient. In comparison to two different dataflow computation schemes and their hardware-accelerated implement... View full abstract»

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  • DFT for fast testing of self-timed control circuits

    Publication Year: 1995, Page(s):382 - 386
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper, we present a methodology to perform fast testing of the control path of self-timed circuits. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler (1991). This Compiler translates an OCCAM program description into an interconnection of pre-existing self-... View full abstract»

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  • Static compaction for two-pattern test sets

    Publication Year: 1995, Page(s):222 - 228
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Ex... View full abstract»

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  • A programmable multiple-sequence generator for BIST applications

    Publication Year: 1995, Page(s):279 - 285
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, a programmable multiple-sequence generation scheme, which is constructed from a two-dimension-like feedback shift register structure, to generate a set of deterministic sequence of vectors followed by pseudo-random vectors is presented. A sequence segmentation method is employed to handle a long sequence of vectors. The proposed scheme has a regular structure, and the sequences so g... View full abstract»

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  • Exploitation of parallelism in group probing for testing massively parallel processing systems

    Publication Year: 1995, Page(s):15 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In this paper, we present a test structure for identifying faulty processing or switching nodes in massively parallel processing systems. The structure does not require any precomputed and stored responses. It is based on group probing and leads to a high test performance by exploiting parallelism in testing. Once a fault is detected, the expected response is obtained by finding a dominant group o... View full abstract»

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  • Generation of tenacious tests for small gate delay faults in combinational circuits

    Publication Year: 1995, Page(s):332 - 338
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious test ⟨V1, V2⟩ for a small gate delay fault on line L. The tenacious test... View full abstract»

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  • Testable design of non-scan sequential circuits using extra logic

    Publication Year: 1995, Page(s):176 - 182
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or test... View full abstract»

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  • Serial transistor network modeling for bridging fault simulation

    Publication Year: 1995, Page(s):100 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor netw... View full abstract»

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  • Fast functional testing of delay-insensitive circuits

    Publication Year: 1995, Page(s):375 - 381
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin's method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously t... View full abstract»

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  • Deterministic test generation for non-classical faults on the gate level

    Publication Year: 1995, Page(s):244 - 251
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pat... View full abstract»

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  • Generator choices for delay test

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions... View full abstract»

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  • Module level weighted random patterns

    Publication Year: 1995, Page(s):274 - 278
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signatur... View full abstract»

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  • An SBus Multi Tracer and its applications

    Publication Year: 1995, Page(s):9 - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    An SBus Multi Tracer (MT) is described, which is based on our previously developed SBus monitoring board (SMB), which can provide timing diagrams for all SBus signals. However, just like any other logic analyzer or a bus analyzer its trace length is limited by the board memory and it is difficult to cope with multi occurrences of trigger patterns in a single application. An effective answer to thi... View full abstract»

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  • A graph coloring based approach for self-checking logic circuit design

    Publication Year: 1995, Page(s):327 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outp... View full abstract»

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