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Proceedings of the Fourth Asian Test Symposium

23-24 Nov. 1995

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Displaying Results 1 - 25 of 59
  • Fanout fault analysis for digital logic circuits

    Publication Year: 1995, Page(s):33 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB)

    Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Im... View full abstract»

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  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • A graph coloring based approach for self-checking logic circuit design

    Publication Year: 1995, Page(s):327 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outp... View full abstract»

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  • Generalized modular design of testable m-out-of-n code checker

    Publication Year: 1995, Page(s):322 - 326
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    A testable design of a programmable m-out-of-n code checker is reported in this paper. The checker is modular in nature and can be easily extended by cascading. Basically, a cellular automaton (CA) structure is taken whose combinational logic port (CL-part) is modified in such a way that all the 1's in the initial state (seed) get accumulated in the rightmost cells. This CA is then transformed int... View full abstract»

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  • Totally Self Checking reconfigurable duplication system with separate internal fault indication

    Publication Year: 1995, Page(s):316 - 321
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A Totally Self Checking (TSC) reconfigurable duplication system with respect to single cell fault model is described in this paper. It consists of two identical functional self checking units that receive the same inputs. TSC checkers are associated with each functional unit and produce either a normal indication when the output is correct or an error indication when the output is incorrect. The c... View full abstract»

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  • Distributed off-line testing of parallel systems

    Publication Year: 1995, Page(s):2 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    This paper deals with off-line testing of parallel systems. The applicability of distributed self-diagnosis algorithms is investigated. Both static and adaptive testing assignment strategies are studied and evaluated using a queueing network model of the system under test. Key results include testing latency and message load of each algorithm View full abstract»

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  • An efficient comparative concurrent Built-In Self-Test technique

    Publication Year: 1995, Page(s):309 - 315
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test... View full abstract»

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  • Training diploma students on ATE-related module

    Publication Year: 1995, Page(s):184 - 187
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    This paper presents the approach adopted by a tertiary institution in teaching ATE-related module to final year students. The Automated Test Systems module is one of the three core subjects taught in the Microelectronics option of a Diploma offered by the Electronics and Communication Engineering (EC) Department of the Singapore Polytechnic. The module aims, teaching methods and means of assessmen... View full abstract»

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  • Generator choices for delay test

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions... View full abstract»

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  • Error masking in compact testing based on the Hamming code and its modifications

    Publication Year: 1995, Page(s):303 - 307
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Probability that an invalid sequence at an output of a device under test is not detected (error masking) is the measure of the effectiveness of compact testing methods. This paper evaluates and analyses the probability distribution of error masking for compact testing by exploiting the characteristics both of the Hamming code (i.e., the signature analysis) and of some modified Hamming codes. To st... View full abstract»

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  • Testable design of non-scan sequential circuits using extra logic

    Publication Year: 1995, Page(s):176 - 182
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or test... View full abstract»

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  • Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

    Publication Year: 1995, Page(s):346 - 352
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential... View full abstract»

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  • Testability analysis of co-designed systems

    Publication Year: 1995, Page(s):206 - 212
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    This paper focus on the testability analysis of co-designed data-flow specifications. The co-designed specification level implies a high level testability analysis, independent of the implementation choices. With respect to testability, the difficulties of generating test sets, detecting and diagnosing faults are discussed and estimates are proposed. A hardware modelling, based on information tran... View full abstract»

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  • A new method for testing mixed analog and digital circuits

    Publication Year: 1995, Page(s):127 - 132
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper a new method is proposed for observing analog test points inside integrated circuits that enables the simultaneous observation of a large number of points. The method permits the removal of the analog multiplexer from the signal path and a reduction of the load introduced at the observed test points. A charge coupled device analog shift register is used to sample input voltage and sh... View full abstract»

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  • A simple technique for locating gate-level faults in combinational circuits

    Publication Year: 1995, Page(s):65 - 70
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper presents a simple technique for locating single gate-level faults in combinational circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to eval... View full abstract»

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  • Software transformations for sequential test generation

    Publication Year: 1995, Page(s):266 - 272
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    This paper presents software (model) transformations that can be used to effectively generate high fault coverage test sets. Unlike synthesis or design for testability methods which involve hardware modifications, this approach does not modify the hardware design. Instead, it transforms a software model of the design into a new software model that has desirable testability properties. A sequential... View full abstract»

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  • An effective BIST design for PLA

    Publication Year: 1995, Page(s):298 - 302
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper, we describe a new design of built-in self test for programmable logic arrays (PLAs). The idea is to use a simple deterministic test pattern generator to generate test patterns such that each cross point in the AND array can be evaluated one after another. The simplest multiple input signature register which uses XQ+1 as its characteristic polynomial is used to evaluate th... View full abstract»

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  • Test sequence compaction by reduced scan shift and retiming

    Publication Year: 1995, Page(s):169 - 175
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flop... View full abstract»

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  • Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing

    Publication Year: 1995, Page(s):107 - 111
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficient. In comparison to two different dataflow computation schemes and their hardware-accelerated implement... View full abstract»

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  • Functional test generation for path delay faults

    Publication Year: 1995, Page(s):339 - 345
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    We present a novel test generation technique for path delay faults, based on the growth (G) and disappearance (D) faults of programmable logic arrays (PLA). The circuit is modeled as a PLA that is prime and irredundant with respect to every output. Certain tests for G faults, generated by using known efficient methods are transformed into tests for path delay faults. Our algorithm generates tests ... View full abstract»

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  • Testability forecasting for sequential circuits

    Publication Year: 1995, Page(s):199 - 205
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Of all the developments of testable as well as reliable designs for computing systems, test generations for sequential circuits are usually viewed as one of the hard nuts to be solved in terms of complexity and time-consumption. Although some dozens of algorithms have been proposed to cope with these issues, much still remains to be desired in solving such problems so as to determine: (1) which of... View full abstract»

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  • DFT for fast testing of self-timed control circuits

    Publication Year: 1995, Page(s):382 - 386
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper, we present a methodology to perform fast testing of the control path of self-timed circuits. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler (1991). This Compiler translates an OCCAM program description into an interconnection of pre-existing self-... View full abstract»

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  • DC control and observation structures for analog circuits

    Publication Year: 1995, Page(s):120 - 126
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    As the complexity of electronic circuits and systems increases, so does the complexity of testing them. The level-sensitive scan-design (LSSD) structure used in a digital circuit enhances the controllability and observability of the circuit under test. For analog circuits, there also are several approaches proposed to improve their observability, based on the LSSD concept. However, none of these a... View full abstract»

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  • Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing

    Publication Year: 1995, Page(s):58 - 64
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    In this paper, we improve the previous method by enhancing a set of diagnostic tests and using an EB testing method. We first enhance the previous set of diagnostic tests to one of diagnostic tests consisting of the four sets, TP-1, TP-2, TP-3 and TP-4. We next present two diagnostic methods by using the enhanced diagnostic tests and an electron-beam tester (EB-tester). Experimental results show t... View full abstract»

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  • A cellular array designed from a Multiple-valued Decision Diagram and its fault tests

    Publication Year: 1995, Page(s):20 - 24
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper, we discuss easily testable cellular arrays that are constructed from Multiple-valued Decision Diagrams (MDD's). The cellular arrays consist of cells having simple switch functions. Since control inputs that specify switches of cells are determined easily by tracing paths activated in MDD's, our method for constructing cellular arrays is simple. We propose fault tests for multiple st... View full abstract»

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