Proceedings of the Fourth Asian Test Symposium

23-24 Nov. 1995

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Displaying Results 1 - 25 of 59
  • Fanout fault analysis for digital logic circuits

    Publication Year: 1995, Page(s):33 - 39
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (659 KB)

    Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Im... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Training diploma students on ATE-related module

    Publication Year: 1995, Page(s):184 - 187
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    This paper presents the approach adopted by a tertiary institution in teaching ATE-related module to final year students. The Automated Test Systems module is one of the three core subjects taught in the Microelectronics option of a Diploma offered by the Electronics and Communication Engineering (EC) Department of the Singapore Polytechnic. The module aims, teaching methods and means of assessmen... View full abstract»

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  • Testable design of non-scan sequential circuits using extra logic

    Publication Year: 1995, Page(s):176 - 182
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB)

    Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or test... View full abstract»

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  • Test sequence compaction by reduced scan shift and retiming

    Publication Year: 1995, Page(s):169 - 175
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (524 KB)

    This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flop... View full abstract»

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  • Testing of a parallel ternary multiplier using I2L logic

    Publication Year: 1995, Page(s):387 - 391
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB)

    A generalized model for faults in multivalued I2L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I2L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The gene... View full abstract»

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  • On the development of power supply voltage control testing technique for analogue circuits

    Publication Year: 1995, Page(s):133 - 139
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    This paper discusses a novel testing technique for analogue circuits. The theory behind its success in exposing defects normally unexposed by other testing techniques is presented. This is supported by simulation results and real IC tests. Due to its modest requirement to perform the test, this testing scheme is more attractive and beneficial. Methods of data analysis are also proposed to expose h... View full abstract»

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  • Test configurations to enhance the testability of sequential circuits

    Publication Year: 1995, Page(s):160 - 168
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (688 KB)

    The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operat... View full abstract»

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  • An approach to hierarchy model checking via evaluating CTL hierarchically

    Publication Year: 1995, Page(s):45 - 49
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    Symbolic Model Checking is one of the most efficient formal verification methods for hardware design. It uses Computational Tree Logic (CTL) for expressing formal specification of hardware design. However, the large demands of space by Symbolic Model Checking prevents itself from verifying large automates. In this paper we study the possibility of hierarchy evaluation of CTL formula. The result sh... View full abstract»

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  • Deterministic test generation for non-classical faults on the gate level

    Publication Year: 1995, Page(s):244 - 251
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (780 KB)

    This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pat... View full abstract»

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  • DFT for fast testing of self-timed control circuits

    Publication Year: 1995, Page(s):382 - 386
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (512 KB)

    In this paper, we present a methodology to perform fast testing of the control path of self-timed circuits. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler (1991). This Compiler translates an OCCAM program description into an interconnection of pre-existing self-... View full abstract»

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  • Fast fault simulation for BIST applications

    Publication Year: 1995, Page(s):93 - 99
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (872 KB)

    Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propa... View full abstract»

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  • A new method for testing mixed analog and digital circuits

    Publication Year: 1995, Page(s):127 - 132
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    In this paper a new method is proposed for observing analog test points inside integrated circuits that enables the simultaneous observation of a large number of points. The method permits the removal of the analog multiplexer from the signal path and a reduction of the load introduced at the observed test points. A charge coupled device analog shift register is used to sample input voltage and sh... View full abstract»

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  • Unified scan design with scannable memory arrays

    Publication Year: 1995, Page(s):153 - 159
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (632 KB)

    Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can g... View full abstract»

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  • Software transformations for sequential test generation

    Publication Year: 1995, Page(s):266 - 272
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (712 KB)

    This paper presents software (model) transformations that can be used to effectively generate high fault coverage test sets. Unlike synthesis or design for testability methods which involve hardware modifications, this approach does not modify the hardware design. Instead, it transforms a software model of the design into a new software model that has desirable testability properties. A sequential... View full abstract»

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  • Metastability evaluation method by propagation delay distribution measurement

    Publication Year: 1995, Page(s):40 - 44
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (468 KB)

    This paper suggests an experimental method for determining metastability properties based on deliberately inducing metastability in edge-triggered flip-flops. It offers the opportunity to analyze the impact of input signals time relationship on the output signal timing characteristics, using graphical and analytical representation of the propagation delay density distribution function. A new appro... View full abstract»

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  • An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits

    Publication Year: 1995, Page(s):237 - 243
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    An improved hierarchical testing algorithm for combinational circuits with repetitive sub-circuits using the bus fault model has been proposed. This model exploits the regularity of a circuit by grouping together identical gate-level sub-circuits into high-level sub-circuits. Though the existing test generation techniques using this model reduces the required time substantially in many cases, it f... View full abstract»

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  • Fast functional testing of delay-insensitive circuits

    Publication Year: 1995, Page(s):375 - 381
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (560 KB)

    Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin's method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously t... View full abstract»

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  • On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation

    Publication Year: 1995, Page(s):86 - 92
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (620 KB)

    This paper presents an advanced concurrent simulation technique for performing Multiple Stuck-at Fault Simulation based on Multiple Domain Concurrent and Comparative Simulation (MDCCS). It efficiently compresses multiple experiments in a single simulation and requires no pre-analysis of the circuit. In addition, MDCCS has a unique feature that allows experiments to interact with each other and spa... View full abstract»

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  • A cellular array designed from a Multiple-valued Decision Diagram and its fault tests

    Publication Year: 1995, Page(s):20 - 24
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    In this paper, we discuss easily testable cellular arrays that are constructed from Multiple-valued Decision Diagrams (MDD's). The cellular arrays consist of cells having simple switch functions. Since control inputs that specify switches of cells are determined easily by tracing paths activated in MDD's, our method for constructing cellular arrays is simple. We propose fault tests for multiple st... View full abstract»

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  • Generator choices for delay test

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (632 KB)

    An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions... View full abstract»

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  • DC control and observation structures for analog circuits

    Publication Year: 1995, Page(s):120 - 126
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (760 KB)

    As the complexity of electronic circuits and systems increases, so does the complexity of testing them. The level-sensitive scan-design (LSSD) structure used in a digital circuit enhances the controllability and observability of the circuit under test. For analog circuits, there also are several approaches proposed to improve their observability, based on the LSSD concept. However, none of these a... View full abstract»

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  • Sequential logic path delay test generation by symbolic analysis

    Publication Year: 1995, Page(s):353 - 359
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (652 KB)

    Many test generation algorithms for path delay faults assume a special methodology for application of the test sequence. The two-vector test sequences are valid under the assumption that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such vectors may be acceptable for combinational circuits, their use for testing a non-scan sequ... View full abstract»

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  • Theory and applications of cellular automata for synthesis of easily testable combinational logic

    Publication Year: 1995, Page(s):146 - 152
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (628 KB)

    Characterization of a special class of nongroup CA termed as D1*CA has been proposed previously (1993) along with its application for synthesis of easily testable FSM. This paper extends application of the D1*CA as an ideal test machine for testing combinational logic (CL) blocks and registers of a circuit. Such a test machine can be conveniently embedded in the data path synthesis phase around th... View full abstract»

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  • Universal test complexity of field-programmable gate arrays

    Publication Year: 1995, Page(s):259 - 265
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (688 KB)

    A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random ac... View full abstract»

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