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Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Date Aug. 29 1995-Sept. 1 1995

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Displaying Results 1 - 25 of 132
  • Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1995 (ASP-DAC '95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award IFIP International Conference on Computer Hardware Discription Language and their Applications 1995 (CHDL'95)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (17 KB)
    Freely Available from IEEE
  • Best Paper Award Candidates IFIP International Conference on Very Large Scale Integration 1995 (VLSI'95))

    Publication Year: 1995
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    Freely Available from IEEE
  • Logic rectification and synthesis for engineering change

    Publication Year: 1995, Page(s):301 - 309
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB)

    In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the exi... View full abstract»

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  • Routing on regular segmented 2-D FPGAs

    Publication Year: 1995, Page(s):329 - 334
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB)

    In this paper we analyze the properties of the Xilinx-like regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). We introduce a new notion of architectural level routing decaying effect caused by wiring segmentation. We discuss its routing properties and propose a relative prime number based segmentation scheme for 2-D FPGA architectures. A new FPGA design concept of applyin... View full abstract»

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  • Conference Author/Panelist Index

    Publication Year: 1995
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    Freely Available from IEEE
  • Current and charge estimation in CMOS circuits

    Publication Year: 1995, Page(s):13 - 18
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the total in circuits that have not been designed carefully. This current depends strongly on the relative sizes of the pull-up to pull-down paths. We introduce the dynamic short-circuit ratio to model this parameter. This allows... View full abstract»

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  • Power reduction by gate sizing with path-oriented slack calculation

    Publication Year: 1995, Page(s):7 - 12
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    This paper describes methods for reducing power consumption. We propose using gate sizing technique to reduce power for circuits that have already satisfied the timing constraint. Replacement of gates on noncritical paths with smaller templates is used in reducing the dissipated power of a circuit. We find that not only gates on noncritical paths can be down-sized, but also gates on critical paths... View full abstract»

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  • A prover for VHDL-based hardware design

    Publication Year: 1995, Page(s):643 - 650
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Surveys a self-contained part of the ESPRIT-project “FORMAT”, which develops a prover for VHDL-based hardware design. Notable is the use of a graphical specification language called STD (Symbolic Timing Diagrams), which can be seen as a visual dialect of temporal logic. The heart of the prover is built by two powerful industrial verification tools: A (compositional) symbolic model chec... View full abstract»

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  • Transistor reordering rules for power reduction in CMOS gates

    Publication Year: 1995, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the ... View full abstract»

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  • The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor

    Publication Year: 1995, Page(s):637 - 642
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    We present an introduction to the DUAL-EVAL hardware description language. DUAL-EVAL is a hierarchical, occurrence-oriented simulator for synchronous Mealy machines. We briefly describe the FM9001 microprocessor, whose design has been formally specified with the DUAL-EVAL language and mechanically proved correct with respect to a behavioral specification. The FM9001 has been fabricated as a CMOS A... View full abstract»

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  • Symbolic verification of hardware systems

    Publication Year: 1995, Page(s):631 - 636
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are val... View full abstract»

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  • Verifying pipelined microprocessors

    Publication Year: 1995, Page(s):503 - 511
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement should show that the parallel machine represented by the pipeline behaves in the same manner as the sequentia... View full abstract»

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  • Automatic verification of memory systems which service their requests out of order

    Publication Year: 1995, Page(s):623 - 630
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    In a shared memory multi-processor environment, one can achieve greater performance by out-of-order servicing of memory requests. Although this results in higher performance, such systems are complicated and their design and programming requires care. Recently, there have been efforts to develop concise formal specifications of such systems. We present a general strategy, based on the language con... View full abstract»

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  • Performance verification using PDL and constraint satisfaction

    Publication Year: 1995, Page(s):531 - 538
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The performance description language PDL provides a compact notation for the specification of non-functional attributes of VLSI systems. This paper presents evaluation mechanisms which allow the designer to assert performance goals on PDL models of VLSI systems and determine if the constrained models are satisfiable. This is done by developing a PDL performance model and constructing a constraint ... View full abstract»

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  • Applying formal verification to a commercial microprocessor

    Publication Year: 1995, Page(s):493 - 502
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    Formal verification using interactive proof-checkers has been used successfully to verify a wide variety of moderate-sized hardware designs. The industry is beginning to look at formal verification as an alternative to simulation for obtaining higher assurance than is currently possible. However, many questions remain regarding its use in practice: Can these techniques scale up to industrial syste... View full abstract»

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  • Explicit-enumeration based verification made memory-efficient

    Publication Year: 1995, Page(s):617 - 622
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    We investigate new techniques for reducing the memory requirements of an on-the-fly model checking tool that employs explicit enumeration. Two techniques are studied in depth: exploiting symmetries in the model, and exploiting sequential regions in the model. These techniques can result in a significant reduction in memory requirements, and often find progress violations at much lower stack depths... View full abstract»

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  • Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits

    Publication Year: 1995, Page(s):567 - 573
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    We propose an algorithm combining two approaches to PN verification: PN unfolding and BDD-based traversal. We introduce a new application of the PN unfolding method. The results of unfolding construction are used for obtaining the close-to-optimal ordering of BDD variables. The effect of this combination is demonstrated on a set of benchmarks. The overall framework has been used for the verificati... View full abstract»

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  • A new performance driven placement method with the Elmore delay model for row based VLSIs

    Publication Year: 1995, Page(s):405 - 412
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iter... View full abstract»

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  • Stoht-an SDL-to-Hardware Translator

    Publication Year: 1995, Page(s):33 - 36
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This article presents a language translator that allows the use of SDL as a front-end, high-level graphical description tool for hardware design. A subset of this language is proposed for hardware design, including a synthesisable model for SDL's signal-based communication. An algorithm to translate this subset to fully synthesisable VHDL is proposed and implemented in a public-domain software pac... View full abstract»

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  • Integrating design and verification environments through a logic supporting hardware diagrams

    Publication Year: 1995, Page(s):669 - 674
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Formal methods and verification tools are difficult for designers to use. Research has been concentrated on handling large proofs; meanwhile, insufficient attention has been paid to the reasoning process. We argue that a heterogeneous logic supporting hardware diagrams and sentential logic provides a natural framework for reasoning and for the formal integration of design and verification environm... View full abstract»

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  • A methodology for the development of integrated and open HDL-based design environments

    Publication Year: 1995, Page(s):525 - 530
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A methodology for the development of integrated and open HDL-based design environments is proposed. It considers different tool integration approaches and the selection of either environment-independent or dependent HDLs and tools. Following this methodology, an application designer can develop an ideal environment with regard to integration and openness. The interplay between HDLs and integrated ... View full abstract»

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  • Reclocking for high level synthesis

    Publication Year: 1995, Page(s):49 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for... View full abstract»

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  • A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems

    Publication Year: 1995, Page(s):67 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    A simple mathematical framework, called cluster-cover, is established for several VLSI optimisation problems including logic minimization, constrained encoding, multi-layer topological planar routing, application timing assignment for delay-fault testing, and minimization of monitoring logic for BIST enhancement. Two paradigms, prime covering and greedy peeling, are presented for developing both e... View full abstract»

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  • Synthesis-for-testability using transformations

    Publication Year: 1995, Page(s):485 - 490
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. A two-stage objective function, that estimates the area and testability of the final implementation, and also captures enabling effects of the transformation... View full abstract»

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