Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Aug. 29 1995-Sept. 1 1995

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Displaying Results 1 - 25 of 132
  • Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1995 (ASP-DAC '95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award IFIP International Conference on Computer Hardware Discription Language and their Applications 1995 (CHDL'95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award Candidates IFIP International Conference on Very Large Scale Integration 1995 (VLSI'95))

    Publication Year: 1995
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    Freely Available from IEEE
  • Logic rectification and synthesis for engineering change

    Publication Year: 1995, Page(s):301 - 309
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB)

    In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the exi... View full abstract»

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  • Routing on regular segmented 2-D FPGAs

    Publication Year: 1995, Page(s):329 - 334
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB)

    In this paper we analyze the properties of the Xilinx-like regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). We introduce a new notion of architectural level routing decaying effect caused by wiring segmentation. We discuss its routing properties and propose a relative prime number based segmentation scheme for 2-D FPGA architectures. A new FPGA design concept of applyin... View full abstract»

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  • EDIF Version 350/400 and information modelling

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB)

    Summary form only given. The design and implementation of the EDIF family of standards is based on the use of the specification technique called information modelling. The goal of information modelling is to provide the standards development process with a methodology that will ensure, as far as is possible, that the contents of the standard are correct, consistent and clearly defined. The first p... View full abstract»

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  • Conference Author/Panelist Index

    Publication Year: 1995
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    Freely Available from IEEE
  • A layout approach to monolithic microwave IC

    Publication Year: 1995, Page(s):265 - 272
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout el... View full abstract»

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  • Implementation of a recursive real time edge detector using retiming techniques

    Publication Year: 1995, Page(s):811 - 816
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 μm process (area 29 mm2). This ASIC is able to process a pixel in less than 30... View full abstract»

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  • An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

    Publication Year: 1995, Page(s):101 - 106
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis, and integrated user interface and internal representation. As an experimental example, a he... View full abstract»

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  • A datapath synthesis system for the reconfigurable datapath architecture

    Publication Year: 1995, Page(s):479 - 484
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto the rDPA without manual interaction. The required algorithms of this synthesis system are described in detail. Optimization techniques like loop folding or loop unrolling are sketched. The rDPA is scalable to arbitrarily large arrays... View full abstract»

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  • Description and verification of RTL designs using multiway decision graphs

    Publication Year: 1995, Page(s):575 - 580
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Traditional OBDD-based methods of automated verification suffer from, the drawback that they require a binary representation of the circuit. Multiway Decision Graphs (MDGs) combine the advantages of OBDD techniques with those of abstract types. RTL designs can be compactly described by MDGs using abstract data values and uninterpreted function symbols. We have developed MDG-based techniques for co... View full abstract»

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  • Reclocking for high level synthesis

    Publication Year: 1995, Page(s):49 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for... View full abstract»

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  • A new layout synthesis for leaf cell design

    Publication Year: 1995, Page(s):259 - 264
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design View full abstract»

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  • On variable ordering and decomposition type choice in OKFDDs

    Publication Year: 1995, Page(s):805 - 810
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    We present methods for the construction of small ordered Kronecker functional decision diagrams (OKFDDs). OKFDDs are a generalization of ordered binary decision diagrams (OBDDs) and ordered functional decision diagrams (OFDDs) as well. Starting with an upper bound for the size of an OKFDD representing a tree like circuit, we develop different heuristics to find good variable orderings and decompos... View full abstract»

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  • A Full Over-the-Cell routing model

    Publication Year: 1995, Page(s):845 - 850
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper describes a Full Over-the-Cell routing model to perform circuit connections over the transistors by using “transparent cells”. The methodology provides flexibility and the resulting layout style presents interesting performance/cost ratios if compared to those produced by Standard Cell and traditional Over-the-Cell routing models. A symbolic environment is shown, where it is... View full abstract»

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  • A scheduling algorithm for multiport memory minimization in datapath synthesis

    Publication Year: 1995, Page(s):93 - 100
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    In this paper, we present a new scheduling algorithm that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory ... View full abstract»

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  • Automatic design for bit-serial MSPA architecture

    Publication Year: 1995, Page(s):27 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    A memory sharing processor array (MSPA) architecture is effective in both data storage and processor cell utilization efficiency. In this paper, the design methodology for MSPA is extended to synthesise a bit-serial datapath. As a synthesis example, we propose a new bit-serial multiplier with a smaller number of logic gates than conventional bit-serial multipliers View full abstract»

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  • Optimum simultaneous placement and binding for bit-slice architectures

    Publication Year: 1995, Page(s):735 - 740
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overal... View full abstract»

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  • Search space reduction in high level synthesis by use of an initial circuit

    Publication Year: 1995, Page(s):471 - 477
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Most existing high-level synthesis (HLS) systems attempt to generate a circuit from a behavioral description “out of the void”, using the entire design space as the search domain. Because of the vastness of the search space, it is impossible to do more than a coarse grain search, often resulting in inefficient designs. This approach ignores the designer's knowledge of the general struc... View full abstract»

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  • Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits

    Publication Year: 1995, Page(s):567 - 573
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    We propose an algorithm combining two approaches to PN verification: PN unfolding and BDD-based traversal. We introduce a new application of the PN unfolding method. The results of unfolding construction are used for obtaining the close-to-optimal ordering of BDD variables. The effect of this combination is demonstrated on a set of benchmarks. The overall framework has been used for the verificati... View full abstract»

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  • A scheduling algorithm for synthesis of bus-partitioned architectures

    Publication Year: 1995, Page(s):43 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible View full abstract»

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  • Architectural simulation for a programmable DSP chip set

    Publication Year: 1995, Page(s):171 - 176
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 pe... View full abstract»

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  • Extending pitchmatching algorithms to layouts with multiple grid constraints

    Publication Year: 1995, Page(s):249 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. The paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving... View full abstract»

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  • Finding best cones from random clusters for FPGA package partitioning

    Publication Year: 1995, Page(s):799 - 804
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The implementation of circuits with FPGAs commonly requires partitioning into several FPGA packages. A good FPGA package partitioning tool minimizes production cost by minimizing packages required without significantly increasing the circuit operational frequency. Prior work has shown that good results can be obtained by partitioning with cone structures. Cone structure partitioning is combined wi... View full abstract»

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