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Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Date Aug. 29 1995-Sept. 1 1995

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Displaying Results 1 - 25 of 132
  • Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1995 (ASP-DAC '95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award IFIP International Conference on Computer Hardware Discription Language and their Applications 1995 (CHDL'95)

    Publication Year: 1995
    Save to Project icon | Request Permissions | PDF file iconPDF (17 KB)  
    Freely Available from IEEE
  • Best Paper Award Candidates IFIP International Conference on Very Large Scale Integration 1995 (VLSI'95))

    Publication Year: 1995
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • Logic rectification and synthesis for engineering change

    Publication Year: 1995 , Page(s): 301 - 309
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (839 KB)  

    In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the exi... View full abstract»

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  • Routing on regular segmented 2-D FPGAs

    Publication Year: 1995 , Page(s): 329 - 334
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (643 KB)  

    In this paper we analyze the properties of the Xilinx-like regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). We introduce a new notion of architectural level routing decaying effect caused by wiring segmentation. We discuss its routing properties and propose a relative prime number based segmentation scheme for 2-D FPGA architectures. A new FPGA design concept of applyin... View full abstract»

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  • Conference Author/Panelist Index

    Publication Year: 1995
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    Freely Available from IEEE
  • Silicon single-electron transistors on a SIMOX substrate

    Publication Year: 1995 , Page(s): 697 - 698
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (180 KB)  

    Until recently, single-electron transistors have only been operable at very low temperatures, mostly below 1 K. By contrast, Si single-electron transistors fabricated on a SIMOX substrate by using a pattern-dependent oxidation technique show conductance oscillations even at room temperature. In addition, a single-electron memory effect is observed in specially designed Si single-electron transisto... View full abstract»

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  • Test pattern embedding in sequential circuits through cellular automata

    Publication Year: 1995 , Page(s): 699 - 704
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (596 KB)  

    The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such... View full abstract»

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  • Architectural simulation for a programmable DSP chip set

    Publication Year: 1995 , Page(s): 171 - 176
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (832 KB)  

    This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 pe... View full abstract»

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  • Design automation for integrated continuous-time filters using integrators

    Publication Year: 1995 , Page(s): 435 - 439
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (316 KB)  

    This paper proposes a design automation for filters using integrators. This is based on a predistortion without knowledge of a filter topology. The predistortion requires an integrator having the same structure, the same-value elements and an electrically controllable unity-gain frequency, and compensates for the deviation of frequency characteristics due to an excess phase shift of an integrator.... View full abstract»

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  • Exploiting signal flow and logic dependency in standard cell placement

    Publication Year: 1995 , Page(s): 399 - 404
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (556 KB)  

    Most existing placement algorithms consider only connectivity information during the placement process, and ignore other information available from the higher levels of design process. In this paper, we exploit the use of signal flow and logic dependency in standard cell placement by using the maximum fanout-free cone (MFFC) decomposition technique. We developed a containment tree based algorithm ... View full abstract»

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  • Evaluation and composition of specification languages, an industrial point of view

    Publication Year: 1995 , Page(s): 519 - 523
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (460 KB)  

    This paper deals with experience with specification languages at AEROSPATIALE Aircraft, Systems and Avionics Division. We describe first the current avionics development environment. Then, we present our results and viewpoints on the use of the three specification languages: LOTOS, ESTEREL, and B. The evaluation studies we performed, showed that each of these languages does not cover in a complete... View full abstract»

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  • Integrating design and verification environments through a logic supporting hardware diagrams

    Publication Year: 1995 , Page(s): 669 - 674
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (508 KB)  

    Formal methods and verification tools are difficult for designers to use. Research has been concentrated on handling large proofs; meanwhile, insufficient attention has been paid to the reasoning process. We argue that a heterogeneous logic supporting hardware diagrams and sentential logic provides a natural framework for reasoning and for the formal integration of design and verification environm... View full abstract»

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  • Communication based FPGA synthesis for multi-output Boolean functions

    Publication Year: 1995 , Page(s): 279 - 287
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (860 KB)  

    One of the crucial problems multi level logic synthesis techniques for multi output Boolean functions f=(f1,...,fm):{0,1}n→{0,1}m have to deal with is finding sublogic which can be shared by different outputs, i.e., finding Boolean functions α=(α1,...,αh):{0,1}p →{0,1}h which can be... View full abstract»

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  • A new and accurate interconnection delay time evaluation in a general tree-type network

    Publication Year: 1995 , Page(s): 359 - 364
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (440 KB)  

    In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of te... View full abstract»

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  • A new performance driven placement method with the Elmore delay model for row based VLSIs

    Publication Year: 1995 , Page(s): 405 - 412
    Cited by:  Papers (3)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (832 KB)  

    In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iter... View full abstract»

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  • Optimum simultaneous placement and binding for bit-slice architectures

    Publication Year: 1995 , Page(s): 735 - 740
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (564 KB)  

    Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overal... View full abstract»

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  • Automatic design for bit-serial MSPA architecture

    Publication Year: 1995 , Page(s): 27 - 32
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (476 KB)  

    A memory sharing processor array (MSPA) architecture is effective in both data storage and processor cell utilization efficiency. In this paper, the design methodology for MSPA is extended to synthesise a bit-serial datapath. As a synthesis example, we propose a new bit-serial multiplier with a smaller number of logic gates than conventional bit-serial multipliers View full abstract»

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  • Time parameterized function method: a new method for hardware verification with the Boyer-Moore Theorem Prover

    Publication Year: 1995 , Page(s): 545 - 552
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (556 KB)  

    We propose a new method for hardware verification using the Boyer-Moore Theorem Prover. In this method, each signal of a sequential circuit is represented not as a waveform, but as a time parameterized function. A user simply describes the logical connection of the components of a circuit, and the separated form is mechanically derived. We formalize the method and show that the method not only rea... View full abstract»

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  • A methodology for the development of integrated and open HDL-based design environments

    Publication Year: 1995 , Page(s): 525 - 530
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (580 KB)  

    A methodology for the development of integrated and open HDL-based design environments is proposed. It considers different tool integration approaches and the selection of either environment-independent or dependent HDLs and tools. Following this methodology, an application designer can develop an ideal environment with regard to integration and openness. The interplay between HDLs and integrated ... View full abstract»

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  • A hardware-oriented design for weighted median filters

    Publication Year: 1995 , Page(s): 441 - 445
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (428 KB)  

    In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design... View full abstract»

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  • Implementation of a recursive real time edge detector using retiming techniques

    Publication Year: 1995 , Page(s): 811 - 816
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (484 KB)  

    We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 μm process (area 29 mm2). This ASIC is able to process a pixel in less than 30... View full abstract»

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  • The T-Ruby design system

    Publication Year: 1995 , Page(s): 587 - 596
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (884 KB)  

    This paper describes the T-Ruby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctness-preserving transformations based on proved equivalences between relations, together with the addition of constraints. A class of implementable relations is defined. The too... View full abstract»

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  • A new system partitioning method under performance and physical constraints for multi-chip modules

    Publication Year: 1995 , Page(s): 119 - 126
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (832 KB)  

    In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and r... View full abstract»

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  • Region definition and ordering assignment with the minimization of the number of switchboxes

    Publication Year: 1995 , Page(s): 189 - 194
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB)  

    In this paper, a region definition and ordering assignment (RDAOA) algorithm for minimizing the number of switchboxes is proposed. The time complexity of the algorithm is proved to be in O(n) time, where n is the number of line segments in a given floorplan graph. Finally, several examples have been tested on the proposed algorithm and other published algorithms, and the experimental results show ... View full abstract»

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