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Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Aug. 29 1995-Sept. 1 1995

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Displaying Results 1 - 25 of 132
  • Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1995 (ASP-DAC '95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award IFIP International Conference on Computer Hardware Discription Language and their Applications 1995 (CHDL'95)

    Publication Year: 1995
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    Freely Available from IEEE
  • Best Paper Award Candidates IFIP International Conference on Very Large Scale Integration 1995 (VLSI'95))

    Publication Year: 1995
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    Freely Available from IEEE
  • Logic rectification and synthesis for engineering change

    Publication Year: 1995, Page(s):301 - 309
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB)

    In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the exi... View full abstract»

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  • Routing on regular segmented 2-D FPGAs

    Publication Year: 1995, Page(s):329 - 334
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB)

    In this paper we analyze the properties of the Xilinx-like regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). We introduce a new notion of architectural level routing decaying effect caused by wiring segmentation. We discuss its routing properties and propose a relative prime number based segmentation scheme for 2-D FPGA architectures. A new FPGA design concept of applyin... View full abstract»

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  • EDIF Version 350/400 and information modelling

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB)

    Summary form only given. The design and implementation of the EDIF family of standards is based on the use of the specification technique called information modelling. The goal of information modelling is to provide the standards development process with a methodology that will ensure, as far as is possible, that the contents of the standard are correct, consistent and clearly defined. The first p... View full abstract»

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  • Conference Author/Panelist Index

    Publication Year: 1995
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    Freely Available from IEEE
  • Limits of using signatures for permutation independent Boolean comparison

    Publication Year: 1995, Page(s):459 - 464
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations. The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification. A popular method to solve it is to compute a signature for each variable... View full abstract»

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  • Delay abstraction in combinational logic circuits

    Publication Year: 1995, Page(s):453 - 458
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. The proposed graphical data structure is of size proportional to (m+n) in best case, where m and n refer to the number of inputs and outputs of the ci... View full abstract»

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  • A new system partitioning method under performance and physical constraints for multi-chip modules

    Publication Year: 1995, Page(s):119 - 126
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and r... View full abstract»

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  • Performance-driven circuit partitioning for prototyping by using multiple FPGA chips

    Publication Year: 1995, Page(s):113 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A new performance-driven partitioning algorithm has been developed to implement a large circuit by using multiple FPGA chips. Partitioning for multiple FPGAs has several constraints to satisfy so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two phases which are the initial partitioning for... View full abstract»

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  • C++ base classes for specification, simulation and partitioning of a hardware/software system

    Publication Year: 1995, Page(s):777 - 784
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The paper introduces a novel method of specification, simulation and partitioning on the system level using a common and convenient language (C++). Special base classes provide explicit concurrency and additional possibilities for analyzing and simulating the whole system during an early design phase. The hardware/software partitioning algorithm uses the results of the analysis and simulation in o... View full abstract»

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  • Techniques for low power realization of FIR filters

    Publication Year: 1995, Page(s):447 - 450
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    We propose techniques for low power realization of FIR filters on programmable DSPs. We first analyse the FIR implementation to arrive at useful measures to reduce power and present techniques that exploit these measures. We then identify limitations of the existing DSP architectures in implementing these techniques and propose simple architectural extensions to overcome these limitations. Finally... View full abstract»

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  • A CSIC implementation with POCSAG decoder and microcontroller for paging applications

    Publication Year: 1995, Page(s):107 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper presents a CSIC (Customer Specification Integrated Circuit) implementation, which includes a 512/1200/2400 bps POCSAG decoder, PDI2400 and MC68HC05 changed by PANTECH. It can receive all the data with the rate of 512/1200/2400 bps of a single clock of 76.8 KHz. It is designed to have maximum 2 own frames for service enhancement. To improve receiver quality, a preamble detection consider... View full abstract»

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  • Optimization methods for lookup-table-based FPGAs using Transduction Method

    Publication Year: 1995, Page(s):353 - 356
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    In recent years Field Programmable Gate Arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes due to their low cost, reprogrammability and rapid turnaround times. Therefore, the need for design methods of FPGAs are getting larger and larger. In this paper, two methods to optimize networks which have been mapped for lookup-table-based FPGAs are discu... View full abstract»

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  • Extending VHDL for state based specifications

    Publication Year: 1995, Page(s):675 - 684
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    Statecharts can complement VHDL, in particular for system level design. We present what would be needed to extend VHDL by state based specification, sharing its syntax and the fundamental notion of time. The resulting integration is very tight, allowing, by comparison to existing approaches, more precise control for synthesis, incorporation of library components, multiple statechart instantiations... View full abstract»

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  • Technology mapping for FPGAs with complex block architectures by fuzzy logic technique

    Publication Year: 1995, Page(s):295 - 300
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    This paper describes a technology mapper for FPGAs with the complex structure of logic blocks. Most technology mappers developed so far are not effective for such complex logic block architectures as XILINX XC4000 series. The proposed mapper applies a constructive mapping algorithm and fuzzy logic rules to balance such criteria as area, timing, routability and others. Performance of the mapper is ... View full abstract»

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  • Explicit-enumeration based verification made memory-efficient

    Publication Year: 1995, Page(s):617 - 622
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    We investigate new techniques for reducing the memory requirements of an on-the-fly model checking tool that employs explicit enumeration. Two techniques are studied in depth: exploiting symmetries in the model, and exploiting sequential regions in the model. These techniques can result in a significant reduction in memory requirements, and often find progress violations at much lower stack depths... View full abstract»

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  • Exploiting signal flow and logic dependency in standard cell placement

    Publication Year: 1995, Page(s):399 - 404
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Most existing placement algorithms consider only connectivity information during the placement process, and ignore other information available from the higher levels of design process. In this paper, we exploit the use of signal flow and logic dependency in standard cell placement by using the maximum fanout-free cone (MFFC) decomposition technique. We developed a containment tree based algorithm ... View full abstract»

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  • A mathematically sound approach to the correct design of hardware

    Publication Year: 1995, Page(s):771 - 776
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Specification languages with a sound and well established semantics are applied to the definition of hardware devices. Exploiting these formalisms, theorem provers are introduced in the design flow to guarantee the equivalence of the different abstraction levels involved in the process of behavioural synthesis. Design constraints, such as area and timing, are evaluated linking this design phase to... View full abstract»

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  • Finding best cones from random clusters for FPGA package partitioning

    Publication Year: 1995, Page(s):799 - 804
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The implementation of circuits with FPGAs commonly requires partitioning into several FPGA packages. A good FPGA package partitioning tool minimizes production cost by minimizing packages required without significantly increasing the circuit operational frequency. Prior work has shown that good results can be obtained by partitioning with cone structures. Cone structure partitioning is combined wi... View full abstract»

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  • A hardware-oriented design for weighted median filters

    Publication Year: 1995, Page(s):441 - 445
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design... View full abstract»

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  • An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

    Publication Year: 1995, Page(s):101 - 106
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis, and integrated user interface and internal representation. As an experimental example, a he... View full abstract»

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  • Learning heuristics by genetic algorithms

    Publication Year: 1995, Page(s):349 - 352
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    In many applications of Computer Aided Design (CAD) of Integrated Circuits (ICs) the problems that have to be solved are NP-hard. Thus, exact algorithms are only applicable to small problem instances and many authors have presented heuristics to obtain solutions (non-optimal in general) for larger instances of these hard problems. In this paper we present a model for Genetic Algorithms (GA) to lea... View full abstract»

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  • Integrating design and verification environments through a logic supporting hardware diagrams

    Publication Year: 1995, Page(s):669 - 674
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Formal methods and verification tools are difficult for designers to use. Research has been concentrated on handling large proofs; meanwhile, insufficient attention has been paid to the reasoning process. We argue that a heterogeneous logic supporting hardware diagrams and sentential logic provides a natural framework for reasoning and for the formal integration of design and verification environm... View full abstract»

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