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Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on

Issue 2 • Date Apr 1997

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Displaying Results 1 - 8 of 8
  • A self-tuning EWMA controller utilizing artificial neural network function approximation techniques

    Page(s): 121 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    Recent works have shown that an exponentially weighted moving average (EWMA) controller can be used on semiconductor processes to maintain process targets over extended periods for improved product quality and decreased machine downtime. Proper choice of controller parameters (EWMA weights) is critical to the performance of this system. This work examines how different process factors affect the optimal controller parameters. We show that a function mapping from the disturbance state (magnitude of linear drift and random noise) of a given process to the corresponding optimal EWMA weights can be generated, and an artificial neural network (ANN) trained to learn the mapping. A self-tuning EWMA controller is proposed which dynamically updates its controller parameters by estimating the disturbance state and using the ANN function mapping to provide updates to the controller parameters. The result is an adaptive controller which eliminates the need for an experienced engineer to tune the controller, thereby allowing it to be more easily applied to semiconductor processes View full abstract»

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  • Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps

    Page(s): 95 - 100
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    Flip chip attachments provide the highest interconnection density possible, which makes this technology very attractive for use with liquid crystal display (LCD) packaging methods. This technology stimulated the development of new interconnection techniques, such as anisotropic adhesives. However, several factors have hindered the wide use of this technology. These factors include the availability and costs of bumped wafers. IZM and TU-Berlin have addressed both of these concerns by establishing a wafer-bumping facility which uses electroless nickel bumps. The combination of anisotropic adhesives and electroless nickel bumps has the potential for a low-cost chip on glass (COG) and chip on flex (COF) bonding technology. In this paper, two types of anisotropic adhesives were studied with an emphasis on the properties of COG and COF interconnections. The electrical and mechanical performance of the adhesive bonds was studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity View full abstract»

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  • Technology and change in the Chinese electronics industry

    Page(s): 142 - 151
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    A wide-ranging study of the technological capability of the mainland China electronics industry has been conducted. The study reveals that the Chinese industry is driven to improve technologically mainly by foreign technology transfer, though local process innovation has been observed that can improve the output of foreign process technology. Surface mount manufacturing technology is common in China, and can be near state-of-the-art. Integrated circuit (IC) technology lags world trends by more than five years. The rate of improvement in technology and output of the mainland China electronics industry suggests that mainland China is likely to rival South Korea, Taiwan, and even Japan as a major Asian force in the world industry in the twenty-first century View full abstract»

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  • Automatic classification of wafer defects: status and industry needs

    Page(s): 164 - 167
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    This paper describes the automatic defect classification (ADC) beta site evaluations performed as part of the SEMATECH ADC project. Two optical review microscopes equipped with ADC software were independently evaluated in manufacturing environments. Both microscopes were operated in bright-field mode with white light illumination, ADC performance was measured on three process levels of random logic devices: source/drain, polysilicon gate, and metal. ADC performance metrics included classification accuracy, repeatability, and speed. In particular, ADC software was tested using a protocol that included knowledge base tests, gauge studies, and small passive data collections View full abstract»

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  • A stair-like CIM system architecture

    Page(s): 101 - 110
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    Computer integrated manufacturing (CIM) has received growing acceptance from both industries and academia alike. However, even with the increasing reliance on computing technologies, there are still wide-spread concerns about the true impacts on the actual performance of the companies implementing CIM. In particular, the overall coherence of the entire system has been considered as a key issue. To address this problem, there is a significant amount of interest in the CIM system architecture, that is, in considering the integration of technology, people and business from the viewpoint of a global system. This paper will first review some major existing CIM system architectures, including CIM-OSA, GRAI-GIM, and PERA. Then, based on the requirements from industry, a stair-like CIM system architecture with six different views and five development stages is proposed. Some modeling formalisms are introduced and discussion of its suitability for industrial application is included View full abstract»

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  • Intelligent X-ray inspection for quality control of solder joints

    Page(s): 111 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Today automated X-ray inspection is a reliable technique for inline process monitoring and 100% quality control of solder joints. In order to further optimize X-ray inspection there are three key tasks: (1) improvement of X-ray sensors with respect to resolution and contrast; (2) development and integration of three-dimensional (3-D) tomographic reconstruction algorithms in order to separate superposition caused for example by double-sided boards; (3) improvement of image processing and machine learning algorithms in order to provide a detailed quality profile of solder joints necessary for inline process control. In this paper, primarily (1) and (3) are addressed, An inspection system is introduced, which is based on a hierarchical inspection strategy in order to meet speed as well as reliability requirements. Within this concept two-dimensional (2-D)-inspection based on single X-ray projections and 3-D-inspection based on multiple projections are combined. Most solder joints are rapidly evaluated based on single 2-D-projections while in complex situations one or more off-axis projections are required. For example, superpositions caused by double-sided boards are separated by 3-D-reconstruction based on multiple projections from different directions. The advantages and limitations of 2-D and 3-D techniques are discussed within several examples. For 2-D-inspection image preprocessing, classification and defect learning by neural networks are addressed. For 3-D-reconstruction of solder joints digital laminography, model based reconstruction and microtomography are investigated View full abstract»

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  • Yield learning in integrated circuit package assembly

    Page(s): 133 - 141
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    This paper describes a yield learning model for integrated circuit package assembly. The goal was to provide a management tool for making yield projections, resource allocations, understanding operating practices, and performing what-if analyses. The model was developed using a series of case studies of packages entering manufacturing. These studies were a tape carrier package (TCP) at Intel, Chandler, AZ, a ceramic ball grid array (CBGA) and plastic quad flat pack (PQFP) at IBM, Bromont, P.Q., Canada, and a plastic ball grid array (PBGA) at Motorola, Austin, TX. These packages covered a wide range of technologies, including liquid and overmolded encapsulation, wirebond and controlled collapsed chip connection (C4) chip connections, and tape automated bonding (TAB), ceramic, laminate, and leadframe substrates. The factors that affect yield learning rates (e.g., process complexity, production volumes, personnel experience) were identified and a nonlinear spreadsheet-based response surface model was built. The model separates out the underlying chronic yield from excursions due to human error, equipment failure, etc. The model has been shown to accurately predict the yield ramp as a function of the factor values, One of the conclusions of this work is that all of the very dissimilar assembly processes had very similar factors, with very similar factor sensitivities and rankings in terms of how each affected the yield learning rate. In all cases, the most important factors were operator experience, changes in line volume, types of work teams, process complexity, equipment upgrades, and technology type. Since the yield ramp for a new product will hopefully be short, the model must be calibrated for a particular product very quickly. We have developed a graphical interface and tuning procedure so that when the production data is readily available, the tuning procedure takes only a few days View full abstract»

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  • Alternative facility layouts for semiconductor wafer fabrication facilities

    Page(s): 152 - 163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on fab cycle time of a number of alternative layouts or machine dedication policies using a process for manufacturing three-dimensional (3-D) complementary metal-oxide-semiconductor (CMOS) devices as a research vehicle. We examine the performance of the layouts under different levels of machine breakdown, utilization, transfer time between stations, and setup times. Results show that cellular layouts, where machines are dedicated to a limited number of process steps, require more machinery but perform well when setup and transfer times are high and machinery is reliable. As machines become more unreliable, the flexibility of the process layouts becomes a major advantage. An interesting result is that the addition of modest amounts of extra capacity at critical workstations can significantly improve the cycle time performance of a fab View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope