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FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on

Date 19-21 April 1995

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  • Proceedings IEEE Symposium on FPGAs for Custom Computing Machines April 19-21, 1995 Napa Valley, California

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (24 KB)
    Freely Available from IEEE
  • A C++ compiler for FPGA custom execution units synthesis

    Publication Year: 1995, Page(s):173 - 179
    Cited by:  Papers (15)  |  Patents (128)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    If reconfigurable processors are to become widely used, we will need tools to help conventional programmer use them. In particular, a single high-level language should be used to program the whole application; both the part which will become the hardware configuration and the part which remains software. Spyder is a reconfigurable processor with configurable execution units. The C++ language has b... View full abstract»

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  • A FCCM for dataflow (spreadsheet) programs

    Publication Year: 1995, Page(s):2 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    We show how the University of Hawaii's field programmable gate array (FPGA) based custom machine (FCCM) can be used for dataflow programs expressed as spreadsheets. We also describe some nontrivial applications of this dataflow spreadsheet FCCM. These applications include computing the discrete cosine transform and solving dynamic programming problems View full abstract»

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  • The Transmogrifier C hardware description language and compiler for FPGAs

    Publication Year: 1995, Page(s):136 - 144
    Cited by:  Papers (38)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    The Transmogrifier C hardware description language is almost identical to the C programming language, making it attractive to the large community of C-language programmers. This paper describes the semantics of the language and presents a Transmogrifier C compiler that targets the Xilinx 4000 FPGA. The compiler is operational and has produced several working circuits, including a graphics display ... View full abstract»

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  • A dynamic instruction set computer

    Publication Year: 1995, Page(s):99 - 107
    Cited by:  Papers (98)  |  Patents (81)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to impl... View full abstract»

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  • Architectural descriptions for FPGA circuits

    Publication Year: 1995, Page(s):145 - 154
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    FPGA-based synthesis roofs require information about behaviour and architecture to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices View full abstract»

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  • Routability improvement using dynamic interconnect architecture

    Publication Year: 1995, Page(s):61 - 67
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Field programmable gate arrays (FPGAs) have formed the basis for high performance and affordable computing systems. FPGA based logic simulators can emulate complex logic designs at clock speeds of several orders of magnitude faster than even accelerated software simulators, while FPGA based prototyping systems provide great flexibility in rapid prototyping and system verification. However, besides... View full abstract»

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  • Enable++: a second generation FPGA processor

    Publication Year: 1995, Page(s):45 - 53
    Cited by:  Papers (8)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    In the computing community field, programmable processors are going to fill the niche for special purpose computing devices. A typical example is ultra fast pattern recognition in experimental particle physics, a task for which we constructed two years ago (1993), Enable 1, an FPGA processor rather specialized for pattern recognition algorithms in μs domain, but also provided with modest featur... View full abstract»

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  • Issues in wireless video coding using run-time-reconfigurable FPGAs

    Publication Year: 1995, Page(s):85 - 89
    Cited by:  Papers (11)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Video coding has been implemented by using rapid reconfiguration to time-share hardware for several sequential stages. This allows the number of gates to be reduced by a factor proportional to the number of coding stages at the expense of some reconfiguration overhead and the added memory and control needed to implement reconfiguration. The results of this work suggest that run-time reconfiguratio... View full abstract»

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  • Teramac-configurable custom computing

    Publication Year: 1995, Page(s):32 - 38
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    The Teramac configurable hardware system can execute synchronous logic designs of up to one million gates at rates up to 1 megahertz. A fully configured Teramac includes half a gigabyte of RAM and hardware support for large multiported register files. The system has been built from custom FPGA's packaged in large multichip modules (MCMs). A large custom circuit (~1,000,000 gates) may be compiled o... View full abstract»

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  • Acceleration of template-based ray casting for volume visualization using FPGAs

    Publication Year: 1995, Page(s):116 - 124
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Volume visualization is used heavily to view simulated or collected data sets in such applications as medical imaging, computational fluid dynamics, and climate modeling. However, software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for interactive viewing. This paper discusses methods for low-cost, hardware acceleration of volume visualizat... View full abstract»

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  • Reconfigurable real-time signal transport system using custom FPGAs

    Publication Year: 1995, Page(s):68 - 75
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The paper discusses a new architecture for reconfigurable real time signal transport systems that uses FPGAs and describes an experimental system design. The basic architecture of the reconfigurable transport system is proposed based on the requirements for real time signal transport in a typical telecommunication network. The proposed system consists of reconfigurable modules using the custom des... View full abstract»

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  • Quantitative analysis of floating point arithmetic on FPGA based custom computing machines

    Publication Year: 1995, Page(s):155 - 162
    Cited by:  Papers (53)  |  Patents (62)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Many algorithms rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Such computationally intensive algorithms are candidates for acceleration using custom computing machines (CCMs) being tailored for the application. Unfortunately, floating point operators require excessive area (or time) for conventional implementations. Inst... View full abstract»

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  • FPGA-based transformable computers for fast digital signal processing

    Publication Year: 1995, Page(s):197 - 203
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    FPGA-based computing systems provide a feasible and cost-effective platform for implementing fast parallel arithmetic circuits for digital signal and image processing. This paper reports the results obtained from embedding a highly parallel convolution algorithm on an FPGA-based “transformable” computer. Such a computer is intended to serve as a transformable co-processor for a standar... View full abstract»

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  • Rapid prototyping of a RISC architecture for implementation in FPGAs

    Publication Year: 1995, Page(s):190 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    This paper focuses on the use of a rapid prototyping system to develop a simple RISC microprocessor architecture for implementation in field programmable gate arrays. The rapid prototyping system enables engineers and academic professionals to quickly place new concepts into circuitry, thus bypassing the traditional lengthy design time. The system consists of object-based component libraries, crea... View full abstract»

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  • Emulating static faults using a Xilinx based emulator

    Publication Year: 1995, Page(s):110 - 115
    Cited by:  Papers (9)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Fault emulation is a logical extension of current trend of using multiple FPGAs for ASIC emulation. This paper presents the basic infrastructure needed for such an emulator, and discusses the advantages of using a fault emulator as compared to a fault simulator View full abstract»

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  • Run time reconfiguration of FPGA for scanning genomic databases

    Publication Year: 1995, Page(s):90 - 98
    Cited by:  Papers (18)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This paper evaluates the feasibility of reconfiguring an FPGA at run time, and tests its performance using a “Grand Challenge Problem”, the high speed scanning of genomic sequence databases. Algorithm implementation into a XC3090 FPGA is described, and methods proposed for generating a placed Xilinx Netlist File that can be efficiently routed at run time by the Automated Placing and Ro... View full abstract»

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  • Flexible image acquisition using reconfigurable hardware

    Publication Year: 1995, Page(s):125 - 134
    Cited by:  Papers (9)  |  Patents (63)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1456 KB)

    We describe the use of a reconfigurable interface board based on FPGAs in a high bandwidth image acquisition system. We show that a generic interface board can be readily adapted to three quite different CCD image sensors. Our guiding philosophy is to implement the entire interface in programmable logic. We depart from this principle only for electrical adaptation which is performed by relatively ... View full abstract»

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  • Design and implementation of a multicomputer interconnection network using FPGAs

    Publication Year: 1995, Page(s):56 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    We present an experience of using FPGAs in the design and implementation of a multicomputer interconnection network. The switching element, the router and the network controllers are all designed and implemented with FPGAs, and cooperatively form a four port by four port interconnection network. The switching elements were designed with ASIC before, but were not very successful. Advantages of usin... View full abstract»

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  • Common processor element packaging for CHAMP

    Publication Year: 1995, Page(s):39 - 44
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A generic approach for packaging advanced, application specific processors as well as future processing elements into a common JEDEC MCM (multi chip module) footprint is presented and demonstrated. Usage of a common I/O scheme at the MCM level eases future device upgrades, maximizes module reuse and minimizes redesign. An 11 chip, Xilinx XC4025 FPGA (field programmable gate array) based MCM was de... View full abstract»

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  • Architecture of a FPGA-based coprocessor: the PAR-1

    Publication Year: 1995, Page(s):20 - 29
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    The implementation of a FPGA based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural... View full abstract»

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  • Design methodologies for partially reconfigured systems

    Publication Year: 1995, Page(s):78 - 84
    Cited by:  Papers (36)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    Run time reconfiguration (RTR) as an implementation approach that divides an application into a series of sequentially executed stages with each stage implemented as a separate circuit module. Partial RTR extends this approach by partitioning these stages and designing their circuit modules such that they exhibit a high degree of functional and physical commonality. Transitioning between configura... View full abstract»

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  • Implementing a genetic algorithm on a parallel custom computing machine

    Publication Year: 1995, Page(s):180 - 187
    Cited by:  Papers (6)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    Genetic algorithms (GAs) are a currently popular method for nonlinear optimization that can be used to provide a solution for the chip partitioning problem. Unfortunately, GAs usually require prohibitively large computation times on current workstations. This paper demonstrates the utility of the Armstrong III architecture by addressing the computational problems associated with partitioning large... View full abstract»

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  • A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH

    Publication Year: 1995, Page(s):11 - 19
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M×N rectangular mesh of processing elemen... View full abstract»

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  • A declarative approach to incremental custom computing

    Publication Year: 1995, Page(s):164 - 172
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Incremental methods can be used to produce implementations rapidly and to facilitate multi-level design optimisation. This paper describes a declarative framework, based on the language Ruby, that supports incremental design and validation of custom computers. The key elements of the approach include parameterised descriptions, design transformation and data refinement. Several priority queue desi... View full abstract»

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