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Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Date 11-14 Nov. 1991

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Displaying Results 1 - 25 of 127
  • 1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (91CH3026-2)

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    Freely Available from IEEE
  • A cell-replicating approach to minicut-based circuit partitioning

    Page(s): 2 - 5
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    An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described.<> View full abstract»

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  • On clustering for minimum delay/ara

    Page(s): 6 - 9
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    The authors address the problem of clustering a circuit for minimizing its delay, subject to capacity constraints on the clusters. They present an algorithm for combinational circuits and give sufficient conditions under which it is optimum. In addition, they address the problem of minimizing the number of clusters and nodes without increasing the maximum delay found by the algorithm. Finally, they extend the clustering algorithm to minimize the clock cycle of a sequential synchronous circuit.<> View full abstract»

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  • Fast spectral methods for ratio cut partitioning and clustering

    Page(s): 10 - 13
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    The ratio cut partitioning objective function successfully embodies both the traditional min-cut and equipartition goals of partitioning. Fiduccia-Mattheyses style ratio cut heuristics have achieved cost savings averaging over 39% for circuit partitioning and over 50% for hardware simulation applications. The authors show a theoretical correspondence between the optimal ratio cut partition cost and the second smallest eigenvalue of a particular netlist-derived matrix, and present fast Lanczos-based methods for computing heuristic ratio cuts from the eigenvector of this second eigenvalue. Results are better than those of previous methods, e.g. by an average of 17% for the Primary MCNC benchmarks. An efficient clustering method, also based on the second eigenvector, is very successful on the 'difficult' input classes in the CAD (computer-aided design) literature. Extensions and directions for future work are also considered.<> View full abstract»

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  • iMACSIM: a program for multi-level analog circuit simulation

    Page(s): 16 - 19
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    The authors describe a new program called iMACSIM which allows multi-level, mixed-domain simulation of analog integrated circuits. The program performs the simulation of different subcircuits at the behavioral, functional, and electrical levels concurrently. It also enables some parts of the circuit to be simulated using discrete-time algorithms while other portions are processed by continuous-time techniques. Simulations are presented to demonstrate the functionality of the program.<> View full abstract»

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  • A modified envelope-following approach to clocked analog circuit simulation

    Page(s): 20 - 23
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    A modified envelope-following method for simulation of clocked analog circuits is described. The modification makes the envelope-following algorithm more efficient, as unnecessary numerical integration is avoided when computing the envelope of 'quasi-algebraic' components in the solution vector. An automatic method for determining the quasi-algebraic solution components is described, and experimental results are given which demonstrate that this modified method reduces the number of computer clock cycles needed to accurately determine the envelope.<> View full abstract»

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  • An accelerated steady-state method for networks with internally controlled switches

    Page(s): 24 - 27
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    A novel accelerated computer oriented procedure, based on the Newton method, is presented to determine the steady-state response of linear networks with internally and/or externally controlled switches. The Jacobian matrix is computed concurrently with the time-domain response for all possible switching times with the initial conditions. The circuit response may be discontinuous and Dirac impulses are permitted at the switching instants. Several examples show the speed and accuracy of the method.<> View full abstract»

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  • Automatic synthesis of time-stationary controllers for pipelined data paths

    Page(s): 30 - 33
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    The authors present an approach for automatically synthesizing a time-stationary control scheme for a given pipelined data path. They have developed an efficient method of producing a control specification for the data path. A highly optimized FSM (finite state machine) controller implementation is obtained by partitioning so as to minimize the total controller area. The FSM controller is implemented using either PLAs or standard cells. The present approach has been compared to published work on FSM generation and optimization, and the results indicate large savings in total controller area.<> View full abstract»

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  • Layout-area models for high-level synthesis

    Page(s): 34 - 37
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    The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers.<> View full abstract»

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  • Efficient microcode arrangement and controller synthesis for application specific integrated circuits

    Page(s): 38 - 41
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    The authors present a controller synthesizer for application-specific multi-function-unit processors. They describe the data path, control path, and timing scheme of the design. They discuss the optimization problems for this architecture, including the translation of a controller-independent schedule into a microprogram to fit the timing scheme and the address assignment of micro-words. They verify the designs using a function simulator and a timing simulator. The synthesized results are proved to be correct by simulation, and a design with 22 ns for each phase, which corresponds to 23 MHz, has been obtained.<> View full abstract»

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  • A new performance driven placement algorithm

    Page(s): 44 - 47
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    The authors present a novel performance driven placement algorithm. They use a convex programming algorithm to compute a set of upper bounds on the net wire lengths. A modified min-cut algorithm is then used to generate a placement with the objective of minimizing the number of nets, the wire lengths of which exceed their corresponding upper bounds. The situation in which the modified min-cut algorithm fails to generate a placement that satisfies the timing requirements is addressed, and an iterative approach is used to modify the set of upper bounds making use of information from previous placements. The algorithm was implemented in C and tested on eight problems on a Sparc 2 workstation.<> View full abstract»

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  • RITUAL: a performance driven placement algorithm for small cell ICs

    Page(s): 48 - 51
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    An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very good results, as is shown on a set of real examples. The algorithm was tested on the ISCAS set of logic benchmark examples using parameters for 1 mu m CMOS technology. On average , there is a 25% improvement in the wire delay for these examples compared to TimberWolf-5.6 with a small impact on the chip area.<> View full abstract»

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  • Wafer packing for full mask exposure fabrication

    Page(s): 52 - 55
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    The authors formulate and classify the various models of the wafer packing problem for the full mask exposure technique. Since the wafer packing problem is NP-hard, the authors propose a good heuristic for it. Their experiments, on real test data, indicate that this heuristic is very effective as it provides considerable cost reduction when compared with the traditional way of producing chips.<> View full abstract»

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  • A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping

    Page(s): 56 - 59
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    The authors propose a novel floorplanning algorithm which handles a mixture of fixed-shaped and variable-shaped blocks in a chip having a chip aspect ratio within a given range. This algorithm consists of two stages. In the first stage, overlapped blocks in the initial placement obtained using FDR (force directed relaxation) are spread out uniformly over the whole chip area using the ratioed rectangular Voronoi diagram such that each block finds enough space without significant overlap with its neighboring blocks. In the second stage, each block is reshaped or moved by the independent move of each block edge according to the attractive force and repulsive force exerted on it due to the overlap and the dead space, respectively. Experimental results were obtained on the ami33 benchmark circuit with varying conditions on the aspect ratio of blocks and chip. Significant improvement of the chip utilization factor has been obtained compared to previous work.<> View full abstract»

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  • An impulse-response based linear time-complexity algorithm for lossy interconnect simulation

    Page(s): 62 - 65
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    A linear time-complexity algorithm for lossy transmission line simulation within arbitrary nonlinear circuits is presented. The method operates by storing information about the state of the line at dynamically selected internal points and using an analytical formulation based on impulse responses to predict the line's future behavior accurately. Previous approaches using impulse responses possess quadratic-time complexity. The proposed method does not require rational or other approximations of transfer functions to achieve linear time-complexity, nor does it increase the size of the simulator's matrix by more than 2 for each transmission line. Experimental results on industrial circuits indicate that, for equivalent or superior accuracy, the state-based method can be faster for simulations of one or more block or data pulses, with speedups of more than 10 and 50 over the convolution and lumped-RLC methods for the longer simulations.<> View full abstract»

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  • Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations

    Page(s): 66 - 69
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    A method is presented for analysis of VLSI interconnects which contain both lossy coupled transmission lines and nonlinear components. An equivalent time domain macromodel is derived for the lossy coupled transmission line. The macromodel takes the form of a set of ordinary differential equations. The method takes full advantage of the asymptotic waveform evaluation technique which offers two to three orders of magnitude speedup relative to other methods with comparable accuracy. Computational results are presented for two examples: an interconnect circuit which contains lossless transmission lines and nonlinear components and a circuit consisting of two lossy coupled transmission lines.<> View full abstract»

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  • Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation

    Page(s): 70 - 73
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    It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. Specifically, an algorithm to extend SPICE-level simulators to include retardation is presented. Comparisons with analytical equations, the method of moments, and with measurements show good agreement.<> View full abstract»

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  • Evaluating RC-interconnect using moment-matching approximations

    Page(s): 74 - 77
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    The authors describes a relation for specifying the 'optimal' number of lumped RC sections needed to approximate a distributed RC element for an estimated digital-signal bandwidth. The bandwidth approximation also aids in determining the order of the AWE (asymptotic waveform evaluation) approximation for the driving-point and transfer function models. Since moving to arbitrarily high orders of approximation to meet the bandwidth requirements is complicated by moment-matching instability problems, a constrained mapping from moments to dominant time constants is used which guarantees stability for RC interconnect models.<> View full abstract»

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  • The effects of false paths in high-level synthesis

    Page(s): 80 - 83
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    The author discusses the effects of false paths and their consequences in scheduling and allocation during high-level synthesis. False paths through the control-flow graph may occur due to sequences of conditional operations. The detection of false paths during scheduling may result in a smaller number of states, improved operator sharing, and smaller control logic. A heuristic algorithm is presented for the detection and elimination of false paths during path-based scheduling. Results for benchmark examples are presented. For the designs which contained false paths, the percentage of false paths varied from 5% to 83%. A reduction of 15% in the final cell count for one benchmark was obtained by eliminating false paths. Even though the proposed algorithm is heuristic and cannot guarantee the detection of all false paths, it did find all false paths in the small to medium size examples tried. In most cases the condition trees are small, with few data dependencies, which increases the probability of a false path being found by the algorithm.<> View full abstract»

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  • A scheduling algorithm for conditional resource sharing

    Page(s): 84 - 87
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    A novel scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an 'equivalent' one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a schedule for the former is derived. Experimental results demonstrated that such an approach is quite effective. The proposed bottom-up hierarchical approach is computationally more effective than a global nonhierarchical one.<> View full abstract»

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  • Optimizing resource utilization using transformations

    Page(s): 88 - 91
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    A transformational approach aimed at improving the resource utilization in high level synthesis is introduced. The current implementation combines retiming and associativity in a single framework. This combination of transformations results in considerable area improvements, as is amply demonstrated by benchmark examples. A novel learning while searching iterative improvement probabilistic algorithm has been developed and is used to resolve the associated NP-complete combinatorial optimization problem. The effectiveness of the proposed algorithms and the transformations is demonstrated using standard benchmark examples, with the aid of statistical analysis, and through a comparison with estimated minimal bounds. The proposed algorithm has proven to be very effective in reaching the optimal solution as well as in runtime.<> View full abstract»

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  • An algorithm for component selection in performance optimized scheduling

    Page(s): 92 - 95
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    The authors describe a novel algorithm that combines the hardware scheduling and component selection phases for high level synthesis. The algorithm improves on previous work in scheduling, by being able to simultaneously select components from a given library. This enlarges the design space, resulting in better optimized designs. Experimental results on the elliptic filter benchmark demonstrate that exploiting all available components in the library results in designs with smaller area compared to designs produced by scheduling with a single implementation for each component type.<> View full abstract»

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  • Optimal module implementation and its application to transistor placement

    Page(s): 98 - 101
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    The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.<> View full abstract»

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  • Track assignment in the Pathway datapath layout assembler

    Page(s): 102 - 105
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    The authors present a novel dynamic programming algorithm for optimizing the assignment of signals to metal2 tracks, in datapaths. The algorithm is part of the Pathway datapath layout assembler, which was used in the design of the NS32SF641 microprocessor. Using this system, it was possible to produce layout as compact as hand-crafted layout, in a fraction of the time. The proposed algorithm for track assignment minimizes datapath height. The runtime was reduced to an acceptable level, without any significant degradation of the solution, by a heuristic limitation of the solution space. The most serious shortcoming of the track assignment algorithm described is the limitation of the model upon which it is based-that each net occupy only one track in any cell.<> View full abstract»

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  • Flexible block-multiplier generation

    Page(s): 106 - 109
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    A multiplier structure is described which leads to a very efficient implementation in a module generator environment. The structure, a block-multiplier, features a wide range of area-time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully parallel multiplier and many combinations in between. A new concept for the carry-hold circuitry plays a key role. The theoretically derived formulas which describe the relations between the area, timing, and bitwidth of this multiplier structure are verified by a large number of experiments.<> View full abstract»

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