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Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Date 11-14 Nov. 1991

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  • 1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (91CH3026-2)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE
  • A cell-replicating approach to minicut-based circuit partitioning

    Publication Year: 1991, Page(s):2 - 5
    Cited by:  Papers (45)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB)

    An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm... View full abstract»

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  • On clustering for minimum delay/ara

    Publication Year: 1991, Page(s):6 - 9
    Cited by:  Papers (35)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB)

    The authors address the problem of clustering a circuit for minimizing its delay, subject to capacity constraints on the clusters. They present an algorithm for combinational circuits and give sufficient conditions under which it is optimum. In addition, they address the problem of minimizing the number of clusters and nodes without increasing the maximum delay found by the algorithm. Finally, the... View full abstract»

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  • Fast spectral methods for ratio cut partitioning and clustering

    Publication Year: 1991, Page(s):10 - 13
    Cited by:  Papers (71)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB)

    The ratio cut partitioning objective function successfully embodies both the traditional min-cut and equipartition goals of partitioning. Fiduccia-Mattheyses style ratio cut heuristics have achieved cost savings averaging over 39% for circuit partitioning and over 50% for hardware simulation applications. The authors show a theoretical correspondence between the optimal ratio cut partition cost an... View full abstract»

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  • iMACSIM: a program for multi-level analog circuit simulation

    Publication Year: 1991, Page(s):16 - 19
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB)

    The authors describe a new program called iMACSIM which allows multi-level, mixed-domain simulation of analog integrated circuits. The program performs the simulation of different subcircuits at the behavioral, functional, and electrical levels concurrently. It also enables some parts of the circuit to be simulated using discrete-time algorithms while other portions are processed by continuous-tim... View full abstract»

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  • A modified envelope-following approach to clocked analog circuit simulation

    Publication Year: 1991, Page(s):20 - 23
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A modified envelope-following method for simulation of clocked analog circuits is described. The modification makes the envelope-following algorithm more efficient, as unnecessary numerical integration is avoided when computing the envelope of 'quasi-algebraic' components in the solution vector. An automatic method for determining the quasi-algebraic solution components is described, and experimen... View full abstract»

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  • An accelerated steady-state method for networks with internally controlled switches

    Publication Year: 1991, Page(s):24 - 27
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    A novel accelerated computer oriented procedure, based on the Newton method, is presented to determine the steady-state response of linear networks with internally and/or externally controlled switches. The Jacobian matrix is computed concurrently with the time-domain response for all possible switching times with the initial conditions. The circuit response may be discontinuous and Dirac impulses... View full abstract»

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  • Automatic synthesis of time-stationary controllers for pipelined data paths

    Publication Year: 1991, Page(s):30 - 33
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB)

    The authors present an approach for automatically synthesizing a time-stationary control scheme for a given pipelined data path. They have developed an efficient method of producing a control specification for the data path. A highly optimized FSM (finite state machine) controller implementation is obtained by partitioning so as to minimize the total controller area. The FSM controller is implemen... View full abstract»

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  • Layout-area models for high-level synthesis

    Publication Year: 1991, Page(s):34 - 37
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. Th... View full abstract»

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  • Efficient microcode arrangement and controller synthesis for application specific integrated circuits

    Publication Year: 1991, Page(s):38 - 41
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB)

    The authors present a controller synthesizer for application-specific multi-function-unit processors. They describe the data path, control path, and timing scheme of the design. They discuss the optimization problems for this architecture, including the translation of a controller-independent schedule into a microprogram to fit the timing scheme and the address assignment of micro-words. They veri... View full abstract»

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  • A new performance driven placement algorithm

    Publication Year: 1991, Page(s):44 - 47
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB)

    The authors present a novel performance driven placement algorithm. They use a convex programming algorithm to compute a set of upper bounds on the net wire lengths. A modified min-cut algorithm is then used to generate a placement with the objective of minimizing the number of nets, the wire lengths of which exceed their corresponding upper bounds. The situation in which the modified min-cut algo... View full abstract»

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  • RITUAL: a performance driven placement algorithm for small cell ICs

    Publication Year: 1991, Page(s):48 - 51
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very g... View full abstract»

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  • Wafer packing for full mask exposure fabrication

    Publication Year: 1991, Page(s):52 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The authors formulate and classify the various models of the wafer packing problem for the full mask exposure technique. Since the wafer packing problem is NP-hard, the authors propose a good heuristic for it. Their experiments, on real test data, indicate that this heuristic is very effective as it provides considerable cost reduction when compared with the traditional way of producing chips.< View full abstract»

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  • A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping

    Publication Year: 1991, Page(s):56 - 59
    Cited by:  Papers (6)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors propose a novel floorplanning algorithm which handles a mixture of fixed-shaped and variable-shaped blocks in a chip having a chip aspect ratio within a given range. This algorithm consists of two stages. In the first stage, overlapped blocks in the initial placement obtained using FDR (force directed relaxation) are spread out uniformly over the whole chip area using the ratioed recta... View full abstract»

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  • An impulse-response based linear time-complexity algorithm for lossy interconnect simulation

    Publication Year: 1991, Page(s):62 - 65
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB)

    A linear time-complexity algorithm for lossy transmission line simulation within arbitrary nonlinear circuits is presented. The method operates by storing information about the state of the line at dynamically selected internal points and using an analytical formulation based on impulse responses to predict the line's future behavior accurately. Previous approaches using impulse responses possess ... View full abstract»

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  • Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations

    Publication Year: 1991, Page(s):66 - 69
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A method is presented for analysis of VLSI interconnects which contain both lossy coupled transmission lines and nonlinear components. An equivalent time domain macromodel is derived for the lossy coupled transmission line. The macromodel takes the form of a set of ordinary differential equations. The method takes full advantage of the asymptotic waveform evaluation technique which offers two to t... View full abstract»

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  • Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation

    Publication Year: 1991, Page(s):70 - 73
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. ... View full abstract»

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  • Evaluating RC-interconnect using moment-matching approximations

    Publication Year: 1991, Page(s):74 - 77
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB)

    The authors describes a relation for specifying the 'optimal' number of lumped RC sections needed to approximate a distributed RC element for an estimated digital-signal bandwidth. The bandwidth approximation also aids in determining the order of the AWE (asymptotic waveform evaluation) approximation for the driving-point and transfer function models. Since moving to arbitrarily high orders of app... View full abstract»

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  • The effects of false paths in high-level synthesis

    Publication Year: 1991, Page(s):80 - 83
    Cited by:  Papers (23)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB)

    The author discusses the effects of false paths and their consequences in scheduling and allocation during high-level synthesis. False paths through the control-flow graph may occur due to sequences of conditional operations. The detection of false paths during scheduling may result in a smaller number of states, improved operator sharing, and smaller control logic. A heuristic algorithm is presen... View full abstract»

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  • A scheduling algorithm for conditional resource sharing

    Publication Year: 1991, Page(s):84 - 87
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB)

    A novel scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an 'equivalent' one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a schedule for the former is derived. Experiment... View full abstract»

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  • Optimizing resource utilization using transformations

    Publication Year: 1991, Page(s):88 - 91
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    A transformational approach aimed at improving the resource utilization in high level synthesis is introduced. The current implementation combines retiming and associativity in a single framework. This combination of transformations results in considerable area improvements, as is amply demonstrated by benchmark examples. A novel learning while searching iterative improvement probabilistic algorit... View full abstract»

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  • An algorithm for component selection in performance optimized scheduling

    Publication Year: 1991, Page(s):92 - 95
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The authors describe a novel algorithm that combines the hardware scheduling and component selection phases for high level synthesis. The algorithm improves on previous work in scheduling, by being able to simultaneously select components from a given library. This enlarges the design space, resulting in better optimized designs. Experimental results on the elliptic filter benchmark demonstrate th... View full abstract»

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  • Optimal module implementation and its application to transistor placement

    Publication Year: 1991, Page(s):98 - 101
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB)

    The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement ... View full abstract»

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  • Track assignment in the Pathway datapath layout assembler

    Publication Year: 1991, Page(s):102 - 105
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB)

    The authors present a novel dynamic programming algorithm for optimizing the assignment of signals to metal2 tracks, in datapaths. The algorithm is part of the Pathway datapath layout assembler, which was used in the design of the NS32SF641 microprocessor. Using this system, it was possible to produce layout as compact as hand-crafted layout, in a fraction of the time. The proposed algorithm for t... View full abstract»

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  • Flexible block-multiplier generation

    Publication Year: 1991, Page(s):106 - 109
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A multiplier structure is described which leads to a very efficient implementation in a module generator environment. The structure, a block-multiplier, features a wide range of area-time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully parallel multiplier and many combinations in between. A new concept for the carry-hold circuitry plays a ke... View full abstract»

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