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Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on

Date 26-29 May 1991

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  • Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic (Cat. No.91CH3009-8)

    Publication Year: 1991
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    Freely Available from IEEE
  • Design of interconnection-free biomolecular computing system

    Publication Year: 1991 , Page(s): 173 - 180
    Cited by:  Papers (10)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (448 KB)  

    A systematic design method for an interconnection-free biomolecular computing system based on parallel distribution of logical information represented by varieties of molecules and parallel selection using specificity of enzymes is presented. A model of a biomolecular switching device is introduced as a universal building block, and the systematic synthesis of biodevice networks is discussed using... View full abstract»

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  • A formal semantical approach to fuzzy logic

    Publication Year: 1991 , Page(s): 72 - 79
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (520 KB)  

    A formal semantical approach to fuzzy logic is given, formalizing it as a family of institutions. In this frame the soundness of the most-used inference patterns in fuzzy logic is proved. The authors believe that this formalization of fuzzy logic can be used to prove the soundness of other inference patterns such as the principle of resolution or the chaining inference rule View full abstract»

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  • On the complexity of enumerations for multiple-valued Kleenean functions and unate functions

    Publication Year: 1991 , Page(s): 55 - 62
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (520 KB)  

    Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this pap... View full abstract»

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  • Post relation algebras and their proof system

    Publication Year: 1991 , Page(s): 298 - 305
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (488 KB)  

    A class of nonclassical relation algebras that correspond to Post logics is introduced and a method of algebraization of those logics is proposed. Relational semantics for Post logics leads to a Rasiowa-Sikorski style proof system for Post logics. A logic LPo intended to provide a formal tool to verify equations in Post relation algebras is defined. Two kinds of rules for the relational logic are ... View full abstract»

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  • A bi-directional current-mode CMOS multiple valued logic memory circuit

    Publication Year: 1991 , Page(s): 196 - 202
    Cited by:  Papers (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (580 KB)  

    A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2-μm polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using log... View full abstract»

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  • A note on minimal partial clones

    Publication Year: 1991 , Page(s): 262 - 267
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (292 KB)  

    Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice LpA of all partial clones are either the atoms of LoA or are generated by partial projections, defined on a totally reflexive and totally symmetric domain View full abstract»

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  • Topological soft algebra for the S5-modal fuzzy logic

    Publication Year: 1991 , Page(s): 80 - 84
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (304 KB)  

    A topological fuzzy algebra is defined as a special case of topological soft algebra. This algebra system is obtained from the S5-modal fuzzy logic, which had been previously proposed. The soundness and completeness of this axiomatic system are proved View full abstract»

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  • On the synthesis of 4-valued current mode CMOS circuits

    Publication Year: 1991 , Page(s): 147 - 155
    Cited by:  Papers (17)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (524 KB)  

    Synthesis of 4-valued current mode CMOS circuits is considered. A method for deriving low-cost realizations of single-variable functions, based on the incremental cost approach, is presented. A technique for synthesis of 2-variable functions, incorporating a modified direct cover approach, is considered. The results show that this technique can be used effectively in conjunction with the multiplex... View full abstract»

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  • Reasoning about digital systems

    Publication Year: 1991 , Page(s): 2 - 6
    Request Permissions | Click to expandAbstract | PDF file iconPDF (336 KB)  

    The uses of automated reasoning in the process of the design and analysis of digital systems are explored. A discussion of reasoning and automated reasoning is presented. Several examples of successful application of this technology are described, and current research is discussed. The author mentions AURA (automated reasoning assistant), ITP (interactive theorem prover) and flow nets View full abstract»

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  • On the maximum size of the terms in the realization of symmetric functions

    Publication Year: 1991 , Page(s): 110 - 117
    Request Permissions | Click to expandAbstract | PDF file iconPDF (408 KB)  

    The symmetric functions of m-valued logic have a sum-product (i.e. max-min) representation whose terms are sums of fundamental symmetric functions (FSFs). These sums may be simplified if they contain adjacent SFSs. This naturally leads to the combinatorial problem of determining the maximum size M(m,n) of adjacent-free sets of n-variable SFSs. J.C. Muzi... View full abstract»

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  • An investigation into the implementation costs of residue and high radix arithmetic

    Publication Year: 1991 , Page(s): 364 - 371
    Request Permissions | Click to expandAbstract | PDF file iconPDF (528 KB)  

    Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that paralle... View full abstract»

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  • Theory and uses of Post algebras of order ω+ω*. II

    Publication Year: 1991 , Page(s): 248 - 254
    Request Permissions | Click to expandAbstract | PDF file iconPDF (408 KB)  

    For pt.I see Proc. 20th International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order ω+ω whose chain of constants is isomorphic with (0⩽1⩽2⩽. . .⩽-3⩽-2⩽-1). The algebras are a generalization of Post algebras of finite order, and... View full abstract»

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  • The abnormality predicate

    Publication Year: 1991 , Page(s): 218 - 224
    Request Permissions | Click to expandAbstract | PDF file iconPDF (592 KB)  

    The author has suggested earlier that the various nonmonotonic reasoning formalisms are converging towards probability. Here, he discusses the idea of randomness: using a definition by Kyburg as a benchmark, he describes how it appears in various nonmonotonic reasoning formalisms, in particular, circumscription. It is argued that behind the complexity of circumscription lie the simple notions of r... View full abstract»

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  • The design of current mode CMOS multiple-valued circuits

    Publication Year: 1991 , Page(s): 130 - 138
    Cited by:  Papers (15)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (672 KB)  

    A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizati... View full abstract»

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  • Proposed CMOS VLSI implementation of an electronic neuron using multivalued signal processing

    Publication Year: 1991 , Page(s): 203 - 209
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (456 KB)  

    Several approaches to the hardware implementation of an electronic neuron are presented and compared. A hardware implementation of a neuron that uses a voltage-controlled input weights is introduced, and its simulated performance presented. This electronic neuron circuit is ideal for CMOS VLSI implementations of neural networks, because it merges, the advantages of analog and digital techniques. I... View full abstract»

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  • Multiple-valued generalized Reed-Muller forms

    Publication Year: 1991 , Page(s): 40 - 48
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (608 KB)  

    The concept of canonical multiple-valued input generalized Reed-Muller forms (MIGRM), a direct extension of the well-known generalized Reed-Muller (GRM) forms for the logic with multiple-valued inputs, is introduced. Code normalization of single multiple-valued literals (MV-literal) to perform a final transformation is developed. The code normalization is used to make the transformation of the com... View full abstract»

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  • Recognition of circle form using fuzzy sequential system

    Publication Year: 1991 , Page(s): 85 - 92
    Cited by:  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (348 KB)  

    An application of the synchronous fuzzy sequential system to pattern recognition in which fuzzy propositions are used to represent various sizes of circles is presented. The advantages of the proposed system include the small amount of required memory elements as well as a fast recognition speed caused by the sequential procedure. Furthermore, an easy realization of the system with electronic devi... View full abstract»

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  • VLSI fuzzy chip and inference accelerator board systems

    Publication Year: 1991 , Page(s): 120 - 127
    Cited by:  Papers (19)  |  Patents (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (480 KB)  

    The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists... View full abstract»

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  • An equational logic approach for mapping/multiple-valued rule-based expert systems into hardware specification rules

    Publication Year: 1991 , Page(s): 308 - 315
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (544 KB)  

    This research extends techniques for mapping rule-based expert systems into VLSI hardware design notation and provides design procedures for performing the mapping from expert system' production rules to hardware specification rules. Results from this work enhance the applicability of the rule-based expert system approach to a larger class of real-time and control applications View full abstract»

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  • Testability analysis of CMOS ternary circuits

    Publication Year: 1991 , Page(s): 158 - 165
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (388 KB)  

    The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circui... View full abstract»

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  • Design of a set logic network based on frequency multiplexing and its applications to image processing

    Publication Year: 1991 , Page(s): 8 - 15
    Cited by:  Papers (12)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (448 KB)  

    An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-select... View full abstract»

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  • On the implementation of set-valued non-Boolean switching functions

    Publication Year: 1991 , Page(s): 166 - 172
    Cited by:  Papers (12)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (316 KB)  

    Biological computing based on the interactions between engines and substrate is addressed. An upper bound is given on the complexity of the bio-circuits that realize set-valued functions. This bound is based on an equivalence attached to a set-valued function such that the classes of the quotient set of the definition domain with respect to such an equivalence coincide with the maximal sets on whi... View full abstract»

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  • Quarternary cyclic AN codes for burst error correction

    Publication Year: 1991 , Page(s): 102 - 109
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    A theoretical approach to quarternary cyclic AN codes for burst error correction is provided. After describing quarternary cyclic AN codes and arithmetic bursts, the authors discuss the arithmetic burst correcting ability of codes generated by A=(4c±1)A2 and show a decoding method for such codes View full abstract»

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  • Application of multi-zero artificial neural network to the design of an m-valued digital multiplier

    Publication Year: 1991 , Page(s): 32 - 37
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (348 KB)  

    An M-ary digital multiplier using artificial multi-zero neural networks and elementary analog arithmetic units has been derived. This multiplier should be accurate because its main arithmetic process is digital, while the speed should be very high because it is a free-running, parallel, and M-ary operation. The multi-zero neural network is a feedback artificial neural system cons... View full abstract»

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