[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

26-29 May 1991

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  • Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic (Cat. No.91CH3009-8)

    Publication Year: 1991
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    Freely Available from IEEE
  • Proposed CMOS VLSI implementation of an electronic neuron using multivalued signal processing

    Publication Year: 1991, Page(s):203 - 209
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    Several approaches to the hardware implementation of an electronic neuron are presented and compared. A hardware implementation of a neuron that uses a voltage-controlled input weights is introduced, and its simulated performance presented. This electronic neuron circuit is ideal for CMOS VLSI implementations of neural networks, because it merges, the advantages of analog and digital techniques. I... View full abstract»

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  • Theory and uses of Post algebras of order ω+ω*. II

    Publication Year: 1991, Page(s):248 - 254
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    For pt.I see Proc. 20th International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order ω+ω whose chain of constants is isomorphic with (0⩽1⩽2⩽. . .⩽-3⩽-2⩽-1). The algebras are a generalization of Post algebras of finite order, and... View full abstract»

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  • An algorithm for the solution of multi-valued logic programming

    Publication Year: 1991, Page(s):322 - 327
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    Logic programming using the Horn clause in the field of artificial intelligence is considered. It has been previously reported that the solution of multivalued logic programming with many truth values is obtained by solving the multivalued logic formula expressed in the Postian algebra. In this paper, expanding the idea that unnecessary search can be avoided by using an indeterminate value, an alg... View full abstract»

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  • Synthesis of current-mode pass transistor networks

    Publication Year: 1991, Page(s):139 - 146
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    The basic properties of the MOS current-mode circuits are considered, and the network synthesis for realization of unary multivalued functions is discussed. The main concern is the minimization of hardware realization. Functional blocks to compose a current-mode circuit from the viewpoint of a design cost are considered. Some decomposition methods of unary functions are proposed and their circuit ... View full abstract»

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  • A bi-directional current-mode CMOS multiple valued logic memory circuit

    Publication Year: 1991, Page(s):196 - 202
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB)

    A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2-μm polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using log... View full abstract»

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  • Optimization of fuzzy logic implementation

    Publication Year: 1991, Page(s):348 - 355
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (728 KB)

    An architecture for implementing fuzzy-logic inference, together with the tools to optimally synthesize fuzzy logic circuits under this architecture, is proposed. The algorithms for finding the parameters for this architecture are presented. The author discusses how, computer-aided-design tools can be built to help fuzzy logic designers to explore the design space. In particular, the design proces... View full abstract»

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  • Uniform notation of tableau rules for multiple-valued logics

    Publication Year: 1991, Page(s):238 - 245
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    A framework for axiomatizing arbitrary finitely valued logics with minimal overhead compared to the classical case is presented. The main idea is to work with tableaux using generalized signs, which makes it possible to express complex assertions regarding the possible truth values of a formula. The class of regular logical connectives which, together with a suitable restriction on queries (i.e. a... View full abstract»

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  • A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

    Publication Year: 1991, Page(s):16 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS trans... View full abstract»

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  • A general-purpose inference processor for real-time intelligent controllers using systolic arrays

    Publication Year: 1991, Page(s):316 - 321
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    A systolic array implementation of a general-purpose inference processor is presented. The proposed processor can be used as a building block in the inference engine of an expert system or in a rule-based controller where computational speed is of importance. After a brief theoretical review of the approximate-reasoning, a VLSI implementation exploiting the parallelism in that routine is presented... View full abstract»

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  • The design of current mode CMOS multiple-valued circuits

    Publication Year: 1991, Page(s):130 - 138
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (672 KB)

    A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizati... View full abstract»

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  • Multiple peak resonant tunneling diode for multi-valued memory

    Publication Year: 1991, Page(s):190 - 195
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    Several designs for a high-speed static random access multivalued memory using the folding characteristics of multiple peak resonant tunneling diodes (RTDs) are presented. The different designs are described and studied by comparing their power consumption under different conditions of device parameters and the switching speed. It is shown that the proposed memory cell using a pair of multiple-pea... View full abstract»

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  • The abnormality predicate

    Publication Year: 1991, Page(s):218 - 224
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (592 KB)

    The author has suggested earlier that the various nonmonotonic reasoning formalisms are converging towards probability. Here, he discusses the idea of randomness: using a definition by Kyburg as a benchmark, he describes how it appears in various nonmonotonic reasoning formalisms, in particular, circumscription. It is argued that behind the complexity of circumscription lie the simple notions of r... View full abstract»

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  • A note on minimal partial clones

    Publication Year: 1991, Page(s):262 - 267
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice LpA of all partial clones are either the atoms of LoA or are generated by partial projections, defined on a totally reflexive and totally symmetric domain View full abstract»

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  • Spectral techniques for multiple valued logic circuits

    Publication Year: 1991, Page(s):340 - 346
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    Canonical representation of multiple valued logic (MVL) functions in any polarity k, k ∈ {0, 1,. . .,pn -1}, where p is the radix and n denotes the number of variables in a function, was previously presented. The coefficients in a canonical representation are called the spectral coefficients. It is shown that for some MVL functions real... View full abstract»

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  • Testability analysis of CMOS ternary circuits

    Publication Year: 1991, Page(s):158 - 165
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circui... View full abstract»

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  • An investigation into the implementation costs of residue and high radix arithmetic

    Publication Year: 1991, Page(s):364 - 371
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (528 KB)

    Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that paralle... View full abstract»

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  • Improving tableau deductions in multiple-valued logics

    Publication Year: 1991, Page(s):230 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    Path dissolution is an efficient generalization of the method of analytic tableaux. Both methods feature (in the propositional case) strong completeness, the lack of reliance upon conjunctive normal form (CNF), and the ability to produce a list of essential models (satisfying interpretations) of a formula. Dissolution can speed up every step in a tableau deduction in classical logic. The authors c... View full abstract»

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  • On the complexity of enumerations for multiple-valued Kleenean functions and unate functions

    Publication Year: 1991, Page(s):55 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this pap... View full abstract»

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  • Design of a set logic network based on frequency multiplexing and its applications to image processing

    Publication Year: 1991, Page(s):8 - 15
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (448 KB)

    An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-select... View full abstract»

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  • An equational logic approach for mapping/multiple-valued rule-based expert systems into hardware specification rules

    Publication Year: 1991, Page(s):308 - 315
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    This research extends techniques for mapping rule-based expert systems into VLSI hardware design notation and provides design procedures for performing the mapping from expert system' production rules to hardware specification rules. Results from this work enhance the applicability of the rule-based expert system approach to a larger class of real-time and control applications View full abstract»

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  • VLSI fuzzy chip and inference accelerator board systems

    Publication Year: 1991, Page(s):120 - 127
    Cited by:  Papers (19)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists... View full abstract»

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  • Multiple-valued generalized Reed-Muller forms

    Publication Year: 1991, Page(s):40 - 48
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    The concept of canonical multiple-valued input generalized Reed-Muller forms (MIGRM), a direct extension of the well-known generalized Reed-Muller (GRM) forms for the logic with multiple-valued inputs, is introduced. Code normalization of single multiple-valued literals (MV-literal) to perform a final transformation is developed. The code normalization is used to make the transformation of the com... View full abstract»

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  • Parallel algorithms for minimizing multiple-valued programmable logic arrays

    Publication Year: 1991, Page(s):287 - 295
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB)

    Two versions of a minimization algorithm for multiple-valued programmable logic arrays for shared and distributed memory multiprocessor systems are presented. Both algorithms exploit the considerable parallelism available in the minimization problem. Discussed are communication, synchronization, and load balancing issues under the two machine models. Limited access and the cost of the required com... View full abstract»

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  • A decade of spectral techniques

    Publication Year: 1991, Page(s):182 - 188
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (396 KB)

    Some of the significant achievements of the last ten years in the area of spectral techniques are summarized. The name spectral techniques denotes developments in abstract harmonic analysis oriented to possible applications in switching theory and logic design, fault detection, coding theory, and pattern analysis. A review of pattern analysis, with emphasis on the study of self-similarity of patte... View full abstract»

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