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Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on

Date 26-29 May 1991

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  • Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic (Cat. No.91CH3009-8)

    Publication Year: 1991
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  • Spectral techniques for multiple valued logic circuits

    Publication Year: 1991, Page(s):340 - 346
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Canonical representation of multiple valued logic (MVL) functions in any polarity k, k ∈ {0, 1,. . .,pn -1}, where p is the radix and n denotes the number of variables in a function, was previously presented. The coefficients in a canonical representation are called the spectral coefficients. It is shown that for some MVL functions real... View full abstract»

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  • VLSI fuzzy chip and inference accelerator board systems

    Publication Year: 1991, Page(s):120 - 127
    Cited by:  Papers (19)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists... View full abstract»

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  • A non-commutative multiple-valued logic

    Publication Year: 1991, Page(s):49 - 54
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A set of operations which can be used to design n-valued switching functions is given. These give rise to a class of algebras which are left-handed skew lattices together with dual implication operation. Such algebras form a decidable discriminator variety, and hence possess a well-behaved structure theory and satisfy many identities. Algorithms for the design and optimization of switchin... View full abstract»

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  • Theory and uses of Post algebras of order ω+ω*. II

    Publication Year: 1991, Page(s):248 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    For pt.I see Proc. 20th International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order ω+ω whose chain of constants is isomorphic with (0⩽1⩽2⩽. . .⩽-3⩽-2⩽-1). The algebras are a generalization of Post algebras of finite order, and... View full abstract»

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  • On the complexity of enumerations for multiple-valued Kleenean functions and unate functions

    Publication Year: 1991, Page(s):55 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this pap... View full abstract»

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  • Reasoning about digital systems

    Publication Year: 1991, Page(s):2 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The uses of automated reasoning in the process of the design and analysis of digital systems are explored. A discussion of reasoning and automated reasoning is presented. Several examples of successful application of this technology are described, and current research is discussed. The author mentions AURA (automated reasoning assistant), ITP (interactive theorem prover) and flow nets View full abstract»

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  • On the maximum size of the terms in the realization of symmetric functions

    Publication Year: 1991, Page(s):110 - 117
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The symmetric functions of m-valued logic have a sum-product (i.e. max-min) representation whose terms are sums of fundamental symmetric functions (FSFs). These sums may be simplified if they contain adjacent SFSs. This naturally leads to the combinatorial problem of determining the maximum size M(m,n) of adjacent-free sets of n-variable SFSs. J.C. Muzi... View full abstract»

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  • Improving tableau deductions in multiple-valued logics

    Publication Year: 1991, Page(s):230 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    Path dissolution is an efficient generalization of the method of analytic tableaux. Both methods feature (in the propositional case) strong completeness, the lack of reliance upon conjunctive normal form (CNF), and the ability to produce a list of essential models (satisfying interpretations) of a formula. Dissolution can speed up every step in a tableau deduction in classical logic. The authors c... View full abstract»

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  • A decade of spectral techniques

    Publication Year: 1991, Page(s):182 - 188
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Some of the significant achievements of the last ten years in the area of spectral techniques are summarized. The name spectral techniques denotes developments in abstract harmonic analysis oriented to possible applications in switching theory and logic design, fault detection, coding theory, and pattern analysis. A review of pattern analysis, with emphasis on the study of self-similarity of patte... View full abstract»

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  • NPN calculi: a family of three strict Q-algebras

    Publication Year: 1991, Page(s):255 - 261
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    NPN (negative-positive-neutral) calculi, a family of three mathematical structures are introduced for qualitative reasoning. NPN crisp logic extends the usual 4-valued model {+, -, 0, ?) to a 6-valued model {1, 0, +1, (-1, 0), (0, +1), (-1, +1)} and adds one more level of specification to the usual model. NPN fuzzy logic extends the NPN model to the space {∀(x,y)|... View full abstract»

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  • Design of a set logic network based on frequency multiplexing and its applications to image processing

    Publication Year: 1991, Page(s):8 - 15
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-select... View full abstract»

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  • On the implementation of set-valued non-Boolean switching functions

    Publication Year: 1991, Page(s):166 - 172
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Biological computing based on the interactions between engines and substrate is addressed. An upper bound is given on the complexity of the bio-circuits that realize set-valued functions. This bound is based on an equivalence attached to a set-valued function such that the classes of the quotient set of the definition domain with respect to such an equivalence coincide with the maximal sets on whi... View full abstract»

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  • Proposed CMOS VLSI implementation of an electronic neuron using multivalued signal processing

    Publication Year: 1991, Page(s):203 - 209
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Several approaches to the hardware implementation of an electronic neuron are presented and compared. A hardware implementation of a neuron that uses a voltage-controlled input weights is introduced, and its simulated performance presented. This electronic neuron circuit is ideal for CMOS VLSI implementations of neural networks, because it merges, the advantages of analog and digital techniques. I... View full abstract»

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  • Quarternary cyclic AN codes for burst error correction

    Publication Year: 1991, Page(s):102 - 109
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A theoretical approach to quarternary cyclic AN codes for burst error correction is provided. After describing quarternary cyclic AN codes and arithmetic bursts, the authors discuss the arithmetic burst correcting ability of codes generated by A=(4c±1)A2 and show a decoding method for such codes View full abstract»

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  • Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations

    Publication Year: 1991, Page(s):330 - 339
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set {0, 1, 2, 3}. The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a ti... View full abstract»

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  • A general-purpose inference processor for real-time intelligent controllers using systolic arrays

    Publication Year: 1991, Page(s):316 - 321
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A systolic array implementation of a general-purpose inference processor is presented. The proposed processor can be used as a building block in the inference engine of an expert system or in a rule-based controller where computational speed is of importance. After a brief theoretical review of the approximate-reasoning, a VLSI implementation exploiting the parallelism in that routine is presented... View full abstract»

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  • Post relation algebras and their proof system

    Publication Year: 1991, Page(s):298 - 305
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    A class of nonclassical relation algebras that correspond to Post logics is introduced and a method of algebraization of those logics is proposed. Relational semantics for Post logics leads to a Rasiowa-Sikorski style proof system for Post logics. A logic LPo intended to provide a formal tool to verify equations in Post relation algebras is defined. Two kinds of rules for the relational logic are ... View full abstract»

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  • Multiple peak resonant tunneling diode for multi-valued memory

    Publication Year: 1991, Page(s):190 - 195
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Several designs for a high-speed static random access multivalued memory using the folding characteristics of multiple peak resonant tunneling diodes (RTDs) are presented. The different designs are described and studied by comparing their power consumption under different conditions of device parameters and the switching speed. It is shown that the proposed memory cell using a pair of multiple-pea... View full abstract»

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  • A fuzzy logic function generator (FLUG) implemented with current mode CMOS circuits

    Publication Year: 1991, Page(s):356 - 362
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A fuzzy logic function generator (FLUG) based on the singleton fuzzy control algorithm is proposed. The normalizing operation can be removed from the original algorithm by introducing a new t-norm operation. The FLUG can be simply implemented with the current mode CMOS circuits, because the dividers are not needed. Further, to solve the problem in the current mode with respect to the rest... View full abstract»

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  • A note on minimal partial clones

    Publication Year: 1991, Page(s):262 - 267
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice LpA of all partial clones are either the atoms of LoA or are generated by partial projections, defined on a totally reflexive and totally symmetric domain View full abstract»

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  • A formal semantical approach to fuzzy logic

    Publication Year: 1991, Page(s):72 - 79
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A formal semantical approach to fuzzy logic is given, formalizing it as a family of institutions. In this frame the soundness of the most-used inference patterns in fuzzy logic is proved. The authors believe that this formalization of fuzzy logic can be used to prove the soundness of other inference patterns such as the principle of resolution or the chaining inference rule View full abstract»

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  • The design of current mode CMOS multiple-valued circuits

    Publication Year: 1991, Page(s):130 - 138
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizati... View full abstract»

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  • Testability analysis of CMOS ternary circuits

    Publication Year: 1991, Page(s):158 - 165
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circui... View full abstract»

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  • Optimization of fuzzy logic implementation

    Publication Year: 1991, Page(s):348 - 355
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    An architecture for implementing fuzzy-logic inference, together with the tools to optimally synthesize fuzzy logic circuits under this architecture, is proposed. The algorithms for finding the parameters for this architecture are presented. The author discusses how, computer-aided-design tools can be built to help fuzzy logic designers to explore the design space. In particular, the design proces... View full abstract»

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