[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications

13-16 May 1991

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Displaying Results 1 - 25 of 168
  • Data networking trends

    Publication Year: 1991, Page(s):1 - 8
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (278 KB)

    Summary form only given. In addition to the change from mainframe-dominated point-to-point networks, wide-area technology now offers a variety of transmission speeds and accommodates a variety of standards, all vendor independent. Technology trends and increased activity in the standards bodies allow the customer to select technology that can be offered from both private and public network provide... View full abstract»

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  • High level software engineering environments in high level synthesis of ASICs

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (96 KB)

    Summary form only given. The use of a software engineering tool, the programming environment generator called CENTAUR, in the high-level synthesis of integrated circuits is described. How CENTAUR can be used in the IC design process is discussed. Also presented is how the VHDL (VHSIC hardware description language) standard fits into CENTAUR and, as an example, how the Ada genericity could be inclu... View full abstract»

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  • Proceedings. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference CompEuro '91 (Cat. No.91CH3001-5)

    Publication Year: 1991
    Request permission for commercial reuse | |PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • Integrating knowledge-based systems and neural networks for navigational tasks

    Publication Year: 1991, Page(s):652 - 656
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    The MONSTER project (Models of Neural-Symbolic Techniques for Extendable Robots) is presented. The project focuses on inherent problems in developing an adaptive system for navigational tasks. The proposed architecture is based on both explicit (symbolic) knowledge of the environment and implicit knowledge encoded in the connections of neural networks. An overview is presented of the current state... View full abstract»

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  • A neurointelligence: cerebral asymmetry and neurocomputing

    Publication Year: 1991, Page(s):647 - 651
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    The development of new types of neurocomputers requires using the `gestalt' form representation of input patterns as well as a deeper knowledge of the specifics of the functioning of the brain (memory, understanding of multisignificance images, cerebral asymmetry mechanisms, etc.). The way in which the formal representation functions in the right hemisphere for understanding images (pictures) and ... View full abstract»

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  • Fast pipelined multipliers for bit-serial complex numbers

    Publication Year: 1991, Page(s):821 - 825
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture View full abstract»

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  • On-line signature learning and checking: experimental evaluation

    Publication Year: 1991, Page(s):642 - 646
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (576 KB)

    An experimental evaluation of a signature monitoring technique called online signature learning and checking (OSLC) is presented. The experiments are based on physical fault injection on the system bus of a prototype. A set of 12000 faults was inserted in the system. The duration of the faults, the line affected, and the point in the program where the faults were injected were chosen at random. An... View full abstract»

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  • A high speed error correcting converter for residue number processing

    Publication Year: 1991, Page(s):816 - 820
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    A novel pipelined systolic design for residue error correction using the Chinese remainder theorem (CRT) is described. This design has a higher throughput compared to previous methods and minimum time latency. The design also has overflow detection and self-diagnosing abilities View full abstract»

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  • Fault detection and fault tolerance for the associative random access memory (ARAM)

    Publication Year: 1991, Page(s):690 - 694
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    Problems of fault detection and fault tolerance for an innovative special associative memory architecture, the associative RAM (ARAM), are considered. Additional components to solve these problems are presented. The resulting reliability improvement of the ARAM is discussed. The extended architecture has been realized as a prototype by a VLSI implementation View full abstract»

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  • Improving fault-tolerance in distributed systems: The saturation approach

    Publication Year: 1991, Page(s):634 - 641
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (936 KB)

    Work done for the research project SATURNE is summarized. The technique developed in this project maximizes the redundancy level of tasks and tolerates hardware faults by majority voting in the context of a pool of interconnected processors (network of workstations, multiprocessor machines, etc.). The technique, called saturation, is presented and briefly compared with similar approaches. The dist... View full abstract»

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  • Processor allocation in parallel systems

    Publication Year: 1991, Page(s):133 - 137
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    A methodology for the evaluation of the effectiveness of processor allocation in parallel system is introduced. In the methodology, different allocation policies are compared, and an estimate of processor utilization is obtained. The estimate, obtained prior to executing the program itself, is very important in many respects. For example, a programmer who has a rough description of the program he ... View full abstract»

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  • A graphical tool for protocol design with Estelle

    Publication Year: 1991, Page(s):552 - 556
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    A new tool is described which enables the user to develop a protocol specification in the formal description technique. Estelle by working on graphical representations of Estelle constructs and objects. Only some parts of the specifications are handled in textual form (e.g., Pascal code), since they are of an intrinsically textual nature. The problems of combining graphical abstractions with pure ... View full abstract»

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  • A real-time message-passing synchronization for multi-SIMD massively parallel machine

    Publication Year: 1991, Page(s):176 - 179
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (256 KB)

    A real-time message passing synchronization method for a multi-SIMD architecture is introduced, and a concrete implementation in SPHINX-a multi-SIMD pyramid vision computer-is given. This synchronization mechanism can give both efficient and flexible solutions to the multi-SIMD control problem. Two algorithms are used in the simulation. One is a pyramid sorting algorithm. The other is a histogramm... View full abstract»

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  • Packaging of advanced computer components

    Publication Year: 1991, Page(s):805 - 810
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB)

    The main constraints and requirements on packaging and the techniques and technologies applied to meet the needs are presented. This includes the semiconductor devices assembly as well as the package and module construction in some of the current computers View full abstract»

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  • An approach for online repair and yield enhancement of VLSI/WSI redundant memories

    Publication Year: 1991, Page(s):685 - 689
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty ... View full abstract»

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  • Parallel structures for efficient and reliable general purpose computing

    Publication Year: 1991, Page(s):472 - 479
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (552 KB)

    A general-purpose parallel processing structure has been prototyped facilitating an any-to-any intercommunication network for interconnecting up to 64 general-purpose processors and their memories, based on a high-speed crosspoint switch. This prototype is used for real problem processing as well as for further application software development. A short description is presented of the hardware and ... View full abstract»

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  • Research activities at CEFRIEL, a university-industry cooperation example

    Publication Year: 1991, Page(s):599 - 602
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (204 KB)

    A description is presented of CEFRIEL, an initiative by academic institutions and industry to promote research and educational activities in the field of information technology. After a general presentation of the structure and the organization of the center, some projects in the area of CAD for VLSI are briefly discussed View full abstract»

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  • The deflection network: a reliable high speed packet network for computer communication

    Publication Year: 1991, Page(s):84 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    The performance of deflection networks (extension of Manhattan Street network) under bursty traffic has been analyzed assuming the use of a preference routing algorithm. The throughput performance under these conditions has proven to be almost independent from the burstiness of the traffic. Packets of a single burst are often received in the wrong alignment. Analyses simulating the generation of b... View full abstract»

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  • Object-oriented approach to software development, a walk through a number of topics

    Publication Year: 1991, Page(s):626 - 633
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    A number of important software development topics in which the object-oriented approach plays a central role and has caused a significant step forward are examined. An attempt is made to describe these topics in the form of dualities and contrasts. The aim is to present a view of software development which is different from the traditional one, in which the development process has been partitioned... View full abstract»

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  • Load balancing in distributed memory multiprocessors

    Publication Year: 1991, Page(s):131 - 132
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (212 KB)

    It is argued that multiuser distributed memory multiprocessors with dynamic mapping of the application onto the hardware structure are needed to make available the advantages of this type of architecture to a wider user community. It is shown, based on an abstract model, that such architectures may be used efficiently. It is also shown that future developments in interconnection hardware will allo... View full abstract»

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  • Fault tolerance in neural networks: theoretical analysis and simulation results

    Publication Year: 1991, Page(s):429 - 436
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (640 KB)

    Work is continuing on the intrinsic capacity of survival of fault characterizing neural nets per se. The authors deal with this theme, considering in particular multilayered feedforward nets. The study is performed on the abstract neural graphs, thus involving errors rather than faults. After an initial analysis of the error model, the effects of errors are mathematically derived and the condition... View full abstract»

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  • Neural networks simulation with array processors

    Publication Year: 1991, Page(s):547 - 551
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    A strategy is presented for implementing neural models, based on an array of interconnected processing elements. A proprietary VLSI parallel processing chip (the array chip ACIIM) is briefly described. It incorporates 16 16-bit processors, 8 kBytes of local memory, external logic, and interface hardware in a single package. Using this chip, a 128-processor computer has been built, the array proces... View full abstract»

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  • A knowledge based architecture for incremental scheduling

    Publication Year: 1991, Page(s):850 - 854
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB)

    A report is presented on the development of CIBELE, a knowledge-based system (KBS) for the resolution of scheduling problems. Scheduling is an area in which traditional systems have often achieved poor results, mainly because of the large amount of knowledge that has to be taken into account and of the lack of a clearly understood resolution strategy. KBS technology, suggesting methodologies and t... View full abstract»

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  • The design of a systolic architecture to implement graphic transformations

    Publication Year: 1991, Page(s):170 - 175
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    A new systolic graphic array architecture is proposed in order to achieve the high computational throughput necessary to generate real-time processing. The proposed systolic architecture implements graphic transformations such as translations, scaling, and rotations on three dimensional vertices. The logarithmic number system is utilized to further increase the computational throughput. A comparis... View full abstract»

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  • A reconfigurable superchip for VLSI processing arrays

    Publication Year: 1991, Page(s):705 - 708
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    A reconfigurable sparse matrix superchip (SMS) for VLSI processing arrays is presented. The superchip architecture, its reconfiguration, and routing strategies are discussed. The application of the SMS for basic signal processing computations like matrix-vector and matrix-matrix multiplications is illustrated. The SMS implementations promise to be more economical and faster than the original systo... View full abstract»

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