By Topic

Proceedings International Phoenix Conference on Computers and Communications

28-31 March 1995

Filter Results

Displaying Results 1 - 25 of 110
  • Proceedings International Phoenix Conference on Computers and Communications

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • Multiprocessor design verification with generated realistic MP programs

    Publication Year: 1995, Page(s):389 - 395
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation requires many stages, from tests of simple portions of the design, through simple tests of a single processor to complex tests of multiple processors. We followed this strategy using so... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiprocessor system verification through behavioral modeling and simulation

    Publication Year: 1995, Page(s):396 - 402
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    The long development times and high costs of multiprocessor (MP) designs arise from their design complexity. To reduce the time and costs, it is critical that design bugs are detected early in the development cycle using design verification tools. The traditional method of hardware design verification is to simulate the actual hardware designs, usually specified in a hardware description language ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Timing driven genetic algorithm for standard-cell placement

    Publication Year: 1995, Page(s):403 - 409
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. At early generations, the search is biased toward solutions with superior timing characteristics. As the algorithm starts converging toward generations with acceptable delay properties, the objective is dynamically adjusted toward optimizing area and routability. Exper... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic, fault, and design error simulation based on an integrated hardware array

    Publication Year: 1995, Page(s):410 - 415
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Simulation is essential for the design and verification of digital systems and simulation tools are widely used to analyze the behavior of digital circuits. This paper describes an integrated hardware array specialized for digital logic, fault, and design error simulation. Hardware simulation, using a high performance special purpose architecture such as the integrated hardware array, is still a v... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Distributed programming in more efficient remote shell environment with direct data forwarding and lazy connection release

    Publication Year: 1995, Page(s):720 - 726
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    In this paper, we propose a distributed programming tool working in a form of programming in the large. We developed an enhanced remote shell, named `Ersh'. Ersh works in two modes, simple mode and distributed programming mode. Simple mode provides similar environment to rsh. For the case of distributed programming mode, Ersh adopts a direct data forwarding, a lazy connection release and an asynch... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Directions in multiprocessor verification

    Publication Year: 1995, Page(s):29 - 33
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    IBM server products, mainframes and RISC engines, have witnessed an evolution in verification techniques. Costly special-purpose engines and blunt attempts to force operating system initial program load's (IPL's) in simulation have given way to the idea of more complete, lower level simulation with smart testcase generation algorithms. The idea is to explore the state space of the smaller piece of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An object-oriented design for user interfaces

    Publication Year: 1995, Page(s):352 - 358
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The Object-Oriented (OO) design architecture for user interfaces presented in this paper, called IOWARE, is effective, does not violate OO principles, and promotes a high degree of reusability, extendibility, and portability. The innovative features of the design architecture are: [1] the decomposition of interactive applications into atomic and container interactive objects, [2] the use of dynami... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • XTPX transport system for flexible QoS support of multimedia applications

    Publication Year: 1995, Page(s):643 - 649
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    This paper describes design, implementation aspects and usage of a transport system based on XTPX (eXpress Transfer Protocol eXtended) for flexible Quality of Service (QoS) support of multimedia applications in a heterogeneous network, operating system and workstation environment. We focus especially on protocol mechanisms providing specific multimedia requirements. Rate control techniques for syn... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-level testing assignment for hypercubes with lower fault bounds

    Publication Year: 1995, Page(s):136 - 142
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The maximum allowed number of faulty processors in an n-dimensional hypercube system is n under PMC model for diagnosis. When the n fault bound is adopted, all links will be used to perform diagnosis. However, if the fault bound is lower than n, many links can be freed from the task of performing diagnosis. In this paper, we show that each drop of the fault bound by 1 can free 2n-1 link... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel task execution in LANs and performance analysis

    Publication Year: 1995, Page(s):423 - 429
    Cited by:  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper analyzes the performance of local area networks (LANs) of workstations for distributed computing. Application programs are scheduled by the user workstation (master) for parallel execution in the idle or lightly loaded processors (slaves). Partial results are collected by the master station to synchronize the operation of slave nodes. A general speedup equation is derived to verify the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ascend/descend algorithms on Cayley graphs

    Publication Year: 1995, Page(s):249 - 255
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    In a fundamental paper, F.P. Preparata and J.E. Vuillemin (1981) introduced the cube connected cycles graph and demonstrated a congestion free implementation of an ascend/descend algorithm. Subsequently, it was shown that the cube connected cycles graph is the Cayley graph of a group, the wreath product. We isolate the properties required of a Cayley graph that enable a congestion free implementat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Supporting dynamic reconfiguration of operating system using object and meta objects

    Publication Year: 1995, Page(s):727 - 733
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    In this paper, we present the architecture of an operating system kernel that provides efficient reconfiguration mechanism for itself and the applications. In the presented kernel, the reconfiguration process is realized either by the reconfiguration of the environment or by the reconfiguration of the contents of an object. The former is provided by the reflective management architecture of object... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Two-way balance-tolerant partitioning based on fuzzy graph clustering for hierarchical design of VLSI systems

    Publication Year: 1995, Page(s):416 - 422
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    In this paper, first, we model a two-way balance-tolerant partitioning for a VLSI circuit. Furthermore, we propose an efficient approach based on one kind of fuzzy graph clustering, probabilistic graph clustering, to obtain a two-way balance-tolerant partitioning of VLSI circuits. In this approach, a circuit netlist is represented as an edge-weighted undirected graph by transforming a hypergraph w... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simulation-based approach to architectural verification of multiprocessor systems

    Publication Year: 1995, Page(s):34 - 37
    Cited by:  Papers (10)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper presents a simulation-based method for verifying coherency in weakly ordered shared memory multiprocessor systems. This methodology requires minimal assumptions regarding the implementation details, such as the coherence protocol and cache line replacement rules. Independence from implementation details for architectural verification is achieved via a technique called data-coloring. The... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Task assignment in distributed computing systems

    Publication Year: 1995, Page(s):49 - 53
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    We introduce a technique based on the problem-space genetic algorithm (PSGA) for the static task assignment problem in homogeneous distributed computing systems to reduce the task turnaround time and to increase the throughput of the system by properly balancing the load and reducing the interprocessor communication time among processors. The PSGA based approach combines the power of genetic algor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel task scheduling using the order graph method

    Publication Year: 1995, Page(s):69 - 75
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    This paper proposes a new approach for task scheduling of fully specified flow graphs (FSFG) on parallel processing systems. This new approach is based on the enumeration and manipulation of linear extensions identified from a FSFG. The objective is to obtain a multiprocessor schedule which meets a set of admissibility conditions (iteration period, number of processors, precedence, and non-preempt... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A dynamically reconfigurable switch for high-speed networks

    Publication Year: 1995, Page(s):508 - 514
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    We present a design for a dynamically reconfigurable switch for high-speed networks. The proposed switch will be used to build high-performance parallel/distributed systems. Switch reconfigurability is exploited to implement different interconnection topologies and support different application requirements. We discuss an FPGA implementation of such a switch where a new configuration can be attain... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experience with an interactive attribute-based user information environment

    Publication Year: 1995, Page(s):359 - 365
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper explores an attribute-based approach to storing information in the context of a file system that supports extended attributes about files and a mechanism to manipulate files based on logical queries and comparisons of attributes. The novel aspects of our system are that it is sophisticated enough to operate as a user's primary method of interaction with the operating system and that it ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Enhancing B-ISDN signaling to meet the challenge of multimedia services

    Publication Year: 1995, Page(s):650 - 658
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    A key B-ISDN functional principle is the support of a wide range of data, video and audio applications in the same network. Moreover, the network must be flexible and adaptable to meet the demands of current and future services. A set of emerging multimedia services is presented in context of the requirements they impose on B-ISDN signaling protocols. With these multimedia services in mind, we ext... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient routing algorithms for folded-cube networks

    Publication Year: 1995, Page(s):143 - 151
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    We consider the partial multinode broadcast, the total exchange, and several other prototype communication tasks in a folded-cube network of processors. In the partial multinode broadcast in a N-processor network, each one of M arbitrary nodes (M⩽N) broadcasts a packet to all the remaining N-1 nodes. In the total exchange task each processor sends a separate (personalized) packet to every othe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Matching algorithms with parallel architectures: a quantitative approach

    Publication Year: 1995, Page(s):430 - 436
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The purpose of this paper is to assess the match between algorithms and MIMD parallel architectures from the perspective of resource requirements and resource supplies. In the Extended Evaluation Framework, three figures of merit (FOM1, FOM2 and FOM3) are proposed as measures of the match. FOM1 shows the time average of the sum of weighted resource to re... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Shortest path routing in a class of Cayley graphs of semi-direct product of finite groups

    Publication Year: 1995, Page(s):256 - 262
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Recently R.N. Draper (1990) initiated the study of interconnection networks based on Cayley graphs of semi-direct products of two cyclic groups called supertoroids graphs. Interest in this class of graphs stems from their relatively smaller diameter compared to toroids of the same size. In this paper we described a deterministic, distributed, shortest path algorithm for routing in this class of ne... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Value chain management: a project management approach

    Publication Year: 1995, Page(s):297 - 301
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Having examined several process-oriented approaches to value chain management, the authors concluded that the project management model (and systems) was a suitable mechanism for managing the value chain. Experiences with managing the value chain using these systems has led to a thorough understanding of their strengths and weaknesses, and an understanding of the need for extensions and enhancement... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A dynamic central scheduler load balancing mechanism

    Publication Year: 1995, Page(s):734 - 740
    Cited by:  Papers (7)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    One of the major design goals in distributed systems is to minimize the mean job response time, an important measurement of system performance. This paper presents a central scheduler load balancing mechanism (CSLB). A threshold policy (with two variable threshold values) is used to reduce network traffic overhead. A simple timer is implemented to allow both periodic and instantaneous load balanci... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.