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Test Conference, 1993. Proceedings., International

Date 17-21 Oct. 1993

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Displaying Results 1 - 25 of 131
  • Proceedings of IEEE International Test Conference - (ITC)

    Publication Year: 1993
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    Freely Available from IEEE
  • IEEE 1149 standards - Changing testing, silicon to systems

    Publication Year: 1993, Page(s):399 - 408
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    After an introduction to IEEE standards development, the five active standards projects in the IEEE 1149 family are described briefly. Some just promulgated changes to ANSI/IEEE Std 1149.1 are presented. Among these changes are two new optional instructions intended to aid testing of product which require both in-circuit and boundary-scan testing and subordination of the 1149.1 Test Access Port to... View full abstract»

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  • Distributed implementation of an ATPG system using dynamic fault allocation

    Publication Year: 1993, Page(s):409 - 418
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    This paper presents a new approach to a distributed ATPG system for large combinational circuits. Although several ATPG parallel implementations have been developed, many of them rely on the use of very specialized and expensive hardware. However, the proposed implementation is built over an heterogeneous network of workstations, which is normally available at all design labs. The proposed paralle... View full abstract»

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  • Workstation based parallel test generation

    Publication Year: 1993, Page(s):419 - 428
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    Generation of test vectors for the VLSI devices used in contemporary digital system is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the proc... View full abstract»

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  • Catch the ground bounce before it hits your system

    Publication Year: 1993, Page(s):574 - 584
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The lack of an industry standard ground bounce characterization procedure led us to a definition of a new BULL specification of this parameter for various families of fast IC components. We have developed a corresponding characterization test. This paper describes our automatic characterization procedure of ground bounce (GB) using automatic test equipment. Three-dimensional Shmoo Plots and corres... View full abstract»

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  • A method for reducing the search space in test pattern generation

    Publication Year: 1993, Page(s):429 - 435
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    This paper introduces the new concept of an implying node by which an efficient decision point can be selected. The implying node is a signal line whose value implies the values of the primary inputs. This means that a decision on the implying node is equivalent to several decisions on the primary inputs. As a result, a decision on the implying node is able to induce more implications. This effect... View full abstract»

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  • Integrating electrical test into final assembly

    Publication Year: 1993, Page(s):585 - 589
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    This paper describes a set of projects that combine integrated circuit assembly steps. The completed set of projects will allow direct shipment of devices to customers from the end of the trim and form press. The integrated process steps include strip inspection, device mark, mark inspection, dambar removal, lead trim, final test, device form, device singulation, coplanarity inspection, reject sor... View full abstract»

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  • Extraction of coupled SPICE models for packages and interconnects

    Publication Year: 1993, Page(s):436 - 445
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    We have developed a method, using TDR, to extract an equivalent coupled SPICE model for a set of package pins. The technique does not use any fitting or optimization. With the appropriate fixturing this method could be used for automated model extraction. The SPICE model which is produced, models the propagation delay and crosstalk between pins View full abstract»

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  • Design-for-testability economics

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    The need for design for testability (DFT) in mixed-signal boards and systems is becoming more significant as the miniaturization and superintegration trends continue. Accessibility to critical nodes of the circuits is required in order to meet the demands for higher quality, lower cost, shorter time to market, continuous improvement and standardization. However, we must be prudent in the way we ad... View full abstract»

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  • Keep alive-A new requirement for high performance μprocessor test

    Publication Year: 1993, Page(s):446 - 450
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The latest generation of RISC μprocessor devices cannot remain powered up without simultaneously being stimulated by the test system, or they will enter into a catastrophic high power dissipation mode. This paper presents a novel solution to this new testing problem View full abstract»

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  • Inhomogeneous cellular automata for weighted random pattern generation

    Publication Year: 1993, Page(s):1013 - 1022
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    Weighted random pattern testing methods produce higher fault coverage with shorter test lengths than random pattern testing methods. Here we present the weighted cellular automaton (WCA), an inhomogeneous cellular automaton that generates weighted random patterns on a test per clock basis. The WCA is a complete automaton that contains no external weighting logic and no multiplexers between flip-fl... View full abstract»

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  • Practical considerations for mixed-signal test bus

    Publication Year: 1993, Page(s):591 - 592
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    Mixed-signal test bus holds the promise to improve board-level testability, but it will also introduce various side-effects, possibly costing excessive overhead and even performance degradation. Some practical considerations on defining and applying such a test bus standard are presented View full abstract»

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  • Minimizing test time by exploiting parallelism in macro test

    Publication Year: 1993, Page(s):451 - 460
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Increasing complexity of modern designs and high costs of test equipment are putting more and more emphasis on test application times. This paper presents a classification of methods for reducing the test time of a device by exploiting parallelism in Macro Test. Techniques and considerations are given for different methods of parallel testing. It is shown that without design modifications signific... View full abstract»

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  • An implicit delay fault simulation method with approximate detection threshold calculation

    Publication Year: 1993, Page(s):705 - 713
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    Existing methodologies for determining delay fault coverages or for building up a delay fault dictionary are sometimes accurate, but rarely fast and easy to implement. Therefore, with the aim of removing these deficiencies, a new and more efficient fault simulation strategy for gate delay faults in combinational or scan-based circuits is presented. This method is based on a critical path tracing a... View full abstract»

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  • A test methodology for VLSI chips on silicon

    Publication Year: 1993, Page(s):359 - 368
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unp... View full abstract»

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  • Multiple fault diagnosis in printed circuit boards

    Publication Year: 1993, Page(s):662 - 671
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    This paper addresses the problems of diagnosing multiple faults occuring in the non-boundary-scan parts of a printed circuit board. The paper details a diagnostic algorithm based upon combining the fault signatures of single faults in order to produce a pattern which best matches the signature of a multiple fault. In addition, a graphical routine is presented which allows the tester to analyze a g... View full abstract»

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  • Visualizing test information: A novel approach for improving testability

    Publication Year: 1993, Page(s):149 - 156
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    As circuit size increases, the difficulty of generating test sets with acceptable fault coverage within useful time limits increases by a non-polynomial factor. Information from test generation programs provides a basis for circuit modification targeting increased fault coverage in reduced time with fewer test vectors. In its raw form, this information is difficult, if not impossible, to comprehen... View full abstract»

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  • Generation of optimized single distributions of weights for random built-in self-test

    Publication Year: 1993, Page(s):1023 - 1030
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper presents a probabilistic-based fault-model approach to the generation of optimized single distributions of weights for random built-in self-test. Many techniques use multiple sets of weights to obtain an important reduction in the test length. However, these strategies consume large memory areas to store the different distributions. In order to obtain a highly optimized set of weights, ... View full abstract»

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  • Dos and Don'ts in computing fault coverage

    Publication Year: 1993
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    High fault coverage for single stuck faults (SSFs) is a necessary (but not sufficient) condition to achieve high defect coverage. The defect coverage of the manufacturing test is the main factor determining the quality of the products shipped to customers. Since the fault coverage for SSFs is a basic concept in testing, it should have a clear, well-understood, and universally accepted meaning. How... View full abstract»

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  • A flexible approach to data collection for component test systems

    Publication Year: 1993, Page(s):461 - 470
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    Yield improvements for VLSI devices require data collection and analysis during the manufacturing cycle. These data should be collected in a form that satisfies the needs of those performing different functions within the factory. This paper describes an approach to data collection that focuses on collecting test data in a format customized to the users needs. Though implemented on an advanced VLS... View full abstract»

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  • Generation of compact delay tests by multiple path activation

    Publication Year: 1993, Page(s):714 - 723
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    We use a 23-value logic system to generate robust path delay tests. Each test is successively augmented to detect as many path faults as possible. Other features of the test generator are a podem-like branch and bound search for test, an efficient path designation based on ordering of paths, and an algorithmic selection of secondary target faults for augmenting the tests to cover multiple faults. ... View full abstract»

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  • Certification trails and software design for testability

    Publication Year: 1993, Page(s):200 - 209
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    This paper investigates design techniques which may be applied to make program testing easier. We present methods for modifying a program to generate additional data which we refer to as a certification trail. This additional data is designed to allow the program output to be checked more quickly and effectively. Certification trails have heretofore been described primarily from a theoretical pers... View full abstract»

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  • MCM foundry test methodology and implementation

    Publication Year: 1993, Page(s):369 - 372
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The Texas Instruments (TI) MCM foundry was initiated to address both military and commercial customers, with varying architectures and test requirements. A test strategy was developed and implemented to address a wide range of customers, as well as a roadmap for future test interface and equipment. This paper describes the test strategy in place for the dual use foundry, including hardware that wa... View full abstract»

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  • The standard mirror boards (SMBs) concept-An innovative improvement of traditional ATE for up to 10 mil bare board testing

    Publication Year: 1993, Page(s):672 - 679
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    TIM A Laboratory and IMD Test Systems, a division of IMD company, offers a brand new reliable and cost effective solution to access and test bare printed circuit boards (whose pitch can be as low as 10 mils), based on a fixture (mixing standard bed of nail and IMD Standard Mirror Boards (SMBs)). This method allows the user to test very fine pitch PCBs, even with this old standard 100 mils universa... View full abstract»

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  • Application of statistical techniques to critical system parameters

    Publication Year: 1993, Page(s):108 - 114
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    An IC supplier's specification or data sheet electrical parameter limits are meaningless without knowledge of the supplier's process capability (i.e., a given critical electrical parameter's centering and distribution), especially if one is attempting to select the most robust supplier. This paper provides practical examples of how statistical techniques can be used to facilitate selection of supp... View full abstract»

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