By Topic

Test Conference, 1993. Proceedings., International

Date 17-21 Oct. 1993

Filter Results

Displaying Results 1 - 25 of 131
  • Proceedings of IEEE International Test Conference - (ITC)

    Save to Project icon | Request Permissions | PDF file iconPDF (36 KB)  
    Freely Available from IEEE
  • The standard mirror boards (SMBs) concept-An innovative improvement of traditional ATE for up to 10 mil bare board testing

    Page(s): 672 - 679
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    TIM A Laboratory and IMD Test Systems, a division of IMD company, offers a brand new reliable and cost effective solution to access and test bare printed circuit boards (whose pitch can be as low as 10 mils), based on a fixture (mixing standard bed of nail and IMD Standard Mirror Boards (SMBs)). This method allows the user to test very fine pitch PCBs, even with this old standard 100 mils universal grid test system View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple fault diagnosis in printed circuit boards

    Page(s): 662 - 671
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    This paper addresses the problems of diagnosing multiple faults occuring in the non-boundary-scan parts of a printed circuit board. The paper details a diagnostic algorithm based upon combining the fault signatures of single faults in order to produce a pattern which best matches the signature of a multiple fault. In addition, a graphical routine is presented which allows the tester to analyze a given set of test vectors. This analysis provides an implicit fault-simulation process for stuck-at and bridging faults. Furthermore, the process informs the tester of any faults which mask other previously detectable faults within the given test set View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cultural evolution in software testing

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB)  

    In order to successfully apply any modern test technique, it is imperative to establish a corresponding training program. The deployment of appropriate tools is only a part of the task, in fact, in some cases - a minor task. The bigger question remains, as to how to plan the cultural shift of an organization. Several successful companies, for example IMA of Colorado, make their business in helping organizations transition into a different culture. This paper explores this important subject, as it pertains to the deployment of the operational profiles-based technique View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analog circuit testing based on sensitivity computation and new circuit modeling

    Page(s): 652 - 661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    Analog circuit testing is considered to be a very difficult task, due mainly to the lack of fault models and accessibility to internal nodes. An approach is presented for analog circuit modeling and testing to overcome this problem. This circuit modeling is based on a sensitivity computation and on circuit structure, which are crucial in analog circuit testing. The testability of the circuit is achieved for the simple fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing both catastrophic and soft faults. Some experimental results are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The impact of commercial off-the-shelf (COTS) equipment on system test and diagnosis

    Page(s): 30 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Improved interface standards and reduced design budgets dictate that commercial off-the-shelf (COTS) equipment be more readily integrated into system design. Often COTS is chosen for its functional capabilities and electronic compatibilities with little regard to testability and maintainability features. COTS equipment is often characterized by a lack of detailed information about the specific internal design of the equipment. Complex interactions across an array of subsystems may decrease the diagnosability of the system as a whole where deficits in information occur. In this paper, we describe an analysis approach for assessing system testability and providing system diagnostics that is amenable to including COTS equipment in the system under test. We illustrate the approach with the standard analysis of a system consisting of several subsystems with full information available View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mutation-based testing of concurrent programs

    Page(s): 845 - 853
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    Mutation-based software testing is a powerful technique for testing software systems. It requires executing many slightly different versions of the same program to evaluate the quality of the test cases used to test the program. Mutation-based testing has been applied to sequential software; however, problems are encountered when it is applied to concurrent programs. These problems are a product of the nondeterminism inherent in the executions of concurrent programs. In this paper, we describe a general approach to testing and debugging concurrent programs, called deterministic execution testing and debugging. We then describe a combination of deterministic execution testing and mutation-based testing, called deterministic execution mutation testing (DEMT), and illustrate the DEMT approach with an example View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Delay testing using a matrix of accessible storage elements

    Page(s): 243 - 252
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    This paper discusses a delay test methodology that avoids the area and performance overhead of enhanced scan elements by using a matrix of accessible storage elements. Delay test generation is performed for circuits, which may contain internal tri-state elements, bi-directional ports, asynchronous sets/resets and clock gating, using an automatic test pattern generator that is based on an extended 16 valued calculus View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A general purpose IDDQ measurement circuit

    Page(s): 642 - 651
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    A relatively high-speed IDDQ measurement circuit called QuiC-Mon is described. Depending upon IC settling times, upper measurement rates range from 50 kHz to 250 kHz at 100 nA resolution. It provides an inexpensive solution for fast, sensitive IDDQ measurements in CMOS IC wafer probe or packaged part production testing View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A universal framework for managed built-in test

    Page(s): 21 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    An approach to systems test is presented that builds on earlier work by several design-for-test and test management standards committees and research teams. The approach is based on a generic model of a managed built-in test process supported by standard test descriptions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test pattern generation with restrictors

    Page(s): 598 - 605
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    This paper extends state-of-the-art ATPG systems by including constraints, called restrictors, on the allowable values of the bits of a test vector. Such restrictors often occur in "real-world" circuits where certain bit positions of a test vector have to take on a particular value (e.g. in case of a reset line) or are prohibited from taking on a particular value (e.g. in order to prevent an illegal state to be entered). This paper describes the types of restrictors, as encountered in "real world" circuits; it shows the required modifications to ATPG algorithms for stuck-at faults in combinational circuits, in order to cope with restrictors; and finally, the results of experiments determining the consequences for the ATPG time and fault coverage are given. The overall conclusion is: restrictors can easily be implemented in any ATPG system; the use of restrictors is essential in "real-world" circuits; the influence of restrictors on the ATPG time is small while a new class of "redundant faults" is identified, belonging to that part of the circuit which cannot be tested due to the specified restrictors View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • BIST and delay fault detection

    Page(s): 236 - 242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    We propose simple modifications to existing BIST schemes. These modifications significantly improve the path delay fault coverage. For example, a modified circular self-test path can detect a significant number of path delay faults within a reasonable test running time View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in current sensor for IDDQ test in CMOS

    Page(s): 635 - 641
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    This paper presents a current sensor circuit which can be built into a CMOS logic circuit to perform a self test for leakage current. The distinct features of the current sensor circuitry are described in detail. The circuit is verified by using the SPICE2 simulator View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Utilizing boundary scan to implement BIST

    Page(s): 167 - 173
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The use of boundary scan as a cost effective design for test (DFT) technique for testing I/O interconnect type defects, i.e. solder opens/shorts, defective drivers/receivers, etc. is demonstrated. To gain added benefits for a small increase in circuit overhead, boundary scan provides an excellent foundation on which to implement a built-in self-test (BIST) strategy which allows migration into future products. This paper describes the BIST techniques and control implemented for two gate array designs at NCR - Peripheral Products Division (PPD) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds

    Page(s): 63 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault location algorithms for repairable embedded RAMs

    Page(s): 825 - 834
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    This paper shows how to: (1) convert single-bit march tests into multi-bit March tests; and then (2) how to transform the new multi-bit March tests, using a "serial shifting notation" which represents "serial access" in embedded RAMs, into serial-access word-oriented March tests. The standard March test notation is extended to compactly include Galloping read actions, and other algorithms with two levels of FOR-loops, since such algorithms are indispensible for locating coupling faults in cell arrays, and stuck-open faults in address decoders. The main body of the paper uses the new notations to describe seven categories of fault location algorithms, with each algorithm displayed in both the "hybrid serial/parallel" and the "modular" data accessing formats View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generated in real-time instant process statistics (“GRIPS”): Immediate, tester-computed test statistics, eliminating the post-processing of datalogs

    Page(s): 471 - 477
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A system called GRIPS has been developed which uses the tester computer to compute test statistics online and generate an immediate comprehensive statistical report per batch. This overcomes memory and response time disadvantages of commercial test statistical packages View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Partial scan at the register-transfer level

    Page(s): 488 - 497
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    This paper presents a partial scan methodology suited for (pipelined) data paths described at the register-transfer level. The method is based on feedback elimination by making existing registers scanable or by adding extra transparent scan registers. An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. Our symbolic test pattern generation technique can very effectively deal with the delay in the remaining sequential circuit parts. Furthermore, the symbolic test method makes various scan schemes possible which ensures a correct application and evaluation of the test vectors. They are discussed and compared in terms of their hardware requirements, test application times and test accuracy View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • “In system” transparent autodiagnostics of RAMs

    Page(s): 835 - 844
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    In this paper we present an original technique of testing classical RAMs (without BIST) in real system environment. The developed testing methodology allows to cover a large class of faults including pattern sensitivity and dynamic faults. An important feature of the presented approach is test transparency which assures that at the end of the test the contents of the RAM are equal to its initial contents (before testing). This technique is especially useful for periodic autodiagnostic procedures in embedded and multiprocessor systems. It has been also extended for cache and dual port RAMs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of parallelsite test on an 8-bit configurable microcontroller

    Page(s): 226 - 235
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    This paper describes the process by which an 8-bit microcontroller was put into production test by testing four devices simultaneously. The test setup used was a pick and place handler, and a VLSI ATE (automated test equipment) tester. The process used to implement this new testing method is presented. Hardware and software constraints are explored, with an emphasis on the additional performance gained from out test system View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IDD pulse response testing on analog and digital CMOS circuits

    Page(s): 626 - 634
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    This paper presents a new method for detecting defect and fabrication variations in both digital and analog CMOS circuits by simultaneously pulsing the power supply rails and analyzing the temporal and/or the spectral characteristics of the resulting transient rail currents. The method presented has a distinct advantage over other forms of iDD testing because it requires a single test vector to excite and expose the presence of a defect or irregular fabrication process condition. This paper presents data from simulations and defective IC's supporting this technique View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology-independent boundary scan synthesis (technology and physical issues)

    Page(s): 157 - 166
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    The paper presents key technology and physical issues associated with a boundary scan synthesis system. The system accommodates multiple vendor technologies and the requirements of (sometimes non-1149.1 compliant) user specified boundary scan architectures that access core test structures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Structured CBIST in ASICS

    Page(s): 332 - 338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A novel method for automating the installation of CBIST and moving test development forward in the design cycle is shown, including a practical method for determining CBIST pathology. Three ASICS have been developed with this method. Design and prototype results are given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A flexible approach to data collection for component test systems

    Page(s): 461 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    Yield improvements for VLSI devices require data collection and analysis during the manufacturing cycle. These data should be collected in a form that satisfies the needs of those performing different functions within the factory. This paper describes an approach to data collection that focuses on collecting test data in a format customized to the users needs. Though implemented on an advanced VLSI test system, key elements of this approach can be applied to any data collection domain View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithms for cost optimised test strategy selection

    Page(s): 383 - 391
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    This paper describes a system which aids designers in the selection of economically optimal design for testability strategies. The approach recognizes that design for testability decisions taken for parts of the circuit affect subsequent decisions for the design as a whole. Economics models are used to objectively evaluate strategies, and a set of algorithms is presented which provide efficient methods for searching the test strategy space. Different approaches are compared and a novel use of simulated annealing for test strategy planning is presented. Examples on real designs are given, with an indication of CPU time and computational complexity View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.