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Proceedings of IEEE International Test Conference - (ITC)

17-21 Oct. 1993

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  • Proceedings of IEEE International Test Conference - (ITC)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (36 KB)
    Freely Available from IEEE
  • Experience in diagnosing a remote, tele-controlled unit using the AITEST expert system

    Publication Year: 1993, Page(s):37 - 44
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    This paper describes our experience in using a diagnostic expert system (AITEST) for fault isolation, diagnosis and repair action recommendations for a remote, tele-controlled UUT (Unit Under Test). We identify the unique requirements of diagnosis in this class of problems, and explains how these requirements were met in less than three person-months by integrating the expert system with specially... View full abstract»

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  • Parameter monitoring: Advantages and pitfalls

    Publication Year: 1993, Page(s):115 - 124
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Complex tests are often required for the measurement of certain IC parameters. Because these tests are too expensive to include in a production test, an alternative test method is studied. Additional structures that behave identically with respect to the considered parameter, called monitors, are placed near the original structures. If a strong spatial correlation exists for the parameter, the par... View full abstract»

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  • System level interconnect test in a tristate environment

    Publication Year: 1993, Page(s):45 - 53
    Cited by:  Papers (12)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    System interconnect test is a significant challenge. In this paper we describe a practical system level interconnect test scheme which has been successfully implemented in a commercial environment. This test scheme is responsible for uncovering faults in driver/receiver elements, card level interconnects and backplane interconnects. It is used both as a manufacturing test and in field service. We ... View full abstract»

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  • Creating a mixed-signal simulation capability for concurrent IC design and test program development

    Publication Year: 1993, Page(s):125 - 132
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The ability to link mixed-signal IC design and test databases can shorten product development cycles in multiple ways. By allowing designers to simulate device tests and by giving test engineers access to the results, such a link promotes testability from the earliest stages of design, and generates data usable in test program development. Moreover, by enabling test program development to take pla... View full abstract»

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  • Fast and accurate CMOS bridging fault simulation

    Publication Year: 1993, Page(s):54 - 62
    Cited by:  Papers (61)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper identifies the two key factors involved in obtaining accurate bridging fault simulation results and presents a hybrid technique that maximizes both the speed and accuracy of bridging fault simulation for gate-level standard cell designs. Both combinational and sequential circuits are studied and the results are compared with several other bridging fault simulators View full abstract»

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  • Tools and techniques for converting simulation models into test patterns

    Publication Year: 1993, Page(s):133 - 138
    Cited by:  Papers (2)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This paper focuses on the problems of extraction of the timing and functional data from the simulation of a complex digital device and the creation of a test pattern suitable for execution on a digital test system. The specific areas of interest are the structure of the device model, representation of the timing information, and language for defining waveforms View full abstract»

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  • Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds

    Publication Year: 1993, Page(s):63 - 72
    Cited by:  Papers (101)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simu... View full abstract»

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  • Economics modelling for the determination of test strategies for complex VLSI boards

    Publication Year: 1993, Page(s):210 - 217
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This paper describes the economics modeling techniques developed by the authors for the determination of optimal test strategies for board level testing. A number of interconnected economics models are used to describe the test process and the quality achieved, enabling the user to make predictive calculations for the effects of design and test choices. The results of sample runs presented, which ... View full abstract»

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  • Realizing a high measure of confidence for defect level analysis of random testing

    Publication Year: 1993, Page(s):478 - 487
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    The defect level in circuit testing is the percentage of circuits, such as chips, which are defective and shipped for use after testing. In this work, it is demonstrated that the defect level of testing a circuit using random patterns should have a probability distribution rather than just a single value. Based on this concept, the confidence degree of a specified defect level for random testing i... View full abstract»

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  • A test methodology for VLSI chips on silicon

    Publication Year: 1993, Page(s):359 - 368
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unp... View full abstract»

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  • Mutation-based testing of concurrent programs

    Publication Year: 1993, Page(s):845 - 853
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Mutation-based software testing is a powerful technique for testing software systems. It requires executing many slightly different versions of the same program to evaluate the quality of the test cases used to test the program. Mutation-based testing has been applied to sequential software; however, problems are encountered when it is applied to concurrent programs. These problems are a product o... View full abstract»

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  • Automatic test plan generation for analog and mixed signal integrated circuits using partial activation and high level simulation

    Publication Year: 1993, Page(s):139 - 148
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    This paper introduces a novel technique to generate test plans automatically for analog and mixed signal integrated circuits (ICs), which are designed using modular design concept similar to that of digital integrated circuits. In such structured, top-down, modular design methodology of analog and mixed signal integrated circuits, each block in the design is represented by a high level but accurat... View full abstract»

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  • Testing fully testable systems: A case study

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Testability is a measure of the potential to evaluate performance, determine operability, or identify faults within a system. Testability must be coupled with a strategy by which it is used to achieve field maintainability. It is often difficult to distinguish between shortcomings in testability and shortcomings in diagnostic strategy; however, adequate levels of both testability and diagnosis are... View full abstract»

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  • Built-in current sensor for IDDQ test in CMOS

    Publication Year: 1993, Page(s):635 - 641
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper presents a current sensor circuit which can be built into a CMOS logic circuit to perform a self test for leakage current. The distinct features of the current sensor circuitry are described in detail. The circuit is verified by using the SPICE2 simulator View full abstract»

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  • A comparison of defect models for fault location with Iddq measurements

    Publication Year: 1993, Page(s):1051 - 1060
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in t... View full abstract»

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  • Test generation with high coverages for quiescent current test of bridging faults in combinational circuits

    Publication Year: 1993, Page(s):73 - 82
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. T... View full abstract»

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  • The economics of guardband placement

    Publication Year: 1993, Page(s):218 - 225
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    This paper investigates the guardbanding technique used with production test equipment. The consequences of guardband size and tester inaccuracy on the profit per unit produced are analyzed. The Taguchi loss function is used to model the effect of customer dissatisfaction when a product strays from its intended target. This loss function is integrated with product profitability and the variables o... View full abstract»

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  • Partial scan at the register-transfer level

    Publication Year: 1993, Page(s):488 - 497
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    This paper presents a partial scan methodology suited for (pipelined) data paths described at the register-transfer level. The method is based on feedback elimination by making existing registers scanable or by adding extra transparent scan registers. An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. Our symbolic test pattern generation... View full abstract»

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  • Simulation of non-classical faults on the gate level - The fault simulator COMSIM

    Publication Year: 1993, Page(s):883 - 892
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    COMSIM is a fault simulator for combinational circuits which can efficiently handle various gate level fault models. Stuck-at faults, function conversions, bridging faults, transition faults as well as multiple faults of all types and faults with additional fault detection conditions, can be simulated in one pass. This offers a practical approach to solve the conflict between the accuracy of fault... View full abstract»

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  • Generation of compact delay tests by multiple path activation

    Publication Year: 1993, Page(s):714 - 723
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    We use a 23-value logic system to generate robust path delay tests. Each test is successively augmented to detect as many path faults as possible. Other features of the test generator are a podem-like branch and bound search for test, an efficient path designation based on ordering of paths, and an algorithmic selection of secondary target faults for augmenting the tests to cover multiple faults. ... View full abstract»

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  • MCM foundry test methodology and implementation

    Publication Year: 1993, Page(s):369 - 372
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The Texas Instruments (TI) MCM foundry was initiated to address both military and commercial customers, with varying architectures and test requirements. A test strategy was developed and implemented to address a wide range of customers, as well as a roadmap for future test interface and equipment. This paper describes the test strategy in place for the dual use foundry, including hardware that wa... View full abstract»

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  • Automated testing of open software standards

    Publication Year: 1993, Page(s):854 - 858
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    This paper illustrates the power and flexibility of a new approach to creating conformance test suites for open systems software standards such as POSIX. The approach incorporates an automated process for the generation and validation of conformance tests. The automated process has been implemented and comprises key components of the Clemson Automated Testing System (CATS). CATS is a testing facil... View full abstract»

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  • Visualizing test information: A novel approach for improving testability

    Publication Year: 1993, Page(s):149 - 156
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    As circuit size increases, the difficulty of generating test sets with acceptable fault coverage within useful time limits increases by a non-polynomial factor. Information from test generation programs provides a basis for circuit modification targeting increased fault coverage in reduced time with fewer test vectors. In its raw form, this information is difficult, if not impossible, to comprehen... View full abstract»

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  • Let's grade all the faults

    Publication Year: 1993
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    The motivation for carrying out fault grading is to obtain a metric which expresses the effectiveness of a test in screening defective components. In terms of shipped parts, this effectiveness is reflected by the reject rate, or the proportion of parts which fail when used in their intended application. The most useful metric would be one which tracks the resultant quality level well, so that impr... View full abstract»

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