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Test Conference, 1993. Proceedings., International

Date 17-21 Oct. 1993

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Displaying Results 1 - 25 of 131
  • Proceedings of IEEE International Test Conference - (ITC)

    Publication Year: 1993
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    Freely Available from IEEE
  • Scan DFT: Why more can cost less

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Reducing "time to market" is one of the keys to success in an increasingly competitive business environment. Even a small delay in getting a product to market can have a significant negative impact on its profitability. A large proportion of the total design time for complex ASICs can be spent on test development. Therefore, test automation is becoming essential View full abstract»

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  • Known good die for MCMs: Enabling technologies

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    Summary form only given, as follows. The need for known good die for MCMs has been widely recognized. However, satisfying this need has presented many test challenges. Fortunately, the efforts of many workers are now providing the basic technology to assure the performance and reliability of die to be used in MCMs. Performance testing of ICs and chips on wafers is illustrated at gigahertz rates wi... View full abstract»

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  • Generation of optimized single distributions of weights for random built-in self-test

    Publication Year: 1993, Page(s):1023 - 1030
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper presents a probabilistic-based fault-model approach to the generation of optimized single distributions of weights for random built-in self-test. Many techniques use multiple sets of weights to obtain an important reduction in the test length. However, these strategies consume large memory areas to store the different distributions. In order to obtain a highly optimized set of weights, ... View full abstract»

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  • Benefits of boundary-scan to in-circuit test

    Publication Year: 1993
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    Boundary-Scan 1149.1 and its tight coupling with built-in self test (BIST) has proven to be an integral part in the time-to-market (TTM) and customer satisfaction that NCR computers are experiencing in their product realization cycles. As one of the many benefactors of these designed-in test features, the manufacturing test group within Columbia has realized tremendous increases in efficiencies in... View full abstract»

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  • MCM foundry test methodology and implementation

    Publication Year: 1993, Page(s):369 - 372
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The Texas Instruments (TI) MCM foundry was initiated to address both military and commercial customers, with varying architectures and test requirements. A test strategy was developed and implemented to address a wide range of customers, as well as a roadmap for future test interface and equipment. This paper describes the test strategy in place for the dual use foundry, including hardware that wa... View full abstract»

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  • Inhomogeneous cellular automata for weighted random pattern generation

    Publication Year: 1993, Page(s):1013 - 1022
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    Weighted random pattern testing methods produce higher fault coverage with shorter test lengths than random pattern testing methods. Here we present the weighted cellular automaton (WCA), an inhomogeneous cellular automaton that generates weighted random patterns on a test per clock basis. The WCA is a complete automaton that contains no external weighting logic and no multiplexers between flip-fl... View full abstract»

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  • Fast and accurate CMOS bridging fault simulation

    Publication Year: 1993, Page(s):54 - 62
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper identifies the two key factors involved in obtaining accurate bridging fault simulation results and presents a hybrid technique that maximizes both the speed and accuracy of bridging fault simulation for gate-level standard cell designs. Both combinational and sequential circuits are studied and the results are compared with several other bridging fault simulators View full abstract»

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  • A BIST scheme for an SNR test of a sigma-delta ADC

    Publication Year: 1993, Page(s):805 - 814
    Cited by:  Papers (97)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Built-In-Self-Test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-the-field diagnostics. This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test of an analog-to-digital converter. The MAD-BIST strategy for the SNR test of the A/D convert... View full abstract»

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  • A test methodology for VLSI chips on silicon

    Publication Year: 1993, Page(s):359 - 368
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unp... View full abstract»

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  • On selecting flip-flops for partial reset

    Publication Year: 1993, Page(s):1008 - 1012
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Partial reset is an inexpensive design for test technique in which an additional primary input is connected to the reset or the set inputs of a subset of flip-flops (FFs). In this paper, we present a new method to select the FFs to be initialized and their initial values. The FFs are selected based on their contribution to the testability of the circuit. A sensitivity analysis is done to determine... View full abstract»

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  • BIST and delay fault detection

    Publication Year: 1993, Page(s):236 - 242
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    We propose simple modifications to existing BIST schemes. These modifications significantly improve the path delay fault coverage. For example, a modified circular self-test path can detect a significant number of path delay faults within a reasonable test running time View full abstract»

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  • Fault location algorithms for repairable embedded RAMs

    Publication Year: 1993, Page(s):825 - 834
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper shows how to: (1) convert single-bit march tests into multi-bit March tests; and then (2) how to transform the new multi-bit March tests, using a "serial shifting notation" which represents "serial access" in embedded RAMs, into serial-access word-oriented March tests. The standard March test notation is extended to compactly include Galloping read actions, and other algorithms with two... View full abstract»

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  • Let's grade all the faults

    Publication Year: 1993
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    The motivation for carrying out fault grading is to obtain a metric which expresses the effectiveness of a test in screening defective components. In terms of shipped parts, this effectiveness is reflected by the reject rate, or the proportion of parts which fail when used in their intended application. The most useful metric would be one which tracks the resultant quality level well, so that impr... View full abstract»

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  • Utilizing boundary scan to implement BIST

    Publication Year: 1993, Page(s):167 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The use of boundary scan as a cost effective design for test (DFT) technique for testing I/O interconnect type defects, i.e. solder opens/shorts, defective drivers/receivers, etc. is demonstrated. To gain added benefits for a small increase in circuit overhead, boundary scan provides an excellent foundation on which to implement a built-in self-test (BIST) strategy which allows migration into futu... View full abstract»

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  • Characterization of edge placement accuracy in high-speed digital pin electronics

    Publication Year: 1993, Page(s):556 - 565
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    Understanding and measuring edge placement accuracy in pin electronics designs can be a tricky and misleading process. This is especially true when the timing differences being measured are on the order of 25 ps. This paper describes some of the potential error sources in pin electronics designs and briefly explains the causes. It then describes the test methods that were used to evaluate the edge... View full abstract»

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  • Design for testability of a modular, mixed signal family of VLSI devices

    Publication Year: 1993, Page(s):797 - 804
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    Recent advances in semiconductor design and fabrication have made it possible to integrate an entire system including digital microcontrollers, memories, analog and power devices onto a single silicon chip. The complexity of test has increased greatly due to the embedded nature of these devices and also the significant economic pressure to maximize the number of analog/power pins and minimize test... View full abstract»

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  • A universal framework for managed built-in test

    Publication Year: 1993, Page(s):21 - 29
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An approach to systems test is presented that builds on earlier work by several design-for-test and test management standards committees and research teams. The approach is based on a generic model of a managed built-in test process supported by standard test descriptions View full abstract»

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  • A synthesis approach to design for testability

    Publication Year: 1993, Page(s):754 - 763
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. We use partition theory and a state variable dependency minimization criterion to map the test function states onto the states of the given circuit. The test generation complexity for our implementation is the same as that for a full scan design. To apply the method to ... View full abstract»

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  • An ALU-based programmable MISR/pseudorandom generator for a MC68HC11 family self-test

    Publication Year: 1993, Page(s):349 - 358
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    This paper describes an ALU-based self-test system implemented on a MC68HC11 Family microcontroller. A fully programmable pseudorandom pattern generator and multiple input signature register are used to reduce test lengths and aliasing probabilities. Design constraints and goals are described along with a detailed description of an efficient method of using the ALU to implement the self-test funct... View full abstract»

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  • A flexible approach to data collection for component test systems

    Publication Year: 1993, Page(s):461 - 470
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    Yield improvements for VLSI devices require data collection and analysis during the manufacturing cycle. These data should be collected in a form that satisfies the needs of those performing different functions within the factory. This paper describes an approach to data collection that focuses on collecting test data in a format customized to the users needs. Though implemented on an advanced VLS... View full abstract»

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  • A learning-based method to match a test pattern generator to a circuit-under-test

    Publication Year: 1993, Page(s):998 - 1007
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    LFSRs are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit is not fully testable by a practical number of pseud... View full abstract»

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  • Certification trails and software design for testability

    Publication Year: 1993, Page(s):200 - 209
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    This paper investigates design techniques which may be applied to make program testing easier. We present methods for modifying a program to generate additional data which we refer to as a certification trail. This additional data is designed to allow the program output to be checked more quickly and effectively. Certification trails have heretofore been described primarily from a theoretical pers... View full abstract»

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  • Implementation of parallelsite test on an 8-bit configurable microcontroller

    Publication Year: 1993, Page(s):226 - 235
    Cited by:  Papers (2)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper describes the process by which an 8-bit microcontroller was put into production test by testing four devices simultaneously. The test setup used was a pick and place handler, and a VLSI ATE (automated test equipment) tester. The process used to implement this new testing method is presented. Hardware and software constraints are explored, with an emphasis on the additional performance g... View full abstract»

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  • Dos and Don'ts in computing fault coverage

    Publication Year: 1993
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    High fault coverage for single stuck faults (SSFs) is a necessary (but not sufficient) condition to achieve high defect coverage. The defect coverage of the manufacturing test is the main factor determining the quality of the products shipped to customers. Since the fault coverage for SSFs is a basic concept in testing, it should have a clear, well-understood, and universally accepted meaning. How... View full abstract»

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