Proceedings of IEEE International Test Conference - (ITC)

17-21 Oct. 1993

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Displaying Results 1 - 25 of 131
  • Multiconfiguration technique to reduce test duration for sequential circuits

    Publication Year: 1993, Page(s):989 - 997
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (996 KB)

    Sequential ATPGs, now, are able to handle an appreciable degree of sequentiality, thus allowing to treat partial scan implementations with a suitable fault coverage. Nevertheless, with these methods the test duration remains often prohibitive due to the long scan register. The DFT method we present is based on cycle breaking and sequential depth reduction guided by graph analysis. When a flip-flop... View full abstract»

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  • Known good die for MCMs: Enabling technologies

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (105 KB)

    Summary form only given, as follows. The need for known good die for MCMs has been widely recognized. However, satisfying this need has presented many test challenges. Fortunately, the efforts of many workers are now providing the basic technology to assure the performance and reliability of die to be used in MCMs. Performance testing of ICs and chips on wafers is illustrated at gigahertz rates wi... View full abstract»

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  • Test generation with high coverages for quiescent current test of bridging faults in combinational circuits

    Publication Year: 1993, Page(s):73 - 82
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (879 KB)

    Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. T... View full abstract»

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  • Proceedings of IEEE International Test Conference - (ITC)

    Publication Year: 1993
    Request permission for commercial reuse | |PDF file iconPDF (36 KB)
    Freely Available from IEEE
  • Analog circuit testing based on sensitivity computation and new circuit modeling

    Publication Year: 1993, Page(s):652 - 661
    Cited by:  Papers (45)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (928 KB)

    Analog circuit testing is considered to be a very difficult task, due mainly to the lack of fault models and accessibility to internal nodes. An approach is presented for analog circuit modeling and testing to overcome this problem. This circuit modeling is based on a sensitivity computation and on circuit structure, which are crucial in analog circuit testing. The testability of the circuit is ac... View full abstract»

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  • On accurate modeling and efficient simulation of CMOS opens

    Publication Year: 1993, Page(s):875 - 882
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    This paper presents a new modeling and simulation technique for CMOS opens. The significance of the method is that both the hazard and charge-sharing effects of all possible opens are modeled in terms of a set of detecting conditions. They are efficiently represented at logic level. Then during fault simulations only these detecting conditions are evaluated to decide if the opens are detected. In ... View full abstract»

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  • Multiple fault diagnosis in printed circuit boards

    Publication Year: 1993, Page(s):662 - 671
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (788 KB)

    This paper addresses the problems of diagnosing multiple faults occuring in the non-boundary-scan parts of a printed circuit board. The paper details a diagnostic algorithm based upon combining the fault signatures of single faults in order to produce a pattern which best matches the signature of a multiple fault. In addition, a graphical routine is presented which allows the tester to analyze a g... View full abstract»

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  • PSBIST: A partial-scan based built-in self-test scheme

    Publication Year: 1993, Page(s):507 - 516
    Cited by:  Papers (38)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (832 KB)

    Partial-scan based built-in self-test (PSBIST) is a versatile design for testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. While PSBIST provides all the benefits of BIST, it incurs less area overhead and performance de... View full abstract»

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  • Simulation of non-classical faults on the gate level - The fault simulator COMSIM

    Publication Year: 1993, Page(s):883 - 892
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (820 KB)

    COMSIM is a fault simulator for combinational circuits which can efficiently handle various gate level fault models. Stuck-at faults, function conversions, bridging faults, transition faults as well as multiple faults of all types and faults with additional fault detection conditions, can be simulated in one pass. This offers a practical approach to solve the conflict between the accuracy of fault... View full abstract»

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  • The standard mirror boards (SMBs) concept-An innovative improvement of traditional ATE for up to 10 mil bare board testing

    Publication Year: 1993, Page(s):672 - 679
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (592 KB)

    TIM A Laboratory and IMD Test Systems, a division of IMD company, offers a brand new reliable and cost effective solution to access and test bare printed circuit boards (whose pitch can be as low as 10 mils), based on a fixture (mixing standard bed of nail and IMD Standard Mirror Boards (SMBs)). This method allows the user to test very fine pitch PCBs, even with this old standard 100 mils universa... View full abstract»

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  • The impact of commercial off-the-shelf (COTS) equipment on system test and diagnosis

    Publication Year: 1993, Page(s):30 - 36
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    Improved interface standards and reduced design budgets dictate that commercial off-the-shelf (COTS) equipment be more readily integrated into system design. Often COTS is chosen for its functional capabilities and electronic compatibilities with little regard to testability and maintainability features. COTS equipment is often characterized by a lack of detailed information about the specific int... View full abstract»

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  • Hierarchically accessing 1149.1 applications in a system environment

    Publication Year: 1993, Page(s):517 - 526
    Cited by:  Papers (15)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (928 KB)

    This paper presents a novel connection method that enables in 1149.1 test bus controller to hierarchically access and test 1149.1 circuits, independent of where the circuit exists within in an electronic system. The advantage of this approach is that it enables the 1149.1 test bus to be used hierarchically as a system level test bus, instead of only as a board level test bus View full abstract»

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  • Differential virtual instrumentation with continuously variable scale

    Publication Year: 1993, Page(s):893 - 901
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (740 KB)

    Analog test functionality is best incorporated into ATE through use of virtual instrumentation. Real-life applications have shown that simultaneously testing at speed, bandwidth and resolution is unreasonably difficult unless such instrumentation is designed with continuously variable analog scaling and differential connection with the measured world. This paper presents instrument capabilities an... View full abstract»

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  • “In system” transparent autodiagnostics of RAMs

    Publication Year: 1993, Page(s):835 - 844
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (900 KB)

    In this paper we present an original technique of testing classical RAMs (without BIST) in real system environment. The developed testing methodology allows to cover a large class of faults including pattern sensitivity and dynamic faults. An important feature of the presented approach is test transparency which assures that at the end of the test the contents of the RAM are equal to its initial c... View full abstract»

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  • Practical application of statistical process control in semiconductor manufacturing

    Publication Year: 1993, Page(s):99 - 107
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    The application of statistical process control to semiconductor processes is hampered by the complexity of the processes. This paper aims to show intuitively how SPC can be utilized to prevent defects in a manufacturing environment through monitoring of supplier processes View full abstract»

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  • Fault diagnosis of flash ADC using DNL test

    Publication Year: 1993, Page(s):680 - 689
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    This paper describes a technique which uses the differential non linearity (DNL) test data for fault location and identification of the analog components of a flash ADC. In a flash ADC, a fault in the analog subcircuit is uniquely reflected in the transfer function and therefore also in DNL data. This property is exploited to locate a fault and to identify the error value in analog components of t... View full abstract»

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  • Experience in diagnosing a remote, tele-controlled unit using the AITEST expert system

    Publication Year: 1993, Page(s):37 - 44
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (516 KB)

    This paper describes our experience in using a diagnostic expert system (AITEST) for fault isolation, diagnosis and repair action recommendations for a remote, tele-controlled UUT (Unit Under Test). We identify the unique requirements of diagnosis in this class of problems, and explains how these requirements were met in less than three person-months by integrating the expert system with specially... View full abstract»

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  • A comparison of defect models for fault location with Iddq measurements

    Publication Year: 1993, Page(s):1051 - 1060
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (756 KB)

    Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in t... View full abstract»

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  • IEEE P1149.5 to 1149.1 data and protocol conversion

    Publication Year: 1993, Page(s):527 - 535
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    The proposed IEEE P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol Standard addresses hierarchical system test using a four wire (five wire with pause option) serial bus scheme. While the standard adresses many system test and maintenance issues, it is an open ended specification that allows user-defined functionality. With the broad acceptance of IEEE Std 1149.1 Boundary Scan, it i... View full abstract»

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  • BIST for embedded static RAMs with coverage calculation

    Publication Year: 1993, Page(s):339 - 348
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (732 KB)

    The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs. Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strategy. A novel fault coverage calculation method for this self-test strategy has been developed. The me... View full abstract»

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  • Testable programmable digital clock pulse control elements

    Publication Year: 1993, Page(s):902 - 909
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    Digital clock pulse control elements - delay lines and pulse-shaping elements - are used widely for clock generation and clock tuning in synchronous digital logic. However, they are intrinsically redundant circuits: without special modifications, DC logic testing cannot completely verify their static behavior (including the correct operation of the decoders and selectors used for their programming... View full abstract»

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  • Timing analyzer for embedded testing

    Publication Year: 1993, Page(s):552 - 555
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB)

    A 20 channel timing analyzer was designed in CMOS for embedded testing applications. The chip executes independent events in each of the channels at rates of 100 MHz, with a precision of 312.5 ps. The chip automatically adjusts for clock rates from 10 to 100 MHz and temperature/process variations, and can be calibrated to compensate for clock skew View full abstract»

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  • A flexible approach to data collection for component test systems

    Publication Year: 1993, Page(s):461 - 470
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (880 KB)

    Yield improvements for VLSI devices require data collection and analysis during the manufacturing cycle. These data should be collected in a form that satisfies the needs of those performing different functions within the factory. This paper describes an approach to data collection that focuses on collecting test data in a format customized to the users needs. Though implemented on an advanced VLS... View full abstract»

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  • Mutation-based testing of concurrent programs

    Publication Year: 1993, Page(s):845 - 853
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    Mutation-based software testing is a powerful technique for testing software systems. It requires executing many slightly different versions of the same program to evaluate the quality of the test cases used to test the program. Mutation-based testing has been applied to sequential software; however, problems are encountered when it is applied to concurrent programs. These problems are a product o... View full abstract»

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  • Towards a test standard for board and system level mixed-signal interconnects

    Publication Year: 1993, Page(s):300 - 308
    Cited by:  Papers (16)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (532 KB)

    This paper describes basic requirements for a standard bus for testing analog interconnects. The viewpoint is that of prospective users. An architecture for such a standard bus is proposed. The basic conception is of a mixed-signal version of boundary-scan and is compatible with, indeed built upon, ANSI/IEEE Std 1149.1. The goals in mind are the detection of faults and the measurement of analog in... View full abstract»

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