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European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Date 6-9 March 1995

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Displaying Results 1 - 25 of 113
  • Proceedings the European Design and Test Conference. ED&TC 1995

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    Freely Available from IEEE
  • Design and test of the PowerPC 603 microprocessor

    Page(s): 378 - 384
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    The PowerPC 603 microprocessor is a powerful low-cost implementation of the PowerPC architecture specification. The structured design, logic verification and test data generation methodologies of the 603 are presented in this paper. The success of these methodologies has been demonstrated by meeting the 603's aggressive time-to-market goals View full abstract»

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  • Low supply voltage, low noise fully differential programmable gain amplifiers

    Page(s): 105 - 112
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    This paper presents the architecture, methodology, circuit design technique and measured results of a low voltage (2.6 V), fully differential, low-noise, programmable gain “microphone” amplifier, differential bandgap reference and low-voltage programmable gain “power” amplifier. They can be used in a low supply voltage analogue front-end for digital voice terminals. CMOS technology with 1.2 μm channel length is used. The measured equivalent average input referred RMS noise voltage of the microphone amplifier is 5.1 nV/√(Hz) in the voice band at 40 dB closed loop gain. The power amplifier is capable of driving 50 Ω load 200 mV from both supply voltages with distortions better than 0.5% under all conditions View full abstract»

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  • Balancing structural hazards and hardware cost of pipelined processors

    Page(s): 562 - 566
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    In this paper a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that minimizes overall processor cost. In the proposed cost model, processor cost has two components, the cost of hardware necessary to realize the processor and the cost of degraded performance due to pipeline hazards as compared to an ideal pipelined processor. A previous paper detailed the optimization algorithm. This paper extends these results to handle enclosed pairs of instructions having structural hazards. The extended algorithm can produce an optimal result. This algorithm and several examples are presented View full abstract»

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  • TRJM: a high speed programmable ATM-SDH mapper

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    Presents the design of the TRJM integrated circuit. This ASIC has been developed to implement the ATM transmission convergence sublayer interfaces for different SONET rates and its SDH equivalents. The chip has been manufactured using a standard cell 0.6 microns 3-layer metal CMOS technology. It contains 350,000 transistors split in 42 K gates and 18 Kbit from dual port RAM View full abstract»

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  • Low-voltage low-power switched-current circuits and systems

    Page(s): 100 - 104
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    This paper presents low-voltage low-power switched-current circuits and systems. Novel class AB configuration and common-mode feedforward are the essence. A delay line, memory cell, oversampling A/D converter, and chopper-stabilized oversampling A/D converter were designed and implemented. Measurement results are presented as well View full abstract»

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  • Automatic test vector generation for mixed-signal circuits

    Page(s): 458 - 463
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    Mixed circuit testing is known to be a very difficult task. This is due to the difficulty of: testing the analog part of the circuit, controlling the digital signal from the analog outputs, observing the analog outputs in the digital circuit, controlling the analog circuit from the digital outputs and observing the digital signals in the analog circuit. As a solution to these problems, we propose an automatic test vector generation for mixed circuits to perform functional testing. In this paper, a case of an analog block followed by a digital block is considered. The experimental results (simulation and discrete realization) show the efficiency of the automatic test generation technique View full abstract»

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  • A BIST approach to delay fault testing with reduced test length

    Page(s): 418 - 423
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    A cost-effective built-in self testing (BIST) method for the detection of delay faults is presented. A multiple-input signature register (MISR) with a constant parallel input vector is used as a test pattern generator. To reduce the test length of the MISR, a two-step approach is proposed. First, deterministic delay test generation is employed to determine a set of two-pattern tests which detect all testable path delay faults. Second, a minimal number of constant MISR input vectors is calculated such that the state sequences generated by the MISR include the pre-determined test set. The second step is formulated as a set covering problem. As the number of MISR input vectors may be exponential in the number of stages of the MISR, their calculation and the set covering are performed implicitly with BDDs. Experimental results reveal that in almost all considered cases a maximum robust path delay fault coverage is obtained with less than 100 MISR input vectors View full abstract»

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  • PPS: a pipeline path-based scheduler

    Page(s): 557 - 561
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    This paper presents a scheduling algorithm that improves on other approaches when dealing with the synthesis of control-flow dominated behavioral descriptions. It achieves this through the use of a constraint-driven path-based scheduling algorithm. The suboptimality of the original path-based algorithms when dealing with loops is overcome through a new technique for pipelining different loop iterations during execution path generation. Results show that the algorithm always generates the fastest solution in terms of clock cycles View full abstract»

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  • Exact scheduling strategies based on bipartite graph matching

    Page(s): 42 - 47
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    Scheduling is one of the central tasks in high-level synthesis. In recent publications a bipartite graph matching formulation has been introduced to prune the search space of schedulers. In this paper, we improve that formulation and introduce two novel aspects related to the way the search space is traversed, namely problem formulation and bottleneck identification. The approach results in a very run time efficient branch-and-bound scheduler searching for a correct ordering of operations from which a schedule can be derived in linear time. The results show that the use of these bipartite graph matching strategies leads to the most run time efficient exact scheduler to date View full abstract»

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  • Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis

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    Although the Fault Dictionary (FD) is one of the oldest approaches in analogue fault diagnosis, it is the most used in industrial environments. We present a fully automatic system that selects a minimum set of test nodes and gives the range of their voltages for each fault. All the information it uses is in three input files given by the test engineer: the circuit description (similar to the SPICE), the fault list and the tolerance file View full abstract»

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  • Run-time consistency checking in discrete simulation models

    Page(s): 223 - 227
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    A new and efficient method is presented to improve the validation capabilities of a discrete event simulator. Discrete event monitors are introduced as a means to analyse event traces during a simulation run. This facilitates the defection and location of erroneous behaviour in a design specification. Furthermore, a specification language for discrete event monitors is described and it is shown how this language facilitates the integration of other specification methods. Experimental results are presented to demonstrate the efficiency of the proposed techniques View full abstract»

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  • High speed communications links for ASICs

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    Summary form only given. ASIC integration and speeds have risen rapidly in the past couple of years to the point now where 50 to I00 MHz clock rates and hundreds of thousands of used gates are commonplace. These performance and integration levels place huge demands on chip-to-chip data transfer and packaging, with communications rates of up to 1 Gbit/sec being required. The author compares some of the traditional I/O standards available to an ASIC designer such as TTL, CMOS with some of the more recent advances such as PECL, GTL, and LVDS. Design considerations and limitations of these modern schemes are explored View full abstract»

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  • Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions

    Page(s): 91 - 97
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    In this paper a polynomial time algorithm for the minimization of Fixed Polarity Reed-Muller Expressions (FPRMs) for totally symmetric functions based on Ordered Functional Decision Diagrams (OFDDs) is presented. A generalization to partially symmetric functions is investigated. The algorithm has been implemented as the program Sympathy. Experimental results in comparison to previously published methods are given to show the efficiency of the approach View full abstract»

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  • Pseudo-exhaustive word-oriented DRAM testing

    Page(s): 126 - 132
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    This paper presents a new methodology for RAM testing based on the PS(n,k) q-ary fault model (q=2w) which includes most classical fault models for SRAMs and DRAMs. According to this fault model, the contents of any w-bit memory word of a memory with n words, or ability to change this contents, is influenced by the contents of any other k-1 words of the memory. The proposed methodology uses a pseudo-exhaustive technique based on Reed-Solomon codes, which can be efficiently applied to a word-oriented RAMs, assuming small values of k. The methodology ensures the detection of any number of disjoint (not linked) k-coupling faults, whereby the involved k words may be located anywhere in the memory; i.e., no assumptions have to be made on the physical topology of the cells in the memory cell array because of the systematic structure of the proposed tests, they are well suited for BIST implementations View full abstract»

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  • Post-layout optimization of power and timing for ECL LSIs

    Page(s): 167 - 172
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    An optimization algorithm for power and timing of bipolar ECL LSls is proposed. The power dissipation is minimized by a nonlinear programming solver under accurate timing constraints extracted from layout. The power and delay time of an ECL gate are considered functions of its switching current which is regulated by programming its resistors. Experimental results show significant power reductions for circuits including a real chip without degrading the performance View full abstract»

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  • Defect-oriented test methodology for complex mixed-signal circuits

    Page(s): 18 - 23
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    Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present specification-oriented testing of these blocks results in high test costs and doesn't ensure detection of all defects, causing potential reliability problems. To solve these problems, in this paper a defect-oriented test methodology for mixed analog-digital circuits is proposed. The strength of the method is demonstrated by an implementation for a complex mixed-signal circuit, a flash analog-to-digital converter. It is shown that with simple tests 93% of the defects in this circuit can be detected. Moreover application of DfT guidelines derived from this test methodology may improve the defect coverage to 99%. First impressions lead to the conclusion that the analyzed test obtains a higher defect coverage with lower test costs than functional tests View full abstract»

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  • Combining MBP-speculative computation and loop pipelining in high-level synthesis

    Page(s): 550 - 556
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    Frequent control dependencies caused by IF- and loop-statements limit the parallelism usable in High-Level Synthesis. Loop pipelining is a powerful way to increase parallelism, but is often limited by these control dependencies. Multiple branch prediction (MBP-SC) applies loop pipelining and speculative computation to the most probable path and serves other paths during the restore phase (prediction error correction). In this paper we combine MBP-SC and loop pipelining and give a scheduling algorithm. Further MBP-SC improvement comes from parallel branch execution. The results show a considerable speedup compared to previous approaches View full abstract»

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  • A unified scheduling model for high-level synthesis and code generation

    Page(s): 234 - 238
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    Scheduling is an essential task both in high-level synthesis and in code generation for programmable processors. In this paper we discuss the impact of the controller model on the scheduling task for DSP applications. Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. In this paper, a unified scheduling model is presented to handle a wide range of controller architectures,from the application-specific to programmable processor solutions. The impact of choosing a certain controller architecture on the scheduling phase is investigated. Finally, the tasks of controller generation and code assembly are discussed, which will generate the FSM or machine code description from the correct schedule View full abstract»

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  • Mixed-signal circuits and boards for high safety applications

    Page(s): 34 - 39
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    A design methodology for analogue on-line test is presented by means of a real circuit implementation. The test strategy is based on monitoring via a very small analogue checker the inputs of all operational amplifiers of a fully differential circuit. The self-checking properties of the functional circuit are evaluated for a hard/soft fault model. Since the analogue checker outputs a double-rail error indication, the compatibility with digital checkers is ensured and the design of self-checking mixed-signal circuits becomes very simple. The mixed-signal approach as extended to boards through the IEEE Std. 1149.1 digital test bus and a layout rule to avoid interconnect differential shorts View full abstract»

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  • Test preparation methodology for high coverage of physical defects in CMOS digital ICs

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    The constant increase of IC circuit complexity and quality requirements make high quality testing a difficult challenge. In this work, a methodology for test preparation leading to high physical defect coverage is proposed. Two new software tools are presented, that implement the proposed methodology, tabloid and iceTgen. From the gate level schematics, a heuristic is proposed to generate a list of pseudo-realistic faults that, when used as target faults for test pattern generation, lead to high coverage of physical defects with a shorter test sequence than the one generated using realistic faults extracted from the layout View full abstract»

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  • Functional test for shifting-type FIFOs

    Page(s): 133 - 138
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    FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing use of FIFOs, as a stand-alone chip or as embedded macros in ASICs, generic algorithms are needed to test FIFOs. This paper addresses the problem of testing the widely available shifting-type FIFOs; it introduces specific fault models and a set of generic tests which have a test length of O(n) and can be used for the stand-alone chip as well as for the embedded macro version of the FIFO View full abstract»

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  • Mixed-signal modelling in VHDL for system-on-chip applications

    Page(s): 218 - 222
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    Function transfer based modelling techniques are applied to the IEEE VHDL language to develop behavioral analogue models. This allows mixed-signal simulations integrated into a top-down ASIC design flow for system designers. An application to a clock module for a DSP-core ASIC, integrating a Phase-Locked Loop, demonstrates the usefulness of such an approach for the validation of large systems containing a small portion of analogue functionalities View full abstract»

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  • A built-in quiescent current monitor for CMOS VLSI circuits

    Page(s): 581 - 585
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    A built-in IDDQ monitor for CMOS digital circuits with low power supply voltage perturbation is presented. It minimizes the extra delay of the CUT in normal operation. An automatic recovery mechanism limits the drop in VDD voltage during the testing phase so the data storage is not perturbed. The IDDQ current level may be measured by a standard digital IC tester. The performance parameters are compared with other published circuits and experimental results of an ASIC with the proposed BIC monitor are discussed View full abstract»

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  • Improved sequential ATPG using functional observation information and new justification methods

    Page(s): 262 - 266
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    Sequential ATPG (Automatic Test Pattern Generation) is a very desirable CAD tool, but to date, the site and complexity of circuits for which sequential ATPG could be performed has been limited. We have discovered a method for collecting functional information which makes fault observation significantly easier. We also propose a new method for state justification which is a combination of function-based methods and structure-based methods. Our sequential ATPG system deals with circuits without a reset state or a synchronizing sequence, and the experimental results show that the proposed method achieves significant improvements over existing sequential ATPG methods View full abstract»

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