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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Issue 2 • Date June 1981

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Displaying Results 1 - 15 of 15
  • Foreword

    Publication Year: 1981 , Page(s): 165
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    Freely Available from IEEE
  • Correction to "Computerized Thermal Analysis of Hybrid Circuits"

    Publication Year: 1981 , Page(s): 230
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  • Correction "Connector Finishes:Tin in Place of Gold"

    Publication Year: 1981 , Page(s): 230
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  • Humidity Test of Premolded Chip Carriers

    Publication Year: 1981 , Page(s): 210 - 213
    Cited by:  Papers (4)
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    Premolded chip carrier packages made by AMPl containing test chips coated with various protective materials were humidity-tested at 85°C/85 percent relative humidity (RH) with a 40-V dc bias for 1000 h. The test chips were also packaged in plastic dual in-line packages (DIP's), and ceramic DIP's and tested at the same time for comparison. The purpose of this test was to gather preliminary information on the suitability of the premolded chip carrier as a semiconductor package. As expected none of those in the hermetic packages failed. The test chips in the chip carrier with protective coatings survived better than those in the plastic DIP's, and one of the chip carrier groups had no failures. The data are sufficiently encouraging to recommend continued development and testing of premolded packages. View full abstract»

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  • High Density Multiwire Circuits Using Thinner Wires

    Publication Year: 1981 , Page(s): 224 - 229
    Cited by:  Papers (2)  |  Patents (1)
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    High density Multiwire circuit technology which can lay two insulated wires between throughholes on 2.5 mm centers has been developed. To reduce crosstalk smaller diameter wires were adopted instead of conventional 0.16 mm diameter wires. Wire breakage and wiring mistakes, which occur in high density wiring, can result from improper wire tacking. A newly developed tackless wiring technique can reduce these problems. The new technology has been applied to backplane wiring boards in an electronic switching system. View full abstract»

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  • Packaging Trade-Offs for an LSI-oriented Very High-Speed Computer, the HITAC M-200H

    Publication Year: 1981 , Page(s): 166 - 172
    Cited by:  Papers (3)
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    Hardware technologies used and design considerations behind important design decisions in the development of the generalpurpose very high-speed computer, HITAC M-200H, are outlined. The logic and memory make extensive use of large-scale integration (LSI) technology. Trade-offs in LSI application to random logic result in the use of 416 circuit, 0.7 ns emitter-coupled logic (ECL) masterslice LSI's for most of the processor logic. The advanced cardon-board system combined with forced air cooling accommodates 70K circuits per board on the average, and permits up to 1.7 kW power dissipation per backboard, wiring channel capacities of masterslice LSI's and logic cards are optimized based on wireability studies. A signal-delay prediction and critical path-delay check system is developed to point out bad paths that will require longer than the permitted delays, prior to the actual building of the machine. These technologies give the M-200H a machine cycle time of less than 40 ns and a processor performance of more than eight million instructions per second (M!PS). View full abstract»

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  • Graphical Solution for the Back Pressurization Method of Hermetic Test

    Publication Year: 1981 , Page(s): 217 - 224
    Cited by:  Papers (1)
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    The back pressurization method for leak-testing hermetically sealed electronic packages requires gas-flow modeling to relate indicated leakage rates to true leak size. The molecular flow relationship which is appropriate for fine leak sizes is nonlinear and requires a numerical solution, which in actual test application may involve either many trial calculations or the use of approximations that lead to limiting case values. A new graphical procedure is presented for complete solution of the molecular flow equation for any given test condition and package volume through the use of a single set of characteristic curves and a test line. The effects of repetitive testing and of prefill with tracer gas are also considered. The characteristic curves are appropriate for both the helium leak detector and the radioisotope methods of test, while the form of the test line distinguishes between the two methods. View full abstract»

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  • Low Energy LSI and Packaging for System Performance

    Publication Year: 1981 , Page(s): 173 - 180
    Cited by:  Papers (9)
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    By defining "power.time products" of digital functional blocks, processor performance can be quantitatively expressed by a parameter which is the product of equivalent energy UB and the thermal resistance RthetaB. The reduction of UB.RthetaBthrough systemoriented large-scale integration (LSl) technology in both chips and packaging is necessary for raising the level of system performance. Using this concept the correlation between gate energy levels for chips, packages, and processors in a hierarchy have been illustrated in four energy levels of gates: microjoule, 100 pJ, picojoute, and subpicojoule. The low energy current-mode logic (CML) chips and multichip packaging for the NEC ACOS series have been developed to reduce system energy through advanced LSI technology for their high performance. View full abstract»

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  • Chip Carrier Applications

    Publication Year: 1981 , Page(s): 192 - 195
    Cited by:  Papers (1)
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    The chip carrier package is gaining acceptance as a largescale integration (LSI) and very large-scale integration (VLSI) circuit package which can be integrated with medium-scale integration (MSI), small-scale integration (SSI), and passive components onto conventional printed wiring boards. In addition, the chip carrier package is being used to manufacture high density small modules which can be used as stand-alone functions or interfaced with conventional printed circuit boards as modular building blocks. In manufacturing high density small ceramic modules with devices in chip carriers, a soft assembly and test approach has been found to be useful during the start-up phase of a new product. View full abstract»

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  • Testing of Properties for Soldered Leadless Chip Carrier Assemblies

    Publication Year: 1981 , Page(s): 200 - 205
    Cited by:  Papers (1)  |  Patents (1)
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    The use of leadless chip carriers in soldered assemblies represents a relatively new device packaging/interconnection technology. There is little published material treating any of the physical properties of the solder attachment in a quantitative fashion. The application of leadless hermetic chip carriers to high reliability microelectronics prompted a joint preliminary investigation by RCA and Sandia Laboratories to quantitatively characterize the solder assembly interface. It was determined that the mechanical and electrical integrity of the soldered connections could best be assured by measuring the yield strength and electrical resistance versus different fabrication conditions and environmental stresses. Sandia devised a program for parallel sample preparation and testing by both RCA and Sandia Laboratories. This program also included tests to evaluate the thick film material system which will not be reported here. The preparation of samples and the design of methods and fixtures for test!ng the yield strength of the soldered connections under lap shear is described. The measurements reported include values corresponding to controlled variation in fabrication and processing parameters and the different environmental stress conditions. While the sample sizes are quite modest, the methods and fixturing are believed to be of general interest, and the various values found for the yield strength and resistance provide a good indication of the magnitude of the influences of the various processing and environmental stress conditions on the integrity of soldered chip carrier assemblies. The measurement values reported were performed by RCA under contract to Sandia Laboratories and the values appear to correlate with those obtained at Sandia for the same sets of conditions. View full abstract»

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  • Chip Carriers-Their Application and Future Direction

    Publication Year: 1981 , Page(s): 195 - 199
    Cited by:  Papers (4)  |  Patents (1)
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    The need for chip carriers and chip-carrier standards is reviewed. Chip-carrier telecommunications applications as well as thermal characteristics of chip carriers are presented. Impediments to chip-carrier applications as well as future directions are reviewed. View full abstract»

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  • Terminal and Cooling Requirements for LSI Packages

    Publication Year: 1981 , Page(s): 187 - 191
    Cited by:  Papers (3)
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    As the level of digital circuit integration on integrated circuit (IC) chips increases, more input-output (I/0) terminals are required on the chip package. More terminals mean a larger conventional package. This can frustrate achievement of higher overall gate density on the printed circuit (PC) board assembly. Chip packages providing terminals as a function of package area or at reduced terminal pitch offer some relief. Gate density may also be thermally limited. Coefficient and exponent values are empirically derived for the Rent equation to predict terminal requirements. A graphical means is developed which can help the designer visualize the trade-offs between package type, terminal pitch, and cooling requirements. Some practical examples are described. View full abstract»

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  • Migration of Silver from Silver-Loaded Polyimide Adhesive Chip Bonds at High Temperatures

    Publication Year: 1981 , Page(s): 214 - 216
    Cited by:  Papers (6)
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    A degradation mechanism found at high temperatures in a commercial silver-loaded polyimide chip adhesive is discussed. The adhesive was used to attach semiconductor diodes to headers for potential use in the geothermal well probe program. Aging the mounted devices at 300°C for 1100 h resulted in a bias dependent migration of the silver out of the adhesive. This effect was accompanied by an increased series resistance and weakened bond strength. View full abstract»

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  • Low Cost Chip Carriers for the 1980's

    Publication Year: 1981 , Page(s): 205 - 209
    Cited by:  Papers (1)  |  Patents (1)
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    Most industry people are projecting an accelerated market penetration in the 1980's for the various forms of chip carriers as laid out by the Joint Electron Device Engineering Council (JEDEC) JCII-3 committee. Many papers have been written promoting its advantages over the old reliable dual in-line package (DIP)-advantages like size, weight, thermal, electrical, and reliability. A novel approach for low cost leaded chip carriers, centered within the JEDEC standards, in both hermetic and plastic versions is outlined. By careful utilization of precious metals, hardware commonality, and process simplification, savings of up to 50 percent can be achieved over present-day chip carrier costs. After a review of chip carrier parameters, both necessary and desirable, an outline of Bell Northern Research's (BNR's) solution highlighting hardware design, flow charts, test results, and comparative material costs curves is pre- sented. View full abstract»

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  • CRAY-1 Computer Technology

    Publication Year: 1981 , Page(s): 181 - 186
    Cited by:  Papers (5)  |  Patents (1)
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    Hardware and packaging technology which provide the high performance of the CRAY-I computer are reviewed. A brief overview of the computer is given, followed by a description of the computer circuits, packaging, power distribution, and cooling system. View full abstract»

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Aims & Scope

This Transaction ceased production in 1993. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope