[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

4-8 Jan. 1991

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  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

    Publication Year: 1991
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    Freely Available from IEEE
  • A practical approach to synchronous hardware verification

    Publication Year: 1991, Page(s):180 - 186
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    Hardware designs expressed in a simple hardware description language can be formally verified by adapting techniques developed for software verification. This paper presents a case study that supports this claim. From the structural specification of a two-phase clocked synchronous hardware design, a behavioral description is automatically inferred. This is subject to algebraic simplification using... View full abstract»

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  • New results on channel routing

    Publication Year: 1991, Page(s):174 - 179
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    Presents a new routing concept which guides the selection of wire segments in track-by-track fashion by inspecting the effects of the endpoints of each selected wire segment to column density and vertical constraint graph of the given channel routing problem. This new routing concept has been implemented in the two-layer and three-layer routers. The routing performance of the developed two-layer a... View full abstract»

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  • Modified interval line representation and its applications to planar routing problems

    Publication Year: 1991, Page(s):168 - 173
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    A modified interval line representation is proposed. This representation makes it possible to speed up some heuristics and algorithms for planar routing problems. This technique is illustrated by speeding up the heuristic proposed by Tsukiyama and Kuh for the double row routing problem. The heuristic suggested by Tsukiyama and Kuh for double row routing problem, can be implemented in O(n2 View full abstract»

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  • An overlap model for routing

    Publication Year: 1991, Page(s):163 - 167
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    Describes a new approach to routing in two layers using the overlap model of layer assignment. The overlap model allows tracks to be laid on top of each other as permitted by the real design rules. The technique is very simple and elegant with results more compact than the optimal solutions under the directional model and with at most one via per subnet. It is illustrated here in the context of ov... View full abstract»

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  • Pipelined concurrent simulation on distributed-memory parallel computers

    Publication Year: 1991, Page(s):63 - 68
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    Presents a space- and time-efficient approach to fault simulation on distributed-memory message-passing parallel computers. The processors in the parallel machine, and the host, communicate in a pipelined fashion where each processor simulates only one partition of the circuit under consideration using the concurrent simulation approach. If good load balancing can be obtained, this approach leads ... View full abstract»

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  • A novel technique for folding logic arrays

    Publication Year: 1991, Page(s):100 - 105
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    The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optim... View full abstract»

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  • Overlap elimination in floorplans

    Publication Year: 1991, Page(s):157 - 162
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    Describes an algorithm for eliminating/reducing overlaps among blocks (macros) in VLSI chip floorplans. These blocks are assumed to be rectangular and can be either preplaced or movable. A movable block can have a fixed or a flexible shape. The authors describe applications for such an algorithm in the floorplanning process. The approach discussed in the paper is targeted towards macro cell based ... View full abstract»

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  • Can test length be reduced during synthesis process?

    Publication Year: 1991, Page(s):57 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (336 KB)

    Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis ... View full abstract»

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  • A novel VLSI solution to a difficult graph problem

    Publication Year: 1991, Page(s):124 - 129
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    Presents a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. The solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the n... View full abstract»

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  • Method for testable design and for built-in test

    Publication Year: 1991, Page(s):286 - 287
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    The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit View full abstract»

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  • A Monte Carlo simulation environment for wear out in VLSI systems

    Publication Year: 1991, Page(s):249 - 254
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switchin... View full abstract»

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  • A new approach for multilevel logic cell optimization

    Publication Year: 1991, Page(s):94 - 99
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    Presents new ideas in the field of multi-level logic optimization for automatic logic macrocell synthesis. A new approach is proposed which performs a quasi-parallel optimization of very different and complex tasks via a simulated annealing based expert system. A first working prototype software package for multilevel logic cell optimization had been implemented to prove the validity of this appro... View full abstract»

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  • An algorithm for minimising the number of test cycles

    Publication Year: 1991, Page(s):154 - 156
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (208 KB)

    The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain ... View full abstract»

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  • Synthesis of multiple outputs CMOS gates

    Publication Year: 1991, Page(s):51 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (508 KB)

    Design of static CMOS gates for multiple output functions is presented. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named delta and lambda networks. Design examples on double output functions are provided. It is shown that the two techniques can be combined togethe... View full abstract»

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  • Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

    Publication Year: 1991, Page(s):118 - 123
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    An approach to carving circuit partitions starting and stopping at controllable and observable points using high-level primitives is described. This approach allows considerable speed up over gate level partitioning. The minimum set of properties to accommodate multi-input, multi-output primitives is presented. The approach is both memory efficient and fast allowing for both deterministic and inte... View full abstract»

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  • A class of hierarchical networks for VLSI/WSI based multicomputers

    Publication Year: 1991, Page(s):267 - 272
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB)

    A class of hierarchical networks is proposed for multicomputer implementation using VLSI and wafer scale integration (VLSI/WSI). These networks, called DBCube, connect clusters of cube topology based nodes with a De Bruijn graph. The nodes are identical and can be easily extended to a larger size. The cube topology for local communication allows easy embedding of parallel algorithms and the De Bru... View full abstract»

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  • A neural network for channel routing

    Publication Year: 1991, Page(s):277 - 278
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (124 KB)

    The authors propose a neural network to handle the channel routing problem. This network also allows the user to preroute critical nets and then invoke the network to complete the rest. Typical examples from published literature are taken for experiments. The theoretic lower bounds are achieved in all examples View full abstract»

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  • Development of TTL equivalent library for ASIC design tools and its use to design printer adapter interface ASIC

    Publication Year: 1991, Page(s):283 - 284
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (148 KB)

    The authors describe development of TE74XX (TTL functional equivalent) library cells for ASIC design tools on Sun SPARCStation1 (model14/110). The functionality of TE74XX series cells is confirmed through exhaustive simulation using mixed-mode simulator VTISim and complete documentation is prepared. Applicability of TE74XX library is demonstrated by designing a 40-pin PAI (Printer Adapter Interfac... View full abstract»

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  • Defect and design error location procedure-theoretical basis

    Publication Year: 1991, Page(s):243 - 248
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (392 KB)

    In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms View full abstract»

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  • Design and performance evaluation of high-resolution oversampling A/D converters

    Publication Year: 1991, Page(s):297 - 298
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (156 KB)

    An approach to the behavioural simulation of ΣΔ A/D converters is presented. Integrator, comparator and digital filtering blocks are implemented with the advantage of being easily interfaced with component designers. Post-processing algorithms for overall performance evaluation are also discussed, specially by focusing on the fact they can largely affect the meaning of the results. Sim... View full abstract»

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  • Elements of a design framework for module generators design and usage

    Publication Year: 1991, Page(s):88 - 93
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Presents a procedural layout description language ALL and elements of design environment that supports it. Language capabilities in defining module generators are shown. Ways of integrating textual and graphical layout representations are presented. A proposal of language implementation based on object-oriented paradigm is discussed View full abstract»

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  • A new test scheduling algorithm for VLSI systems

    Publication Year: 1991, Page(s):148 - 153
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results View full abstract»

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  • A scan-based BIST technique using pair-wise compare of identical components

    Publication Year: 1991, Page(s):225 - 230
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a r... View full abstract»

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  • A simulated annealing based state assignment approach for control synthesis

    Publication Year: 1991, Page(s):45 - 50
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    The optimality of synthesized control designs for complex VLSI systems hinges to a great extent on the efficiency of the state assignment phase. A new system is presented for state assignment of sequential functions modelled as finite state machines. Using a simulated annealing technique and an embedded mechanism to vary the state assignment length, this scheme arrives at a synthesized logic that ... View full abstract»

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