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VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Date 4-8 Jan. 1991

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Displaying Results 1 - 25 of 62
  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

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  • Method for testable design and for built-in test

    Page(s): 286 - 287
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    The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit View full abstract»

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  • Multilevel simulation tool for designing fault-tolerant VLSI array processors

    Page(s): 293 - 294
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    The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural simulator which is embedded into an environment supporting array processor design. One of the most important features of this CAD tool is that advanced fault-tolerance techniques can be incorporated in an early design phase not only to achieve high reliability and long life time but also to enhance production yields View full abstract»

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  • A novel technique for folding logic arrays

    Page(s): 100 - 105
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    The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optimal solution for both simple and multiple folding of logic arrays. The algorithms developed have been implemented in a computer program called GAMIN-SA. When compared to PLEASURE, GAMIN-SA was seen to perform as good or better with regard to quality of solution and, for the bigger PLAs (multiple folding), it was better in terms of run-time as well View full abstract»

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  • A Monte Carlo simulation environment for wear out in VLSI systems

    Page(s): 249 - 254
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    The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switching activity is collected. This data is then used along with Monte Carlo simulation to model wear-out at the chip-level View full abstract»

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  • PLATEST: A PLA test generator

    Page(s): 288 - 289
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    The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS) View full abstract»

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  • A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies

    Page(s): 290 - 292
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    A novel test structure has been designed to electrically measure the misalignment between polysilicon and the active area in MOS technologies. This alignment is one of the most critical alignments in small geometry integrated circuit processing. The structure exploits the channel width change of specially designed MOS transistors resulting from the misalignment between the active area and polysilicon layers to develop a proportionate differential current sensing arrangement. A calibrating structure is used to translate the measured differential current to actual microns View full abstract»

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  • ATPG with efficient testability measures and partial fault simulation

    Page(s): 35 - 40
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    Proposes an improved version of the test generation algorithm PODEM path oriented decision-making incorporating a different technique for backtracing and forward implication. The authors also propose a partial fault simulator which is integrated into the improved PODEM algorithm. The performance of this test generation package (when partial fault simulator is employed) is compared to that of a concurrent fault simulator using deterministically generated test patterns. It is shown that the runtime performance of the algorithm compares favourably with that of the concurrent fault simulator and is less memory intensive. The authors also present effective heuristics to determine some of the redundant faults and to drive the test vectors for some PI faults, by the use of implication relations. Experimental results on all the 10 ISCAS benchmark circuits demonstrate that the algorithm is faster and more efficient than the PODEM algorithm for these circuits View full abstract»

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  • Modified interval line representation and its applications to planar routing problems

    Page(s): 168 - 173
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    A modified interval line representation is proposed. This representation makes it possible to speed up some heuristics and algorithms for planar routing problems. This technique is illustrated by speeding up the heuristic proposed by Tsukiyama and Kuh for the double row routing problem. The heuristic suggested by Tsukiyama and Kuh for double row routing problem, can be implemented in O(n2rlg r) time algorithm, whereas the implementation suggested by Tsukiyama and Kuh requires O(n3r) time. It is also shown that the heuristic can be implemented in parallel in O(lg2n+lg r) time using O(N 4+n2r) processors on the concurrent read exclusive write (CREW) model View full abstract»

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  • A multilayered VLSI array design for multistage interconnection network

    Page(s): 295 - 296
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    The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation View full abstract»

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  • Partitioning and reorganization of hierarchical circuits for DFT

    Page(s): 106 - 111
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    To make VLSI circuits more testable, design-for-testability (DFT) and built-in self-test (BIST) techniques are often employed. These techniques typically assume a register/gate level decomposition of the overall circuit. In general, the given user hierarchy is not appropriate for embedding various testable design methodologies (TDMs). This paper describes a new canonical partitioning of a circuit into disjoint subcircuits, referred to as clouds and registers. A salient feature of this partitioning is the attempt to preserve the user hierarchy as much as possible. This enables easy identification of equivalence among various clouds of the circuit. The authors also show how this canonical partitioning can be used for three specific TDMs, namely full scan, partial scan and BILBO designs. For the case of full scan, deterministic tests are generated for one cloud in each equivalence class, and replicated for all clouds in that class. These tests are organized to form a test set for the entire circuit. Test vectors are edited to correspond to the order of flip-flops in the scan paths of the circuit. Analytical expressions for the reduction in the number of test vectors due to this canonical partitioning are derived and substantiated with experimental results View full abstract»

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  • Simulator for IDEAL-implementation and environment

    Page(s): 187 - 194
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    Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately scheduling coroutines corresponding to the design entities. The behavioral and structural description is translated into coroutines by compiling IDEAL data transfer and control constructs into `C'. The semantics of IDEAL constructs are discussed and the simulator implementation and supporting environment are described View full abstract»

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  • A new test scheduling algorithm for VLSI systems

    Page(s): 148 - 153
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    Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results View full abstract»

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  • Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

    Page(s): 118 - 123
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    An approach to carving circuit partitions starting and stopping at controllable and observable points using high-level primitives is described. This approach allows considerable speed up over gate level partitioning. The minimum set of properties to accommodate multi-input, multi-output primitives is presented. The approach is both memory efficient and fast allowing for both deterministic and interactive heuristic partitioning at the system level. Partitioning is orthogonal to test generation, and the best scan test generator can still be used on the generated scan targets. Practical application of the approach for the system level scan test generation of the Apollo DN10000 and its CPU upgrade, both designs of more than a million gates, are presented. Evolution of the techniques to accommodate new technology will be addressed. Partitioning for test generation for both stuck-at and delay faults are addressed View full abstract»

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  • Yield and layout issues in fault tolerant VLSI architectures

    Page(s): 255 - 260
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    Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique View full abstract»

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  • Signal delay in linear leaky RC mesh/tree

    Page(s): 195 - 199
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    As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions View full abstract»

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  • Fault detection in DCVS circuits

    Page(s): 29 - 34
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    Dynamic CMOS circuits are known to be easier to test, in general, than static CMOS circuits. Differential cascode voltage switch (DCVS) logic belongs to the dynamic CMOS logic family. No comprehensive results on deterministic testing of DCVS circuits have been presented previously. This paper discusses the detection of stuck-open, stuck-on and stuck-at faults in these circuits. A test set which detects all single stuck-on faults in the functional sections of the DCVS gates in the circuit can also be guaranteed to detect all multiple stuck-on, multiple stuck-open and unidirectional stuck-at faults in these sections, even when the faults are not confined to the functional section of a single gate. All detectable faults in the precharge, access and buffer transistors are also detected by the test set View full abstract»

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  • CLSS-a workbench for control logic synthesis

    Page(s): 219 - 224
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    Describes a system called CLSS, that serves as a workbench for the synthesis of control logic. The system provides an integrated solution to the designer by providing effective solutions for all the major steps in the control logic synthesis flow. CLSS allows specification of the control logic in the form of a state transition representation. Through a set of transformation steps, all of which are an integral part of the CLSS workbench, the layout of the design is generated for standard cell or PLA based implementations. In addition to providing automated solutions to optimally perform state assignment, logic minimization, constrained area-delay optimization, etc., CLSS provides a mechanism for the expert designers to override the decisions taken by the system. The major strength of the system lies in the tight coupling between the several components of the flow in an integrated environment. Designed at Texas Instruments, the CLSS workbench has been successfully used on several large and realistic designs View full abstract»

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  • New results on channel routing

    Page(s): 174 - 179
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    Presents a new routing concept which guides the selection of wire segments in track-by-track fashion by inspecting the effects of the endpoints of each selected wire segment to column density and vertical constraint graph of the given channel routing problem. This new routing concept has been implemented in the two-layer and three-layer routers. The routing performance of the developed two-layer and three-layer routers has overwhelmingly outperformed all the currently existing two-layer and three-layer routers in most examples in the literature as shown in experimental results View full abstract»

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  • An algorithm for minimising the number of test cycles

    Page(s): 154 - 156
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    The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain conditions View full abstract»

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  • A novel VLSI solution to a difficult graph problem

    Page(s): 124 - 129
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    Presents a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. The solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the neural network model of the logic circuit. Each input vector provides one solution of the independent set problem. The independent set consists of only vertices with true encoding. This new methodology has the potential of solving the problem in real time if programmable logic is used View full abstract»

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  • State machine design-an interactive approach

    Page(s): 41 - 44
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    Finite state machines are essential components in digital systems. This paper describes a tool for designing a finite state machine from its behavioral description. Useful user interfaces for describing a state machine and for verification of its behavior are the important contributions made in this paper View full abstract»

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  • A new processor interconnection structure for fault tolerant processor arrays

    Page(s): 261 - 266
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    Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the traditional design for restructuring a rectangular array. Because interconnection of a fault tolerant processor array occupies a substantial chip area, especially for large word parallel systems, this will significantly improve the overall performance of the processor arrays in VLSI/WSI View full abstract»

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  • Can test length be reduced during synthesis process?

    Page(s): 57 - 62
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    Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis process has been modified to obtain circuits that can be tested with smaller test length. Results of the implementation have shown significant reduction in test length with little increase in run time over the MIS-II synthesis system and very little increase in literal count View full abstract»

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  • A class of hierarchical networks for VLSI/WSI based multicomputers

    Page(s): 267 - 272
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    A class of hierarchical networks is proposed for multicomputer implementation using VLSI and wafer scale integration (VLSI/WSI). These networks, called DBCube, connect clusters of cube topology based nodes with a De Bruijn graph. The nodes are identical and can be easily extended to a larger size. The cube topology for local communication allows easy embedding of parallel algorithms and the De Bruijn graph provides shortest distance among different clusters. The authors compare the DBCube with other networks in terms of topological properties. They compute the silicon area requirement of DBCube. The DBCube topology is such that testing of the network before metallization make it easily configurable to DBCube of smaller size. Potential extension of the DBCube is also addressed View full abstract»

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