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VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Date 4-8 Jan. 1991

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Displaying Results 1 - 25 of 62
  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

    Publication Year: 1991
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    Freely Available from IEEE
  • A practical approach to synchronous hardware verification

    Publication Year: 1991, Page(s):180 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Hardware designs expressed in a simple hardware description language can be formally verified by adapting techniques developed for software verification. This paper presents a case study that supports this claim. From the structural specification of a two-phase clocked synchronous hardware design, a behavioral description is automatically inferred. This is subject to algebraic simplification using... View full abstract»

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  • Parallel test pattern generation using Boolean satisfiability

    Publication Year: 1991, Page(s):69 - 74
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabe... View full abstract»

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  • Simulator for IDEAL-implementation and environment

    Publication Year: 1991, Page(s):187 - 194
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately sc... View full abstract»

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  • A new processor interconnection structure for fault tolerant processor arrays

    Publication Year: 1991, Page(s):261 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the tradition... View full abstract»

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  • A neural network for channel routing

    Publication Year: 1991, Page(s):277 - 278
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    The authors propose a neural network to handle the channel routing problem. This network also allows the user to preroute critical nets and then invoke the network to complete the rest. Typical examples from published literature are taken for experiments. The theoretic lower bounds are achieved in all examples View full abstract»

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  • A scan-based BIST technique using pair-wise compare of identical components

    Publication Year: 1991, Page(s):225 - 230
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a r... View full abstract»

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  • Overlap elimination in floorplans

    Publication Year: 1991, Page(s):157 - 162
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Describes an algorithm for eliminating/reducing overlaps among blocks (macros) in VLSI chip floorplans. These blocks are assumed to be rectangular and can be either preplaced or movable. A movable block can have a fixed or a flexible shape. The authors describe applications for such an algorithm in the floorplanning process. The approach discussed in the paper is targeted towards macro cell based ... View full abstract»

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  • A switched capacitor filter synthesis system with built-in design for manufacturability

    Publication Year: 1991, Page(s):136 - 141
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The paper presents a switched capacitor filter synthesis system with yield estimation and optimization as the integral components of the design environment. The design process is an iterative process involving filter synthesis and yield estimation. Different design choices such as filter order, approximation, circuit topology, etc., affect the yield and also other parameters such as filter area, n... View full abstract»

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  • Additive cellular automata (CA) as a primitive structure for signature analysis

    Publication Year: 1991, Page(s):237 - 242
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Additive cellular automata (CA) have been proposed as an alternative to LFSR for signature analysis. It has also been shown that for nongroup CAs the steady state aliasing error probability (AEP) can be less than 2-n (for an n-cell CA). A closed form expression for the steady state AEP for a special class of CA has been derived. From the closed form expression it has been shown that the... View full abstract»

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  • Generic component library characterization for high level synthesis

    Publication Year: 1991, Page(s):5 - 10
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Describes a novel generator-generator environment for characterizing generic component libraries used in high level hardware synthesis. The environment is composed of LEGEND, a language used to specify generic libraries, and GENUS, the generated generic component library. GENUS provides generic component instances for the task of behavior-to-structure mapping in high level synthesis. The LEGEND/GE... View full abstract»

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  • An efficient interchangeable switch-box router: a generalized study

    Publication Year: 1991, Page(s):279 - 280
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The authors present a new algorithm for routing a reserved two-layer switch-box with interchangeable terminals. Savings in respect of number(s) of horizontal and/or vertical movements and number of via holes used are achieved by simply interchanging terminals in each cell View full abstract»

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  • An algorithm for minimising the number of test cycles

    Publication Year: 1991, Page(s):154 - 156
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain ... View full abstract»

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  • A systolic chip for LZ based data compression

    Publication Year: 1991, Page(s):310 - 311
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throug... View full abstract»

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  • Defect and design error location procedure-theoretical basis

    Publication Year: 1991, Page(s):243 - 248
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms View full abstract»

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  • An overlap model for routing

    Publication Year: 1991, Page(s):163 - 167
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Describes a new approach to routing in two layers using the overlap model of layer assignment. The overlap model allows tracks to be laid on top of each other as permitted by the real design rules. The technique is very simple and elegant with results more compact than the optimal solutions under the directional model and with at most one via per subnet. It is illustrated here in the context of ov... View full abstract»

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  • Automated data path synthesis to avoid global interconnects

    Publication Year: 1991, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in la... View full abstract»

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  • A novel technique for folding logic arrays

    Publication Year: 1991, Page(s):100 - 105
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optim... View full abstract»

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  • Development of ASIC datapath compilers for gate array designs

    Publication Year: 1991, Page(s):281 - 282
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    The authors present a complete development flow of ASIC datapath compilers for gate array designs. The module design and usage flow for the parameterized datapath elements is described. The efficiency achieved through the use of a highly integrated design environment is highlighted View full abstract»

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  • A novel VLSI solution to a difficult graph problem

    Publication Year: 1991, Page(s):124 - 129
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Presents a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. The solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the n... View full abstract»

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  • Method for testable design and for built-in test

    Publication Year: 1991, Page(s):286 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit View full abstract»

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  • Efficient testing techniques for bit and digit-serial arrays

    Publication Year: 1991, Page(s):142 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Bit and digit-serial architectures are used extensively in digital signal processing applications. Testing these structures is a very difficult problem due to low controllability/observability and complex interconnections between the circuit components. Efficient test generation techniques have been developed and applied to three classes of bit and digit-serial circuits. The testing techniques are... View full abstract»

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  • Tools for reliable software design of VLSI

    Publication Year: 1991, Page(s):312 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The automation tools for reliable software design of VLSI are proposed. They consist of tools for program testing based on building the minimum coverage of the analyzed program's graph, and tools for providing the required reliability of a program during its execution based on optimum program redundancy View full abstract»

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  • On reducing test length in LFSR based testing

    Publication Year: 1991, Page(s):231 - 236
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Proposes a new method for generating test patterns in the BIT (built-in testing) environment. This method reduces the testing time under both deterministic and pseudo-random testing, for a desired fault coverage. It relies on the fact that the LFSR (linear feedback shift register) sequence is deterministic. Since the position of any test vector in this sequence can be predicted, the starting vecto... View full abstract»

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  • Development of TTL equivalent library for ASIC design tools and its use to design printer adapter interface ASIC

    Publication Year: 1991, Page(s):283 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The authors describe development of TE74XX (TTL functional equivalent) library cells for ASIC design tools on Sun SPARCStation1 (model14/110). The functionality of TE74XX series cells is confirmed through exhaustive simulation using mixed-mode simulator VTISim and complete documentation is prepared. Applicability of TE74XX library is demonstrated by designing a 40-pin PAI (Printer Adapter Interfac... View full abstract»

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