[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

4-8 Jan. 1991

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  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

    Publication Year: 1991
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    Freely Available from IEEE
  • Automated data path synthesis to avoid global interconnects

    Publication Year: 1991, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in la... View full abstract»

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  • Simulator for IDEAL-implementation and environment

    Publication Year: 1991, Page(s):187 - 194
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately sc... View full abstract»

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  • Generic component library characterization for high level synthesis

    Publication Year: 1991, Page(s):5 - 10
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Describes a novel generator-generator environment for characterizing generic component libraries used in high level hardware synthesis. The environment is composed of LEGEND, a language used to specify generic libraries, and GENUS, the generated generic component library. GENUS provides generic component instances for the task of behavior-to-structure mapping in high level synthesis. The LEGEND/GE... View full abstract»

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  • A practical approach to synchronous hardware verification

    Publication Year: 1991, Page(s):180 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Hardware designs expressed in a simple hardware description language can be formally verified by adapting techniques developed for software verification. This paper presents a case study that supports this claim. From the structural specification of a two-phase clocked synchronous hardware design, a behavioral description is automatically inferred. This is subject to algebraic simplification using... View full abstract»

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  • A novel VLSI solution to a difficult graph problem

    Publication Year: 1991, Page(s):124 - 129
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Presents a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. The solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the n... View full abstract»

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  • CLSS-a workbench for control logic synthesis

    Publication Year: 1991, Page(s):219 - 224
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Describes a system called CLSS, that serves as a workbench for the synthesis of control logic. The system provides an integrated solution to the designer by providing effective solutions for all the major steps in the control logic synthesis flow. CLSS allows specification of the control logic in the form of a state transition representation. Through a set of transformation steps, all of which are... View full abstract»

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  • A class of hierarchical networks for VLSI/WSI based multicomputers

    Publication Year: 1991, Page(s):267 - 272
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A class of hierarchical networks is proposed for multicomputer implementation using VLSI and wafer scale integration (VLSI/WSI). These networks, called DBCube, connect clusters of cube topology based nodes with a De Bruijn graph. The nodes are identical and can be easily extended to a larger size. The cube topology for local communication allows easy embedding of parallel algorithms and the De Bru... View full abstract»

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  • A multilayered VLSI array design for multistage interconnection network

    Publication Year: 1991, Page(s):295 - 296
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementatio... View full abstract»

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  • New results on channel routing

    Publication Year: 1991, Page(s):174 - 179
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents a new routing concept which guides the selection of wire segments in track-by-track fashion by inspecting the effects of the endpoints of each selected wire segment to column density and vertical constraint graph of the given channel routing problem. This new routing concept has been implemented in the two-layer and three-layer routers. The routing performance of the developed two-layer a... View full abstract»

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  • Partitioning and reorganization of hierarchical circuits for DFT

    Publication Year: 1991, Page(s):106 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    To make VLSI circuits more testable, design-for-testability (DFT) and built-in self-test (BIST) techniques are often employed. These techniques typically assume a register/gate level decomposition of the overall circuit. In general, the given user hierarchy is not appropriate for embedding various testable design methodologies (TDMs). This paper describes a new canonical partitioning of a circuit ... View full abstract»

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  • An algorithm for minimising the number of test cycles

    Publication Year: 1991, Page(s):154 - 156
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain ... View full abstract»

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  • Synthesis of a control unit from instruction set specification in VHDL environment

    Publication Year: 1991, Page(s):200 - 205
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation i... View full abstract»

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  • Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

    Publication Year: 1991, Page(s):118 - 123
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    An approach to carving circuit partitions starting and stopping at controllable and observable points using high-level primitives is described. This approach allows considerable speed up over gate level partitioning. The minimum set of properties to accommodate multi-input, multi-output primitives is presented. The approach is both memory efficient and fast allowing for both deterministic and inte... View full abstract»

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  • A novel integrated scheduling and allocation algorithm for data path synthesis

    Publication Year: 1991, Page(s):212 - 218
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Proposes a novel integrated scheduling and allocation algorithm suitable for automatic data path synthesis. The algorithm is based on computation of an accurate lower bound on the cost of functional units. The algorithm produces optimal schedules in most cases View full abstract»

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  • A new processor interconnection structure for fault tolerant processor arrays

    Publication Year: 1991, Page(s):261 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the tradition... View full abstract»

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  • A Monte Carlo simulation environment for wear out in VLSI systems

    Publication Year: 1991, Page(s):249 - 254
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switchin... View full abstract»

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  • A VLSI routing framework for use on a multiprocessor workstation

    Publication Year: 1991, Page(s):82 - 87
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    With the coming of age of CAD workstations based on parallel hardware and the increasing need to accelerate CAD tools, there is a demand to exploit parallelism on general-purpose parallel hardware to achieve speedup. Hence, a novel VLSI routing framework was investigated for a parallel CAD workstation View full abstract»

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  • Synthesis of multiple outputs CMOS gates

    Publication Year: 1991, Page(s):51 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Design of static CMOS gates for multiple output functions is presented. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named delta and lambda networks. Design examples on double output functions are provided. It is shown that the two techniques can be combined togethe... View full abstract»

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  • Multilevel simulation tool for designing fault-tolerant VLSI array processors

    Publication Year: 1991, Page(s):293 - 294
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural s... View full abstract»

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  • Additive cellular automata (CA) as a primitive structure for signature analysis

    Publication Year: 1991, Page(s):237 - 242
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Additive cellular automata (CA) have been proposed as an alternative to LFSR for signature analysis. It has also been shown that for nongroup CAs the steady state aliasing error probability (AEP) can be less than 2-n (for an n-cell CA). A closed form expression for the steady state AEP for a special class of CA has been derived. From the closed form expression it has been shown that the... View full abstract»

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  • Modified interval line representation and its applications to planar routing problems

    Publication Year: 1991, Page(s):168 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A modified interval line representation is proposed. This representation makes it possible to speed up some heuristics and algorithms for planar routing problems. This technique is illustrated by speeding up the heuristic proposed by Tsukiyama and Kuh for the double row routing problem. The heuristic suggested by Tsukiyama and Kuh for double row routing problem, can be implemented in O(n2 View full abstract»

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  • A novel technique for folding logic arrays

    Publication Year: 1991, Page(s):100 - 105
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optim... View full abstract»

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  • Parallel test pattern generation using Boolean satisfiability

    Publication Year: 1991, Page(s):69 - 74
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabe... View full abstract»

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  • A new test scheduling algorithm for VLSI systems

    Publication Year: 1991, Page(s):148 - 153
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results View full abstract»

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