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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

4-8 Jan. 1991

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Displaying Results 1 - 25 of 62
  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies

    Publication Year: 1991, Page(s):290 - 292
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    A novel test structure has been designed to electrically measure the misalignment between polysilicon and the active area in MOS technologies. This alignment is one of the most critical alignments in small geometry integrated circuit processing. The structure exploits the channel width change of specially designed MOS transistors resulting from the misalignment between the active area and polysili... View full abstract»

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  • A Monte Carlo simulation environment for wear out in VLSI systems

    Publication Year: 1991, Page(s):249 - 254
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switchin... View full abstract»

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  • PLATEST: A PLA test generator

    Publication Year: 1991, Page(s):288 - 289
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models a... View full abstract»

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  • Fault modeling and testable design of 2-level complex ECL gates

    Publication Year: 1991, Page(s):23 - 28
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly h... View full abstract»

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  • New results on channel routing

    Publication Year: 1991, Page(s):174 - 179
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Presents a new routing concept which guides the selection of wire segments in track-by-track fashion by inspecting the effects of the endpoints of each selected wire segment to column density and vertical constraint graph of the given channel routing problem. This new routing concept has been implemented in the two-layer and three-layer routers. The routing performance of the developed two-layer a... View full abstract»

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  • Defect and design error location procedure-theoretical basis

    Publication Year: 1991, Page(s):243 - 248
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms View full abstract»

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  • Method for testable design and for built-in test

    Publication Year: 1991, Page(s):286 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit View full abstract»

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  • Methods for computer estimation of word lengths for behaviorally synthesized digital ASICs

    Publication Year: 1991, Page(s):17 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    In digital ASICs with predefined algorithms, the optimal word length can be defined for each internal operator, bus and register, based on the accuracy needed at the ASIC outputs. If optimal word lengths are used, rather than merely choosing 8, 16 or 32 bits, then considerable silicon area may be saved. This paper describes methods of optimizing these word lengths in a form suitable for use by a b... View full abstract»

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  • Design for testability and test generation with two clocks

    Publication Year: 1991, Page(s):112 - 117
    Cited by:  Papers (16)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is ... View full abstract»

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  • YAQT: Yet another quad tree

    Publication Year: 1991, Page(s):302 - 309
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A new data structure for storing two dimensional objects has been presented. A multiple storage quad tree is a quad tree which stores pointers to objects intersecting more than one quad in all of the quad that they intersect. The YAQT (Yet Another Quad Tree) is a modified form of multiple storage quad tree with no list required for storing crossing objects. A substantial improvement in the region ... View full abstract»

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  • A new approach for multilevel logic cell optimization

    Publication Year: 1991, Page(s):94 - 99
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Presents new ideas in the field of multi-level logic optimization for automatic logic macrocell synthesis. A new approach is proposed which performs a quasi-parallel optimization of very different and complex tasks via a simulated annealing based expert system. A first working prototype software package for multilevel logic cell optimization had been implemented to prove the validity of this appro... View full abstract»

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  • Modified interval line representation and its applications to planar routing problems

    Publication Year: 1991, Page(s):168 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A modified interval line representation is proposed. This representation makes it possible to speed up some heuristics and algorithms for planar routing problems. This technique is illustrated by speeding up the heuristic proposed by Tsukiyama and Kuh for the double row routing problem. The heuristic suggested by Tsukiyama and Kuh for double row routing problem, can be implemented in O(n... View full abstract»

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  • Synthesis of a control unit from instruction set specification in VHDL environment

    Publication Year: 1991, Page(s):200 - 205
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation i... View full abstract»

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  • Additive cellular automata (CA) as a primitive structure for signature analysis

    Publication Year: 1991, Page(s):237 - 242
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Additive cellular automata (CA) have been proposed as an alternative to LFSR for signature analysis. It has also been shown that for nongroup CAs the steady state aliasing error probability (AEP) can be less than 2-n (for an n-cell CA). A closed form expression for the steady state AEP for a special class of CA has been derived. From the closed form expression it has been shown that the... View full abstract»

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  • Development of TTL equivalent library for ASIC design tools and its use to design printer adapter interface ASIC

    Publication Year: 1991, Page(s):283 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The authors describe development of TE74XX (TTL functional equivalent) library cells for ASIC design tools on Sun SPARCStation1 (model14/110). The functionality of TE74XX series cells is confirmed through exhaustive simulation using mixed-mode simulator VTISim and complete documentation is prepared. Applicability of TE74XX library is demonstrated by designing a 40-pin PAI (Printer Adapter Interfac... View full abstract»

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  • Automated data path synthesis to avoid global interconnects

    Publication Year: 1991, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in la... View full abstract»

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  • A multilayered VLSI array design for multistage interconnection network

    Publication Year: 1991, Page(s):295 - 296
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementatio... View full abstract»

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  • Tools for reliable software design of VLSI

    Publication Year: 1991, Page(s):312 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The automation tools for reliable software design of VLSI are proposed. They consist of tools for program testing based on building the minimum coverage of the analyzed program's graph, and tools for providing the required reliability of a program during its execution based on optimum program redundancy View full abstract»

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  • Partitioning and reorganization of hierarchical circuits for DFT

    Publication Year: 1991, Page(s):106 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    To make VLSI circuits more testable, design-for-testability (DFT) and built-in self-test (BIST) techniques are often employed. These techniques typically assume a register/gate level decomposition of the overall circuit. In general, the given user hierarchy is not appropriate for embedding various testable design methodologies (TDMs). This paper describes a new canonical partitioning of a circuit ... View full abstract»

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  • A novel integrated scheduling and allocation algorithm for data path synthesis

    Publication Year: 1991, Page(s):212 - 218
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Proposes a novel integrated scheduling and allocation algorithm suitable for automatic data path synthesis. The algorithm is based on computation of an accurate lower bound on the cost of functional units. The algorithm produces optimal schedules in most cases View full abstract»

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  • The high level design of the long accumulator chip

    Publication Year: 1991, Page(s):299 - 301
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    The authors discuss an architecture and its high level description of a long accumulator chip suited for the exact calculation of the inner products of floating point numbers. A highly parallel implementation is developed using eight independent adder stations, which add products to two circular long accumulators. A dispatcher schedules each product to the best available station. To validate this ... View full abstract»

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  • Synthesis of multiple outputs CMOS gates

    Publication Year: 1991, Page(s):51 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Design of static CMOS gates for multiple output functions is presented. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named delta and lambda networks. Design examples on double output functions are provided. It is shown that the two techniques can be combined togethe... View full abstract»

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  • Elements of a design framework for module generators design and usage

    Publication Year: 1991, Page(s):88 - 93
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Presents a procedural layout description language ALL and elements of design environment that supports it. Language capabilities in defining module generators are shown. Ways of integrating textual and graphical layout representations are presented. A proposal of language implementation based on object-oriented paradigm is discussed View full abstract»

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  • An overlap model for routing

    Publication Year: 1991, Page(s):163 - 167
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Describes a new approach to routing in two layers using the overlap model of layer assignment. The overlap model allows tracks to be laid on top of each other as permitted by the real design rules. The technique is very simple and elegant with results more compact than the optimal solutions under the directional model and with at most one via per subnet. It is illustrated here in the context of ov... View full abstract»

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