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ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

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ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Date Sept. 27 1993-Oct. 1 1993

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Title History

Sixth Annual IEEE International ASIC Conference and Exhibit

Circuit partitioning for pseudo-exhaustive test

Testable design environment with test-added tools

An asymptotically optimal algorithm for gate array placement

Automated test data development for semi-custom ICs: An ideal approach to fast development

A FPGA ASIC communication channel systems emulator

Direct comparison of 2 set of results from testability analysis by using correlation and statistical testability analysis of transient (delay) faults

Development of high performance ASICs using ACUITY image resizing engine cores

Implementing a fuzzy inference engine using FPGA

Placement and placement driven technology mapping for FPGA synthesis

Accelerated fuzzy pattern classification with ASICs

Programmable capabilities allow field customization of ASIC devices

BiNMOS-CBA: An optimum solution for high performance EDP and telecom applications

Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

A cell-based datapath synthesizer for ASICs

Large system asynchronous design

An automatic cell characterization environment for cell-based design methodology

Top down system design using VHDL [FFT system]

New delay model for 0.5μ CMOS ASIC

An ASIC signal processor for electronic warfare receivers

A sub-50 psec. 89 K gate ECL-gate array with 480 Kb BiCMOS STRAM

Design verification techniques for system level testing using ASIC level BIST implementations

MMIC front-ends for optical communication systems

Application of process statistics to macro/behavioral modeling

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

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