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ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Date Sept. 27 1993-Oct. 1 1993

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  • Sixth Annual IEEE International ASIC Conference and Exhibit

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (197 KB)
    Freely Available from IEEE
  • Technology issues of library porting in multi-process environment

    Publication Year: 1993, Page(s):320 - 325
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    In the multi-process environment, a library vendor has to port libraries to foundries using different processes. Technology match between the library and the process becomes necessary, in addition to software compatibility. Typical issues are design rules, device targets, simulation models, reliability, and performance. Retarget of either process or library or both is generally required. Criteria,... View full abstract»

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  • ASIC manufacturability simulation

    Publication Year: 1993, Page(s):310 - 319
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    In this tutorial, the use of simulation techniques to improve the manufacturability yield of ASIC devices is described. ASIC manufacturability simulation procedures are illustrated with the help of various practical examples. Use of ASIC manufacturability simulation as part of standard design methodology at AT&T has been shown to improve the yield of ASIC devices, and it also helps reduce the ... View full abstract»

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  • Design and fabrication of long wavelength OEICs

    Publication Year: 1993, Page(s):474 - 477
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The motives behind the development of 1.3 and 1.55 μm opto-electronic integrated circuits (OEICs) are discussed. OEICs for WDM (wavelength division multiplexing) and ATM (asynchronous transfer mode) communications applications are used to explain the materials, design, and fabrication issues involved. Factors determining the optimum size of OEICs are outlined View full abstract»

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  • A full custom VLSI design methodology using Mentor Graphics design software in an educational environs

    Publication Year: 1993, Page(s):305 - 308
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    An 8-b arithmetic logic unit (ALU) was schematic-captured, simulated, physically designed, and resimulated with parasitics using Mentor Graphics design tools and a full custom methodology. The design can be fabricated with confidence that it will perform as expected. The design has demonstrated how a commercial design tool can effectively be used in an educational environment. Many tool related is... View full abstract»

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  • Linear IC parasitic element simulation methodology

    Publication Year: 1993, Page(s):500 - 506
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Linear IC design requires an intimate understanding of how the physical circuit realization affects the electrical performance of the circuit. An overview of parasitic elements of consequence in linear IC design is followed by a straightforward methodology to include these physical considerations into the electrical schematic such that the circuit simulations will take these elements into account.... View full abstract»

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  • Design of a high speed interface for 0.5μm gate arrays

    Publication Year: 1993, Page(s):468 - 471
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Modern systems running at clock rates of 50-150 MHz need high-performance interfaces for use between different logic and memory chips on the PCB. There is also a need for very tight clock skew control. The author examines the requirements of high-performance input/output buffers (I/Os) and clock skew control for 0.5-μm gate arrays. In order to produce a cost-effective and performance-optimized ... View full abstract»

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  • ASIC DFT techniques and benefits

    Publication Year: 1993, Page(s):46 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    This tutorial provides an overview of market prospective on and use of the ASIC DFT, DFT techniques (their benefits and drawbacks), and the ASIC DFT process flow. What is needed to do a testable ASIC is discussed. Testability must be incorporated in all phases of the design from embedded blocks, chip level, to board and system level in order to meet the aggressive design-to-volume times. There is ... View full abstract»

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  • A design consultant to support CAD tool usage

    Publication Year: 1993, Page(s):301 - 304
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    New designers and students are typically overwhelmed by the plethora of CAD tools at their disposition. To ease their task and to familiarize them with both an efficient usage of tools and a strict design methodology, the authors developed the knowledge-based design consultant CADEC. It contains a comprehensive general concept for partitioning and modeling the design process. In each design step i... View full abstract»

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  • A transistor voltage reference-and what the bandgap has to do with it

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (16 KB)

    Summary form only given, as follows. Many ICs lack stable avalanche or Zener diodes or the operating voltage to derive a reference voltage. A stable, reproducible low-voltage reference can be derived from a bipolar transistor base-emitter junction. The operating principle of such circuits is described and the significance of the bandgap voltage is explained View full abstract»

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  • Microprogram sequencer with concurrent error detection

    Publication Year: 1993, Page(s):224 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The design of a microprogram sequencer with concurrent error detection is described. The error detection scheme involves generation of signatures based on past and present sequencer outputs; these signatures are compared frequently against expected values. Software tools for signature assignment are described. Testing results using prototype parts are summarized View full abstract»

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  • Time domain optimisation of high bit rate optical receivers

    Publication Year: 1993, Page(s):494 - 497
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    The design and optimization of integrated post detection optical receiver filters are discussed. A novel time domain based optimization technique accounting for process degeneracies is presented along with practical results for a 15-Gb/s GaAs MMIC pulse shaping network, demonstrating the suitability of the technique for designing structures with a well-controlled response to frequencies beyond 20 ... View full abstract»

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  • Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs

    Publication Year: 1993, Page(s):464 - 467
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Compared to conventional packaging, multichip modules have significantly reduced capacitive loading in their interconnections. The authors present experimental results showing the performance of I/O buffers specially designed to operate in this environment, evaluated in several different silicon-on-silicon test modules View full abstract»

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  • Data compression and VLSI implementation neuroprocessor

    Publication Year: 1993, Page(s):570 - 579
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    VLSI data compression research has been motivated by the needs of high-speed high-performance data compression and inspired by the VLSI technologies. An integrated data compression system has been proposed to provide adaptive multi-mode data compression for an advanced multi-instrument spacecraft payload system that has various source data. It combines a high-ratio lossy data compressor with a los... View full abstract»

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  • Automated test data development for semi-custom ICs: An ideal approach to fast development

    Publication Year: 1993, Page(s):62 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    With the advent of high performance technologies (sub-micron CMOS, BiCMOS, and BiNMOS), the practicality of automated test data development will be emphasized. Although automatic test pattern generation and timing analysis are currently considered desirable, the complexity and size of future ICs will make them mandatory. The author describes a new trend in test data development for a complex semi-... View full abstract»

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  • A baseband mixed signal ASIC for CDMA subscriber equipment applications

    Publication Year: 1993, Page(s):23 - 26
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    An implementation of the baseband mixed signal processing required in a code division multiple access (CDMA) telephone is discussed. These processing blocks include quadrature up and down conversion between a 5 MHz intermediate frequency and baseband, active filtering, A/D and D/A converters clocking at 10 MHz, and clock conditioning circuits View full abstract»

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  • Test tradeoffs in ASIC design: tutorial

    Publication Year: 1993, Page(s):36 - 45
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    In this tutorial test fundamentals are reviewed to introduce key concepts in design for test and built-in self-test. Design for test and built-in self-test are illustrated by their implementation in single-chip conversion of a PCB design and a floating point co-processor design, respectively. The savings in design effort when testability is part of the initial design is stressed View full abstract»

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  • Experiences with an HDL-based design method for complex architectures

    Publication Year: 1993, Page(s):297 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Two RISC microprocessors have been designed to improve the design method and to study its effect on the design of complex architectures. The method is presented, and some key issues are identified. They include HDL-based modeling rules, supplementary high-level specification with statecharts, the notion of behavioral and structural similarity, and a consistent test strategy View full abstract»

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  • CircuitSim93: A circuit simulator benchmarking methodology case study

    Publication Year: 1993, Page(s):531 - 535
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A circuit simulator benchmarking methodology is developed that follows the philosophy that one wants to exercise each of the simulators on each of the benchmark circuits and make a fair comparison of their performance. This methodology was tested out in a benchmarking of six commercial circuit simulators from three CAE companies using a new circuit simulator benchmark suite called CircuitSim93 View full abstract»

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  • An ASIC signal processor for electronic warfare receivers

    Publication Year: 1993, Page(s):218 - 221
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A specialized ASIC signal processor has been developed for electronic warfare (EW) receivers using the amplitude comparison direction finding technique. Algorithms for signal detection, and the estimation of time-of-arrival, pulse width, and direction-of-arrival are implemented in real-time on up to eight channels of 8-b video data sampled at 40 MHz View full abstract»

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  • High speed and high performance long wavelength OEICs using heterojunction bipolar transistors

    Publication Year: 1993, Page(s):490 - 493
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    High-speed heterojunction bipolar transistors (HBTs) in the InP/InGaAs material system have been monolithically integrated with p-i-n photodetecters as receivers and with quantum well lasers as transmitters for potential applications in long wavelength lightwave communications. Speeds well beyond 5 Gb/s have been achieved with excellent performance View full abstract»

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  • An extended hyperbolic hop code transmitter

    Publication Year: 1993, Page(s):374 - 377
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Frequency hop codes represent a class of codes in which the signal is transmitted as a sine wave, whose frequency at any time, is one of a set of possible discrete values. A 2.0-μm CMOS technology transmitter which efficiently generates the signal for an extended hyperbolic congruential (EHC) frequency hop code is described. Minimal hardware is used to generate the constituent sine waves and th... View full abstract»

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  • XBERT - A versatile 622 Mb/sec bit error rate generator/receiver methodology for SONET OC-3 application

    Publication Year: 1993, Page(s):358 - 361
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    XBERT, a microprocessor programmable multi-rate bit error rate generator/receiver is described. It is used for testing the performance of digital communication circuits and communication links. The data rate for XBERT can be configured from 1 kb/s to 622 Mb/s. This makes XBERT an extremely versatile device for testing asynchronous (DS0, DS1, DS3) and synchronous SONET/STS-3 (STM-1), STS-12 (STM-4)... View full abstract»

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  • An adaptive CMOS transmission line driver

    Publication Year: 1993, Page(s):460 - 463
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    Fabrication process tolerances prevent the direct and precise matching of off-chip driver impedances to the impedances of driven transmission lines. The adaptive circuit described automatically adjusts the output impedance of a reference driver to that of a reference transmission line and generates a control voltage for adjusting the output impedances of the other drivers on the same chip to the s... View full abstract»

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  • Accelerated fuzzy pattern classification with ASICs

    Publication Year: 1993, Page(s):250 - 253
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    The wide proliferation fuzzy classification depends on the availability of fast low cost systems. Specific integrated hardware like ASICs is needed. An accelerator system for fuzzy pattern classification mthod is presented. Further, the application of different ASICs is discussed. Especially, the design and realization of a fuzzy pattern classification accelerator with FPGAs (rapid prototyping) ar... View full abstract»

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