Sixth Annual IEEE International ASIC Conference and Exhibit

Sept. 27 1993-Oct. 1 1993

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  • Sixth Annual IEEE International ASIC Conference and Exhibit

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (197 KB)
    Freely Available from IEEE
  • ECL I/O buffers for BiCMOS integrated systems: A tutorial overview

    Publication Year: 1993, Page(s):436 - 443
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    The authors describe the methodology for the design and layout of fast BiCMOS ECL I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature and supply voltage compensated an... View full abstract»

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  • A transistor voltage reference-and what the bandgap has to do with it

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (22 KB)

    Summary form only given, as follows. Many ICs lack stable avalanche or Zener diodes or the operating voltage to derive a reference voltage. A stable, reproducible low-voltage reference can be derived from a bipolar transistor base-emitter junction. The operating principle of such circuits is described and the significance of the bandgap voltage is explained.<> View full abstract»

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  • Test tradeoffs in ASIC design: tutorial

    Publication Year: 1993, Page(s):36 - 45
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (662 KB)

    In this tutorial test fundamentals are reviewed to introduce key concepts in design for test and built-in self-test. Design for test and built-in self-test are illustrated by their implementation in single-chip conversion of a PCB design and a floating point co-processor design, respectively. The savings in design effort when testability is part of the initial design is stressed.<> View full abstract»

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  • Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

    Publication Year: 1993, Page(s):130 - 139
    Cited by:  Papers (2)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (630 KB)

    This is a comprehensive tutorial on DFT with emphasis on concepts of digital Application Specific Integrated Circuit (ASIC) testing incorporating boundary scan architecture in ASIC design. This tutorial covers discussion and features of Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, Joint Test Action Group (JTAG) test technique, that can be implemented during design and ... View full abstract»

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  • ASIC system design considerations

    Publication Year: 1993, Page(s):294 - 296
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    This tutorial focuses on reducing interchip delays using performance controlled circuitry (PCC). Variations in CMOS ASIC temperature, voltage, and IC manufacturing process all cause variations in performance, especially I/O switching performance. Variations in I/O switching performance are no longer tolerable in today's high-performance system designs where interchip timing and communications is c... View full abstract»

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  • BiNMOS-CBA: An optimum solution for high performance EDP and telecom applications

    Publication Year: 1993, Page(s):170 - 173
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    So far, the ASIC industry has looked at only traditional approaches, such as CMOS and BiCMOS gate array and standard cell, to solve various design issues. The authors discuss a detailed investigation that resulted in an innovative cell based array (CBA) architecture: BiNMOS-CBA with highly efficient CMOS compute cells and performance optimized drive cells with bipolar and NMOS transistors View full abstract»

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  • Digital transistor sizing techniques applied to 100K ECL CMOS output buffers

    Publication Year: 1993, Page(s):456 - 459
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Regulated current levels have been maintained with a control circuit that digitally adjusts the effective width of a 0.9-μm CMOS output buffer to generate 100 K ECL levels operating up to 800 MHz. A pseudo-random bit error rate test of the buffer operating at 1.6 Gb/s indicated no errors Digital sizing reduces the variation of internal power dissipation over operating conditions from 250% to 10... View full abstract»

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  • Automated test data development for semi-custom ICs: An ideal approach to fast development

    Publication Year: 1993, Page(s):62 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    With the advent of high performance technologies (sub-micron CMOS, BiCMOS, and BiNMOS), the practicality of automated test data development will be emphasized. Although automatic test pattern generation and timing analysis are currently considered desirable, the complexity and size of future ICs will make them mandatory. The author describes a new trend in test data development for a complex semi-... View full abstract»

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  • ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

    Publication Year: 1993, Page(s):100 - 103
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The design of a multi-channel, single-chip, adaptive echo canceller for T1 and E1 long-distance telecommunications networks is described. The ECHO2 chip required a novel architecture to achieve the throughput necessary to process multi-channels and end-paths of up to 128 msec delay. The design was implemented in Texas Instruments TLM CMOS EPICIZ 1 μm process and TSC700 standard cell technology.... View full abstract»

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  • Improving FSMD design assurance

    Publication Year: 1993, Page(s):274 - 277
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Assurance is a critical factor in the application of EDA tools to ASIC design. An experimental environment for high-assurance rapid prototyping using an application specific language, formal verification, and circuit synthesis for the design of communicating FSMDs has been successfully demonstrated. Digital design paradigms that consider both the digital and verification domains can integrate symb... View full abstract»

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  • Timing skew of the equal-length serpentines routing

    Publication Year: 1993, Page(s):546 - 549
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Serpentines routing has been frequently utilized in multichip module or PCB layout to control the propagation delay of the signal trace. The coupling effect in serpentine structures was indicated by simulation and measurement results to be able to degrade signal quality and change signal flight time. The amount of skew was found to be proportional to the coupling coefficient and parallel length of... View full abstract»

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  • Implementing a timing shell for VHDL simulation using the proposed EIA-567 standard

    Publication Year: 1993, Page(s):288 - 291
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Timing issues in VHDL simulation continue to be important to the VHDL community. The proposed EIA-567 standard is one of several methods of describing a database for timing parameters within the language. Although there are several methods for accessing and using these data, the author explains how a particular timing shell was constructed, how it is used, its unique language constructs, and some ... View full abstract»

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  • Motorola MC68040 high-speed design using altera EPM5000 erasable programmable logic devices

    Publication Year: 1993, Page(s):235 - 238
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Many designs use EPLDs (Erasable Programmable Logic Devices) to implement control logic and state machines. If the design is slow, timing through the EPLD is not crucial so designers often treat the device as a black box. In high speed designs, timing through the EPLD is critical. In these cases a thorough understanding of the device architecture is necessary. Lessons learned in the implementation... View full abstract»

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  • Microprogram sequencer with concurrent error detection

    Publication Year: 1993, Page(s):224 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The design of a microprogram sequencer with concurrent error detection is described. The error detection scheme involves generation of signatures based on past and present sequencer outputs; these signatures are compared frequently against expected values. Software tools for signature assignment are described. Testing results using prototype parts are summarized View full abstract»

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  • A semicustom implemented connection matrix for SDH systems

    Publication Year: 1993, Page(s):378 - 381
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The introduction of the synchronous digital hierarchy (SDH) in digital communications has emphasized the importance of implementing complex and compact matrix devices, inside the network nodes. The authors introduce the ASIC Matisse, which performs a complete, rearrangeable connection matrix among 16 input Synchronous Transport Module-1 (STM1) frames (up to 1008 Virtual Container-12 (VC12) synchro... View full abstract»

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  • 5-volt to 3-volt evolution paths: Selecting a gate array product for the next generation

    Publication Year: 1993, Page(s):178 - 185
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    As systems evolve from 5 V to 3 V, designers must choose an appropriate gate array technology and migration path. The author identifies and discusses the complex set of factors which govern these choices. The factors include market and technological driving forces, migration rates of systems and components, gate array technologies available for the migration, and possible migration paths. This ana... View full abstract»

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  • Current mode transceiver logic, (CMTL) for reduced swing CMOS, chip to chip communication

    Publication Year: 1993, Page(s):452 - 455
    Cited by:  Papers (4)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    A reduced voltage swing CMOS interface for differential and single-ended signaling is presented. Differential 400-MHz transmitter/receiver operation with a 5-V supply and 300-MHz operation with a 3.3-V supply are both shown. Results showing PECL (positive ECL) compatibility are also presented View full abstract»

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  • An automatic cell characterization environment for cell-based design methodology

    Publication Year: 1993, Page(s):326 - 329
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The authors introduce an automatic cell characterization environment developed for cell-based design methodology. With its structured cell description language, automatic stimuli generation algorithm and flow event manager, varieties of cells are automatically characterized. It has been applied successfully to characterize the 1.0-μm and 0.8-μm standard cell, sea-of-gates, and full-custom ce... View full abstract»

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  • Parallel optical interconnects for Scalable Coherent Interface

    Publication Year: 1993, Page(s):482 - 485
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    The feasibility of using parallel optical interconnects as a high-performance and potentially low-cost alternative for implementing the IEEE Scalable Coherent Interface (SCI) standard is investigated using a simulation approach. The simulation results show that an 18-parallel optical interconnect system using a fully differential configuration has extremely low crosstalk (⩽ -30 dB) at a 500-MH... View full abstract»

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  • Testable design environment with test-added tools

    Publication Year: 1993, Page(s):58 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    A testable design environment with test-added tools is presented. These programs check whether the circuit design violates testable rules, locate the sources of poor testability, and calculate toggle rate of the circuit. A testable design flow is introduced and functions of the programs are described. The system is in production use and some experimental results are also shown View full abstract»

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  • An asymptotically optimal algorithm for gate array placement

    Publication Year: 1993, Page(s):95 - 98
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A novel technique, the neighbor state transition (NST) method, is introduced for solving a class of optimization problems often found in VLSI designs. The NST method utilizes the powerful means developed for the optimization in continuous space to solve the optimization problems confined to discrete points. For a well known NP-hard problem, gate array placement, the method produces an asymptotical... View full abstract»

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  • Parameter-driven data path VHDL model generation for ASIC design

    Publication Year: 1993, Page(s):270 - 273
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Previous methods for automatic generation of behavioral VHDL models require an ASIC engineer to have knowledge of particular input techniques such as graphical entry, specialized table, etc. The author presents a new method that takes the user-specified engineering parameters as inputs for the behavioral VHDL model generation. Since it is a common practice for the ASIC engineer to specify circuits... View full abstract»

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  • A floorplanning system for tape automated bonding packages

    Publication Year: 1993, Page(s):542 - 545
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Tape automated bonding (TAB) technology offers an ideal choice for packaging high pin count ICs. However, the manual routing for TAB is tedious and takes weeks to complete. The authors have developed a high performance router which completes routing in a few seconds on a PC-486. Compared to manual work, an average of 19% area reduction has been achieved. Based on the router, a floorplanning system... View full abstract»

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  • A design consultant to support CAD tool usage

    Publication Year: 1993, Page(s):301 - 304
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    New designers and students are typically overwhelmed by the plethora of CAD tools at their disposition. To ease their task and to familiarize them with both an efficient usage of tools and a strict design methodology, the authors developed the knowledge-based design consultant CADEC. It contains a comprehensive general concept for partitioning and modeling the design process. In each design step i... View full abstract»

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