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Sixth Annual IEEE International ASIC Conference and Exhibit

Sept. 27 1993-Oct. 1 1993

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  • Sixth Annual IEEE International ASIC Conference and Exhibit

    Publication Year: 1993
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    Freely Available from IEEE
  • A transistor voltage reference-and what the bandgap has to do with it

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (22 KB)

    Summary form only given, as follows. Many ICs lack stable avalanche or Zener diodes or the operating voltage to derive a reference voltage. A stable, reproducible low-voltage reference can be derived from a bipolar transistor base-emitter junction. The operating principle of such circuits is described and the significance of the bandgap voltage is explained.<> View full abstract»

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  • A CMOS circuit technique for high-speed RAMs

    Publication Year: 1993, Page(s):243 - 246
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Recently, CMOS circuits at clock speeds normally described with ECL have been demonstrated. The author presents a technique for including RAM structures in such designs. Pipelining the address decoder and integrating a fast sense amplifier in the high-speed CMOS technique allows integration of small RAMs in circuits running at several hundred MHz. A 420 MHz, 32 word by 64-b register file has been ... View full abstract»

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  • RLRAM: A VLSI implementation of a resetable, loadable RAM module

    Publication Year: 1993, Page(s):239 - 242
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    The design, implementation, and testing of a 128 × 6 Reset Load RAM (RLRAM) chip is presented. It is a RAM module with additional functionality: one cycle complete RAM reset, and two cycle loading of pre-determined value set, out of eight. The successfully tested 1.5 μm prototype modules run at 35.7 MHz and measure 4 mm2. In spite of the massively parallel operations, supply cu... View full abstract»

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  • Motorola MC68040 high-speed design using altera EPM5000 erasable programmable logic devices

    Publication Year: 1993, Page(s):235 - 238
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Many designs use EPLDs (Erasable Programmable Logic Devices) to implement control logic and state machines. If the design is slow, timing through the EPLD is not crucial so designers often treat the device as a black box. In high speed designs, timing through the EPLD is critical. In these cases a thorough understanding of the device architecture is necessary. Lessons learned in the implementation... View full abstract»

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  • A CMOS phase detector for mixed signal ASIC application

    Publication Year: 1993, Page(s):232 - 234
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    The author presents a phase detector that is constructed using a type of current mode logic. The resulting design can be fabricated on a conventional CMOS process but exhibits performance that is approximately two times faster than a similar design based upon conventional CMOS logic circuits. At the same time the low voltage swings of the current mode logic produce low parasitic coupling energy, a... View full abstract»

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  • Modelling of a self timed dataflow processor in VHDL

    Publication Year: 1993, Page(s):228 - 231
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989). Dataflow computers differ from most other parallel architectures. They are based on the concept of data-driven computation instead of the program store computation model. Since the d... View full abstract»

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  • Microprogram sequencer with concurrent error detection

    Publication Year: 1993, Page(s):224 - 227
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    The design of a microprogram sequencer with concurrent error detection is described. The error detection scheme involves generation of signatures based on past and present sequencer outputs; these signatures are compared frequently against expected values. Software tools for signature assignment are described. Testing results using prototype parts are summarized View full abstract»

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  • An ASIC signal processor for electronic warfare receivers

    Publication Year: 1993, Page(s):218 - 221
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A specialized ASIC signal processor has been developed for electronic warfare (EW) receivers using the amplitude comparison direction finding technique. Algorithms for signal detection, and the estimation of time-of-arrival, pulse width, and direction-of-arrival are implemented in real-time on up to eight channels of 8-b video data sampled at 40 MHz View full abstract»

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  • “Piecewise-quadratic” synthesis of an exponential characteristic with an array of square-law MOSFETs

    Publication Year: 1993, Page(s):31 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    The author presents a procedure for synthesizing an MOS circuit with an approximately exponential voltage-current characteristic. Analysis of an infinite array of ideal MOSFETs yields mathematically convenient results, which guide the development of an algorithm for finite arrays of nonideal MOSFETs. Given a desired exponential function, the design algorithm determines the required MOSFET device s... View full abstract»

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  • Placement and placement driven technology mapping for FPGA synthesis

    Publication Year: 1993, Page(s):91 - 94
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Because of the more restrictive placement and routing constraints in Xilinx FPGA designs, conventional physical design tools for general placement and routing architectures usually do not work well for FPGA designs. Moreover, to generate high quality circuits which are easy to place and route, it is important to consider the specific physical design constraints during the technology mapping proces... View full abstract»

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  • Programmable capabilities allow field customization of ASIC devices

    Publication Year: 1993, Page(s):214 - 217
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    The new Vialink antifuse technology is discussed. This allows ASIC customers to add PROM-style field programmability to standard ASIC devices. An overview of the technology is discussed. Techniques used to incorporate this circuitry into an ASIC device are also discussed View full abstract»

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  • A 5 Mbit/sec data transceiver chip for the `FIP' protocol

    Publication Year: 1993, Page(s):382 - 385
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    A transceiver chip for serial data communications in harsh industrial environments is presented. The transceiver chip fully complies with the FIP protocol standard for data rates up to 5 Mb/s over a twisted pair connection View full abstract»

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  • High speed and high performance long wavelength OEICs using heterojunction bipolar transistors

    Publication Year: 1993, Page(s):490 - 493
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    High-speed heterojunction bipolar transistors (HBTs) in the InP/InGaAs material system have been monolithically integrated with p-i-n photodetecters as receivers and with quantum well lasers as transmitters for potential applications in long wavelength lightwave communications. Speeds well beyond 5 Gb/s have been achieved with excellent performance View full abstract»

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  • A cell-based datapath synthesizer for ASICs

    Publication Year: 1993, Page(s):416 - 419
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A datapath synthesis method that maps an RTL description of an ASIC to a hierarchical netlist is presented. The method partitions the ASIC's behavior into datapath, mapped to bit-sliced layout or cell-based netlist, and glue logic mapped to cells. This synthesis method performs resource selection and resource sharing, and thus allows the user to explore design space both at the architectural-level... View full abstract»

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  • 5-volt to 3-volt evolution paths: Selecting a gate array product for the next generation

    Publication Year: 1993, Page(s):178 - 185
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    As systems evolve from 5 V to 3 V, designers must choose an appropriate gate array technology and migration path. The author identifies and discusses the complex set of factors which govern these choices. The factors include market and technological driving forces, migration rates of systems and components, gate array technologies available for the migration, and possible migration paths. This ana... View full abstract»

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  • A wideband, fixed gain BiMOS amplifier

    Publication Year: 1993, Page(s):27 - 30
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Circuits which achieve precise gains without the use of negative feedback have recently become of interest because of their simplicity and large bandwidth. A new circuit architecture is proposed for precision, fixed gain amplifiers using an open loop approach. Two circuit implementations using the new architecture are presented. The first is constructed as a 9 × 12 mil cell on an N-well CMOS... View full abstract»

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  • Closing the gap: Near-optimal Steiner trees in polynomial time

    Publication Year: 1993, Page(s):87 - 90
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The authors enhance the Iterated 1-Steiner (I1S) MRST heuristic of A.B. Kahng, and G. Robins (1992). For typical nets, the methods obtain average performance of less than 0.25% from optimal, and produce optimal solutions in 90% of cases. The authors generalize I1S to higher dimensions, and prove that in 2-D and 3-D the MST degree of any point can be made ⩽4 and ⩽14, respectively. Aside fro... View full abstract»

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  • Interconnect and output driver modeling of high speed designs

    Publication Year: 1993, Page(s):507 - 510
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    An adaptive Thevenin equivalent circuit model, which can be applied to both emitter follower structured drivers and other unconventional drivers with bootstrap capacitor and overshooting output voltage, and a second order circuit on-chip interconnect approximation make it possible to derive a closed-form analytic expression relating the transient response of the driver to the loading of the interc... View full abstract»

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  • 1V high-speed digital circuit technology with 0.5μm multi-threshold CMOS

    Publication Year: 1993, Page(s):186 - 189
    Cited by:  Papers (31)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A 1-V high-speed and low-power digital circuit technology with 0.5μm multi-threshold CMOS (MT-CMOS) is proposed. This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period. ... View full abstract»

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  • Modeling for synthesis in VHDL

    Publication Year: 1993, Page(s):278 - 282
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    VHDL is a rich modeling language supporting a vast range of abstractions. To efficiently use present day synthesis, the modeler must follow a style that differs considerably from the one required by logic simulators. In this tutorial, a guide to the efficient use of available synthesis tools is provided View full abstract»

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  • A top down design environment for data-path design [FIR filter]

    Publication Year: 1993, Page(s):266 - 269
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    A top-down data-path design environment is discussed in four major aspects: the design entry, simulation, synthesis, and optimization. A new design environment based on enhanced Verilog-HDL and the data-path library is proposed for the inner-product circuit design. An example of a 20 K gate digital filter design demonstrates the efficiency in the design period and design optimization View full abstract»

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  • Large system asynchronous design

    Publication Year: 1993, Page(s):207 - 213
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    A language is presented for the design of asynchronous logic circuits. The language offers effective syntax for specifying long-range interactions among signals remote from one another in the data pipeline. Problems specified in the language have a unique-state-coding implicit in their formulation. Solutions are fully interlocked and satisfy properties of liveness, safeness, and persistency. Featu... View full abstract»

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  • A semicustom implemented connection matrix for SDH systems

    Publication Year: 1993, Page(s):378 - 381
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    The introduction of the synchronous digital hierarchy (SDH) in digital communications has emphasized the importance of implementing complex and compact matrix devices, inside the network nodes. The authors introduce the ASIC Matisse, which performs a complete, rearrangeable connection matrix among 16 input Synchronous Transport Module-1 (STM1) frames (up to 1008 Virtual Container-12 (VC12) synchro... View full abstract»

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  • MMIC front-ends for optical communication systems

    Publication Year: 1993, Page(s):486 - 489
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for the GaAs MESFET tuned front-end View full abstract»

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