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Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Date 20-24 Sept. 1993

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Displaying Results 1 - 25 of 91
  • Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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    Freely Available from IEEE
  • Graph based analysis of FPGA routing

    Page(s): 104 - 109
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    The experimental results of FPGA (field programmable gate array) routing suggest that there are difficulties in mapping global routing to a predictable detailed routing for array type architectures. The authors develop a graph theoretical formulation of this mapping problem and show that it is NP-complete for both multi-pin net lists and two-pin net lists for the Xilinx-like routing model. They present two changes in the routing architecture such that each of them yields a predictable mapping of global routing to the optimal detailed routing. The results suggest a novel approach to array type FPGA routing.<> View full abstract»

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  • Locally optimistic methods of concurrent simulation

    Page(s): 572 - 576
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    A new model is presented for the simulation of large and complex systems by exploiting concurrency. Composite ELSA is a distributed asynchronous event-driven simulation model which combines the conservative and optimistic synchronization protocols, while preserving their respective advantages. This model assigns synchronization classes to processes or a hierarchy of processes, which are based on attributes of conservatism or degree of optimism. These attributes can be dynamically updated during the course of simulation, enabling processes to switch smoothly between synchronization classes. A locally optimistic synchronization protocol is introduced, and comparisons are made with two traditional protocols for parallel logic simulation on distributed memory MIMD machines View full abstract»

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  • Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD

    Page(s): 78 - 83
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    The simulated annealing (SA) algorithm has been applied to every difficult optimization problem in VLSI (very large scale integration) CAD. Existing SA implementations use monotone decreasing, or cooling, temperature schedules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that challenges the correctness of using such schedules. Specifically, the theoretical framework under which monotone cooling schedules is proved optimal fails to capture the practical application of simulated annealing. In practice, the algorithm runs for a finite rather than infinite amount of time; and the algorithm returns the best solution visited during the entire run ("best-so-far") rather than the last solution visited ("where-you-are"). For small instances of classic VLSI CAD problems, the authors determine annealing schedules that are optimal in terms of the expected quality of the best-so-far solution. These optimal schedules do not decrease monotonically, but are in fact either periodic or warming. (When the goal is to optimize the cost of the where-you-are solution, they confirm the traditional wisdom of cooling.) The results open up many new research directions, particularly how to choose annealing temperatures dynamically to optimize the quality of the finite time, best-so-far solution View full abstract»

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  • PEAS-I: A hardware/software co-design system for ASIPs

    Page(s): 2 - 7
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    The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design View full abstract»

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  • An approach to CAD database support of design consistency control

    Page(s): 326 - 331
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    CAD database services which support CAD tools in preserving design consistency are presented. Design consistency is briefly defined. Interactive design tools require support with respect to the specification of consistency rules, check points, and reactions to checks. Services of the object oriented IREEN database system designed to meet these requirements are presented. The authors introduce tasks (event driven processes) which provide a means to create supervisors for consistency rules as well as to model higher order actions to which consistency rules are related View full abstract»

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  • Demosthenes-A technology-independent power DMOS layout generator

    Page(s): 178 - 183
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    A methodology to automate DMOS layout generation starting from electrical specifications is presented. The main features of the Demosthenes technology independent layout generator that make it possible to synthesize lateral and vertical DMOS in different low and high voltage technologies are described. The built-in electrical model used by the generator to extract the device layout resistance is exposed and the accuracy of the model, ranging from 1% to 15%, is reported, according to comparisons with silicon measurements. In the future, the Demosthenes generator will be extended to support the next generation of BCD technology. In addition, electrical modeling capabilities will be improved by generating detailed electrical simulation models that make it possible to accurately simulate DMOS switching View full abstract»

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  • Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device

    Page(s): 39 - 44
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    A new routing-driven partitioning approach for fitting a sequential circuit onto limited-connectivity EPLDs (electrically programmable logic devices) is presented. The fitting problem is stated as a graph monomorphism problem. Global, local, and adjacency routing constraints are used to define the partitioning properties of the graph representing chip resources. This approach very effectively limits the solution space of the graph monomorphism problem in the early stages of the search. The program which uses the proposed algorithm to solve the fitting problem for the CY7C361 device, from Cypress Semiconductor, has been implemented and tested. Solutions to a number of problems unsolved by the previous fitter were found. The experimental results are presented View full abstract»

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  • An HDL approach to board-level BIST

    Page(s): 410 - 415
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    Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language) View full abstract»

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  • High-level synthesis transformations for programmable architectures

    Page(s): 8 - 13
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    The application of high level synthesis techniques in connection with highly programmable VLSI (very large scale integration) architectures is presented. Very early prototype realizations of subcomponents of complex systems can be achieved for real-time test runs if automatic synthesis is applied. The efficiency and applicability of this approach will be demonstrated with realistic mechatronic applications and a rapid prototyping board based on FPGAs View full abstract»

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  • An approach to module binding by fuzzy partitioning

    Page(s): 58 - 63
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    A new method for dealing with the problem of module selection on unscheduled behavioral descriptions is described. The method is based on the application to partitioning of some results of fuzzy set theory. It inherits, from its theoretical basis, some interesting properties, such as global treatment of similarity among operators, and computational simplicity View full abstract»

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  • GAFPGA: Genetic algorithm for FPGA technology mapping

    Page(s): 300 - 305
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    A method for solving the technology mapping problem for field-programmable gate arrays that is based on the genetic algorithm is presented. The genetic algorithm simultaneously optimizes a set of solutions, which makes it a very powerful optimization technique. However, due to the highly constrained search spaces for design automation problems, the application of the genetic algorithm is not straightforward. It is shown that this limitation can be overcome by enhancing the genetic search appropriately. The performance of the enhanced genetic search is demonstrated through experimental results for the technology mapping problem View full abstract»

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  • The concept of superprocesses for high-level synthesis and their VHDL modelling

    Page(s): 480 - 485
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    The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed View full abstract»

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  • JOGM: A CMOS cell layout style using jogged transistor gates

    Page(s): 184 - 188
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    A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45° jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested View full abstract»

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  • A net-based semantics for VHDL

    Page(s): 514 - 519
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    The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs View full abstract»

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  • Fast Boolean matching for field-programmable gate arrays

    Page(s): 352 - 357
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    A key step in technology mapping for non-lookup-table (such as multiplexer) based FPGAs (field programmable gate arrays) is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm which requires only a few string comparisons for each matching operation. When compared to the matching algorithm by searching for isomorphism on all different BDDs (binary decision diagrams), the new algorithm is much faster with a modest increase of memory requirement. For example, the experimental results showed that in matching all three-input Boolean function against Actel's ACT1 logic module, the new algorithm is 634 times faster by using 19.9% more memory View full abstract»

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  • Modeling of real bistables in VHDL

    Page(s): 460 - 465
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    A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modeled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: a description of a more complex latch (D-type) and a description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented model provides very realistic information about the device behavior, which until now had to be obtained through electric simulation View full abstract»

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  • On over-the-cell channel routing

    Page(s): 110 - 115
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    The authors consider two over-the-cell channel routing problems: the over-the-cell planar routing problem and the over-the-cell net assignment problem. They present optimal algorithms for solving the two problems. Experimental results are also provided to demonstrate the efficiency and effectiveness of the algorithms View full abstract»

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  • DSP datapath synthesis eliminating global interconnect

    Page(s): 46 - 51
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    CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system View full abstract»

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  • Monitoring BIST by covers

    Page(s): 208 - 213
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    The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer View full abstract»

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  • An efficient tool for system-level verification of behaviors and temporal properties

    Page(s): 124 - 129
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    The use of process algebras is advocated as a solution for system-level description of structure, communication, and behavior, while an action-based temporal logic is used to specify and check system-level properties. It is shown how SEVERO, a tool for describing and verifying finite state systems, can be used to integrate in the unified framework of symbolic manipulations both descriptive and prescriptive aspects. Experimental results show the efficiency of the BDD (binary decision diagram)-based implementation of the proof procedures View full abstract»

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  • Technology independent boundary scan synthesis (design flow issues)

    Page(s): 416 - 421
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    A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed View full abstract»

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  • A novel and efficient technique for transient analysis of tightly coupled circuits: The integral equation method (IEM)

    Page(s): 86 - 89
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    A new method capable of simulating transient behavior of tightly coupled circuits with high precision and speed is proposed. It is based on the transformation of the differential equations into integral equations. The method is semi-analytic and is of the third order. It gives a net speed advantage (about one order of magnitude) over classical methods, especially for high precision (typically analog) circuits. It also gives an a priori error estimate which will reduce rejected steps View full abstract»

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  • A consistent nonlinear simulation environment based on improved harmonic balance techniques

    Page(s): 90 - 95
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    Nonlinear simulations of semiconductor networks, in both the time and the frequency domains, determine the accuracy of analog CAD tools. Conventional circuit simulators such as SPICE provide nonlinear simulation only in the time domain. Analysis outputs are often verified by the frequency-domain nonlinear harmonic balance (HB) techniques. However, inconsistency between the individually developed tools would easily invalidate this simulation/verification process. In addition, the HB algorithms also suffer from many convergence problems which exclude HB from general applications. The authors present a compiler-based design framework in association with the improved HB algorithms to provide consistent nonlinear simulations. Simulation algorithms are formulated directly on unified modeling primitives which are then used to construct device models. Application examples and simulation results are presented to demonstrate the effectiveness of the proposed methodology View full abstract»

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  • PCUBE: A performance driven placement algorithm for low power designs

    Page(s): 72 - 77
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    PCUBE, a performance driven placement algorithm for minimizing power consumption, is described. The problem is formulated as a constrained programming problem and is solved in two phases: global optimization and slot assignment. The objective function used during either phase is the total weighted net length, where net weights are calculated as the expected switching activities of gates driving the nets. Constraints on total path delays are also accounted for. On average, PCUBE reduces power consumption due to interconnect by 7% at the expense of 8% increase in the total wire length and 2% increase in circuit delay View full abstract»

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