Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

20-24 Sept. 1993

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  • Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (39 KB)
    Freely Available from IEEE
  • Graph based analysis of FPGA routing

    Publication Year: 1993, Page(s):104 - 109
    Cited by:  Papers (17)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB)

    The experimental results of FPGA (field programmable gate array) routing suggest that there are difficulties in mapping global routing to a predictable detailed routing for array type architectures. The authors develop a graph theoretical formulation of this mapping problem and show that it is NP-complete for both multi-pin net lists and two-pin net lists for the Xilinx-like routing model. They pr... View full abstract»

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  • The MODES Global Control Environment - A tool for rapid prototyping

    Publication Year: 1993, Page(s):338 - 343
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This paper presents a software environment for the rapid prototyping of CAD systems, the Global Control Environment (GCE). It basically provides a mechanism to define the user interface and to study possible interactions between internal applications without having to cope with a programming language. The GCE tool is currently used for the design of the MODES system, an environment for the automat... View full abstract»

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  • Toward a formal semantics of IEEE Std. VHDL 1076

    Publication Year: 1993, Page(s):526 - 531
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process ... View full abstract»

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  • Concepts and methods for version modeling

    Publication Year: 1993, Page(s):332 - 337
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Object versions are one of the most important data-modeling requirements for design environments. The authors describe the mechanisms for the creation of versioned objects (simple objects or composite objects) and the conversion of non-versioned objects into versioned form. They then explain the relationships between versions View full abstract»

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  • BEPPO: A data model for design representation

    Publication Year: 1993, Page(s):378 - 382
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The authors present a data model for design representation. BEPPO (Basic, Efficient, Portable, Persistent Objects) provides a data model, schema language, and schema invariant programming interface geared towards the representation of arbitrary design data. Its domain invariant concepts and well-defined interfaces to applications and to the underlying storage manager make it suitable as a flexible... View full abstract»

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  • A framework for macro- and micro-time to model VHDL attributes

    Publication Year: 1993, Page(s):520 - 525
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete ... View full abstract»

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  • Technology mapping for sequential circuits based on retiming techniques

    Publication Year: 1993, Page(s):318 - 323
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transform... View full abstract»

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  • GAUT: An architectural synthesis tool for dedicated signal processors

    Publication Year: 1993, Page(s):14 - 19
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    This paper describes a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUT takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The result... View full abstract»

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  • On over-the-cell channel routing

    Publication Year: 1993, Page(s):110 - 115
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The authors consider two over-the-cell channel routing problems: the over-the-cell planar routing problem and the over-the-cell net assignment problem. They present optimal algorithms for solving the two problems. Experimental results are also provided to demonstrate the efficiency and effectiveness of the algorithms View full abstract»

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  • Implementation of the conception of flexible integration within the CADS framework

    Publication Year: 1993, Page(s):366 - 371
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The flexible integration approach intended for the construction of open, tightly integrated CAD systems is presented. The conception of the approach, which is based on maximum flexibility of tool integration methods, design data representation, and data processing, is described in detail. Additionally, experiences in using flexible integration for the development of the CADS framework is reported View full abstract»

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  • A net-based semantics for VHDL

    Publication Year: 1993, Page(s):514 - 519
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs View full abstract»

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  • On the minimal test set for single fault location

    Publication Year: 1993, Page(s):265 - 270
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A new heuristic algorithm (based on the fault dictionary approach) that finds the minimal test set for locating single faults (of the stuck-at type) in a digital circuit, thus reducing the size of the fault dictionary, is presented. The proposed algorithm is based on finding the transitive closure of the vectors in the test set with respect to the functional dominancies using Warshall's algorithm ... View full abstract»

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  • A new logic minimization method for multiplexor-based FPGA synthesis

    Publication Year: 1993, Page(s):312 - 317
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don't care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on... View full abstract»

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  • Monitoring BIST by covers

    Publication Year: 1993, Page(s):208 - 213
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the sig... View full abstract»

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  • State-machine-development-tool for high-level-design entry and simulation

    Publication Year: 1993, Page(s):164 - 169
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and prov... View full abstract»

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  • High-level synthesis transformations for programmable architectures

    Publication Year: 1993, Page(s):8 - 13
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The application of high level synthesis techniques in connection with highly programmable VLSI (very large scale integration) architectures is presented. Very early prototype realizations of subcomponents of complex systems can be achieved for real-time test runs if automatic synthesis is applied. The efficiency and applicability of this approach will be demonstrated with realistic mechatronic app... View full abstract»

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  • An iterative combinational logic synthesis technique using spectral information

    Publication Year: 1993, Page(s):358 - 363
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The spectral information of a Boolean function provides data regarding the correlation between the input variables and the output of the function. A spectral based methodology for combinational logic synthesis using linear transforms is introduced. An analysis of the properties of the spectra obtained from these transforms is provided and a synthesis algorithm using spectral techniques is presente... View full abstract»

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  • State assignment for finite state machines using T flip-flops

    Publication Year: 1993, Page(s):396 - 401
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Considerable progress in the area of state assignment for PLA and multi-level finite state machine realizations was made in the last ten years. Although many finite state machines can be more efficiently implemented if T flip-flops are used as memory elements, research has concentrated on finite state machines using D flip-flop memory. A state assignment algorithm for finite state machines using T... View full abstract»

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  • A practical approach to EMC for printed circuit board (PCB) and multichip module (MCM) design

    Publication Year: 1993, Page(s):284 - 289
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The authors introduce a new tool to assist in ensuring electromagnetic compatibility (EMC): an expert system for measuring EMC design rules during printed circuit board (PCB) or multi-chip module (MCM) layout. The nature of the tool and its place in the design process are discussed and the perceived merits of this approach are presented View full abstract»

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  • Extended 0/1 LP formulation for the scheduling problem in high-level synthesis

    Publication Year: 1993, Page(s):226 - 231
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    An extended zero-one linear programming (O/1 LP) model for the scheduling problem in high-level synthesis is presented. As an extension to former approaches, the 0/1 LP model can handle multifunctional function units as well as different execution times for different instances of the same operation type. These extensions are very important for the applicability of general high-level synthesis tool... View full abstract»

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  • Industrial experimentation of high-level synthesis

    Publication Year: 1993, Page(s):506 - 511
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The use of the high-level synthesis system AMICAL for the architectural synthesis of the filter or subband synthesis described in the MPEG-AUDIO specification is described. AMICAL starts with a behavioral specification given in VHDL and generates a structural description that may feed existing silicon compilers acting at the logic and register transfer levels. AMICAL is an interactive tool, meanin... View full abstract»

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  • REGGEN-Test pattern generation on register transfer level

    Publication Year: 1993, Page(s):259 - 264
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The authors describe the functional test generator REGGEN on a register transfer level. The technique of the symbolic simulation was modified by new rules to simplify symbolic expressions. In the REGGEN system a fault simulator at the RT level is also implemented. The efficiency of the REGGEN system has been proved on several gate arrays View full abstract»

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  • Synchronous designs in VHDL

    Publication Year: 1993, Page(s):486 - 491
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the c... View full abstract»

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  • An approach to module binding by fuzzy partitioning

    Publication Year: 1993, Page(s):58 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A new method for dealing with the problem of module selection on unscheduled behavioral descriptions is described. The method is based on the application to partitioning of some results of fuzzy set theory. It inherits, from its theoretical basis, some interesting properties, such as global treatment of similarity among operators, and computational simplicity View full abstract»

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