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Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Date 20-24 Sept. 1993

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Displaying Results 1 - 25 of 91
  • Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

    Publication Year: 1993
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    Freely Available from IEEE
  • Graph based analysis of FPGA routing

    Publication Year: 1993 , Page(s): 104 - 109
    Cited by:  Papers (17)  |  Patents (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (622 KB)  

    The experimental results of FPGA (field programmable gate array) routing suggest that there are difficulties in mapping global routing to a predictable detailed routing for array type architectures. The authors develop a graph theoretical formulation of this mapping problem and show that it is NP-complete for both multi-pin net lists and two-pin net lists for the Xilinx-like routing model. They pr... View full abstract»

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  • TONIC: A timing database for VLSI design

    Publication Year: 1993 , Page(s): 426 - 431
    Cited by:  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (472 KB)  

    A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis ... View full abstract»

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  • Hierarchical test generation: Where we are, and where we should be going

    Publication Year: 1993 , Page(s): 434 - 439
    Cited by:  Papers (23)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB)  

    Complex VLSI (very large scale integration) system design with VHDL requires test generation techniques that work at different levels in the abstraction hierarchy. The author discusses approaches to test generation which attempt to address this issue. Areas of test generation considered are behavior-assisted gate-level and switch-level test generation, test construction from sub-component tests, a... View full abstract»

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  • Synthesis of functions and procedures in behavioral VHDL

    Publication Year: 1993 , Page(s): 560 - 565
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (508 KB)  

    VHDL procedures and functions greatly increase the power and utility of the language for specifying designs. While these constructs are being used extensively for modeling, most VHDL synthesis tools limit their synthesis to a single implementation style such as treating them as a component. The authors evaluate four techniques for the synthesis of procedures/functions and discuss their relative me... View full abstract»

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  • Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm

    Publication Year: 1993 , Page(s): 22 - 27
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (508 KB)  

    This paper describes a new partitioning algorithm, BISECT, which is an extension of the Fiduccia-Mattheyses (FM) algorithm that recursively combines clustering and iterative improvement. A post analysis of sequences of moves in one pass generates disjoint subsets of nodes for clustering. After clustering BISECT is applied again on the compacted circuit. BISECT is stabler, achieves results that can... View full abstract»

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  • Dynamic variable reordering for BDD minimization

    Publication Year: 1993 , Page(s): 130 - 135
    Cited by:  Papers (13)  |  Patents (8)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (508 KB)  

    Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD... View full abstract»

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  • A new optimization driven clustering algorithm for large circuits

    Publication Year: 1993 , Page(s): 28 - 32
    Cited by:  Papers (6)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (328 KB)  

    It is well known that doing clustering before cell placement could improve the quality of the placement and reduce the run time significantly. The authors present a clustering algorithm which is specially suitable for large designs. It uses local connectivity information to do clustering, and uses global connectivity information to do tie-breaking. Large scale real world circuits show that by this... View full abstract»

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  • On the modeling and testing of VHDL behavioral descriptions of sequential circuits

    Publication Year: 1993 , Page(s): 440 - 445
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (564 KB)  

    A new automatic test generation principle based on a formal modeling of VHDL behavioral descriptions is proposed. Using to the finite state machine representation and a formalism close to that of Petri nets, the authors define two models which represent all the concepts associated with a VHDL description. They then propose a generation principle which uses both forward and backward time processing View full abstract»

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  • Synthesis of complex VHDL operators

    Publication Year: 1993 , Page(s): 566 - 571
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (428 KB)  

    Behavioral descriptions in VHDL often take advantage of complex operations to describe the behavior of a system in a comprehensive way. Existing synthesis tools, however, are not able to handle the complete set of operations. A time expansive transformation is required to map the high level behavioral description to a lower level description containing only operations that can be processed by synt... View full abstract»

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  • Boolean matching based on Boolean unification

    Publication Year: 1993 , Page(s): 346 - 351
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (400 KB)  

    The authors consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and their associated don't-care sets. This is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems su... View full abstract»

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  • The MODES Global Control Environment - A tool for rapid prototyping

    Publication Year: 1993 , Page(s): 338 - 343
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (624 KB)  

    This paper presents a software environment for the rapid prototyping of CAD systems, the Global Control Environment (GCE). It basically provides a mechanism to define the user interface and to study possible interactions between internal applications without having to cope with a programming language. The GCE tool is currently used for the design of the MODES system, an environment for the automat... View full abstract»

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  • Test function embedding algorithms with application to interconnected finite state machines

    Publication Year: 1993 , Page(s): 219 - 224
    Cited by:  Papers (8)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (468 KB)  

    The authors present new algorithms for embedding a test function in the state diagram of a finite state machine. When possible, the test function is embedded in the given object machine without using an extra input line. When such embedding is not possible, an extra input line is added to the object machine to make the embedding possible. For the extra input case, partition theory and the state va... View full abstract»

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  • An approach to module binding by fuzzy partitioning

    Publication Year: 1993 , Page(s): 58 - 63
    Request Permissions | Click to expandAbstract | PDF file iconPDF (452 KB)  

    A new method for dealing with the problem of module selection on unscheduled behavioral descriptions is described. The method is based on the application to partitioning of some results of fuzzy set theory. It inherits, from its theoretical basis, some interesting properties, such as global treatment of similarity among operators, and computational simplicity View full abstract»

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  • VHDeLDO: A new mixed mode simulation

    Publication Year: 1993 , Page(s): 546 - 551
    Cited by:  Papers (5)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (444 KB)  

    Mixed-mode simulation has recently received increased interest not only in cases where analog and digital circuitries coexist in one integrated circuit, but also for a faster digital and complex circuitry which needs high precision in simulation. The importance of mixed mode simulation is highlighted, and its basic principles are described. VHD eLDO, a new mixed mode simulation, is pres... View full abstract»

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  • Technology mapping for sequential circuits based on retiming techniques

    Publication Year: 1993 , Page(s): 318 - 323
    Cited by:  Papers (8)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB)  

    A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transform... View full abstract»

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  • A formal model for coupling computer based system and physical systems

    Publication Year: 1993 , Page(s): 158 - 163
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (492 KB)  

    One of the main challenges of information technology is the development of heterogeneous systems consisting of digital and analog parts. A technique for the common modeling of the different system parts and their interfaces that allows development all parts of the system in a consistent manner is shown. This technique is based on extensions of predicate/transition nets. Based on this model tools f... View full abstract»

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  • Monitoring BIST by covers

    Publication Year: 1993 , Page(s): 208 - 213
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (360 KB)  

    The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the sig... View full abstract»

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  • A framework for macro- and micro-time to model VHDL attributes

    Publication Year: 1993 , Page(s): 520 - 525
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (408 KB)  

    The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete ... View full abstract»

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  • A performance driven hierarchical partitioning placement algorithm

    Publication Year: 1993 , Page(s): 33 - 38
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB)  

    A new hierarchical partitioning placement algorithm is presented. The objective function is formulated as a weighted sum of the total wire length and the maximum circuit delay. Special balancing rules are used to assure a good balance between the numbers of components in the regions. Total wire length and maximum circuit delay are estimated and updated efficiently at each step of the partitioning ... View full abstract»

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  • Aspects of realizing the CFI design representation specification in the NELSIS framework

    Publication Year: 1993 , Page(s): 372 - 377
    Request Permissions | Click to expandAbstract | PDF file iconPDF (516 KB)  

    The CFI (CAD Framework initiative) organization aims to provide solutions for concurrent engineering by defining a set of standard textual specifications for interfaces that should enable ECAD tool consumers to incorporate tools from various vendors. The most mature of these specifications is the DRPI, a programming interface which specifies the data schema and functions for manipulating elementar... View full abstract»

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  • A new performance driven macro-cell placement algorithm

    Publication Year: 1993 , Page(s): 66 - 71
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (580 KB)  

    The authors present a new performance-driven macro-cell placement algorithm. They introduce the concept of a window which is an estimate of the initial placement of a module. There are three phases in the algorithm. In phase one, an initial window for each module is constructed. In phase two, a novel force-directed approach is used to reduce the size of each window in an iterative process so as to... View full abstract»

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  • REGGEN-Test pattern generation on register transfer level

    Publication Year: 1993 , Page(s): 259 - 264
    Request Permissions | Click to expandAbstract | PDF file iconPDF (432 KB)  

    The authors describe the functional test generator REGGEN on a register transfer level. The technique of the symbolic simulation was modified by new rules to simplify symbolic expressions. In the REGGEN system a fault simulator at the RT level is also implemented. The efficiency of the REGGEN system has been proved on several gate arrays View full abstract»

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  • Using VHDL for HW/SW co-specification

    Publication Year: 1993 , Page(s): 500 - 505
    Cited by:  Papers (14)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (444 KB)  

    HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design wher... View full abstract»

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  • Top-down modeling of RISC processors in VHDL

    Publication Year: 1993 , Page(s): 454 - 459
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (556 KB)  

    The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usef... View full abstract»

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