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Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

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Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Date 20-24 Sept. 1993

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Title History

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

Graph based analysis of FPGA routing

SPAN: Tightly coupled thermal and electrical simulation

A performance driven hierarchical partitioning placement algorithm

Synthesis of complex VHDL operators

Realizing expression graphs using table-lookup FPGAs

Top-down modeling of RISC processors in VHDL

Test generation based on synthesizable VHDL descriptions

A consistent nonlinear simulation environment based on improved harmonic balance techniques

Concepts and methods for version modeling

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis

Fast Boolean matching for field-programmable gate arrays

Register allocation for data flow graphs with conditional branches and loops

Next generation environment for extremely fast test pattern generation

A new logic minimization method for multiplexor-based FPGA synthesis

The CALLAS synthesis system and its application to mechatronic ASIC design problems

Using VHDL for HW/SW co-specification

Features supporting system-level specification in HDLs

High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device

A framework for macro- and micro-time to model VHDL attributes

Dynamic variable reordering for BDD minimization

Toward a formal semantics of IEEE Std. VHDL 1076

Locally optimistic methods of concurrent simulation

Hierarchical test generation: Where we are, and where we should be going

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