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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

20-24 Sept. 1993

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  • Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (39 KB)
    Freely Available from IEEE
  • Graph based analysis of FPGA routing

    Publication Year: 1993, Page(s):104 - 109
    Cited by:  Papers (17)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB)

    The experimental results of FPGA (field programmable gate array) routing suggest that there are difficulties in mapping global routing to a predictable detailed routing for array type architectures. The authors develop a graph theoretical formulation of this mapping problem and show that it is NP-complete for both multi-pin net lists and two-pin net lists for the Xilinx-like routing model. They pr... View full abstract»

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  • State-machine-development-tool for high-level-design entry and simulation

    Publication Year: 1993, Page(s):164 - 169
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and prov... View full abstract»

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  • A formal model for coupling computer based system and physical systems

    Publication Year: 1993, Page(s):158 - 163
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    One of the main challenges of information technology is the development of heterogeneous systems consisting of digital and analog parts. A technique for the common modeling of the different system parts and their interfaces that allows development all parts of the system in a consistent manner is shown. This technique is based on extensions of predicate/transition nets. Based on this model tools f... View full abstract»

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  • Modelling aspects of system level design

    Publication Year: 1993, Page(s):534 - 539
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The necessity for a common modeling approach for heterogeneous systems is discussed. As an example for such a modeling technique, extended predicate/transition nets (Pr/T-Nets) are introduced. These nets can combine modeling in a declarative way by means of first order logic with an operational interpretation inherited from Petri nets. The added concepts of hierarchy and recursion allow the descri... View full abstract»

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  • Interface specification and synthesis for VHDL processes

    Publication Year: 1993, Page(s):152 - 157
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification... View full abstract»

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  • Toward a formal semantics of IEEE Std. VHDL 1076

    Publication Year: 1993, Page(s):526 - 531
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process ... View full abstract»

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  • A new optimization driven clustering algorithm for large circuits

    Publication Year: 1993, Page(s):28 - 32
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    It is well known that doing clustering before cell placement could improve the quality of the placement and reduce the run time significantly. The authors present a clustering algorithm which is specially suitable for large designs. It uses local connectivity information to do clustering, and uses global connectivity information to do tie-breaking. Large scale real world circuits show that by this... View full abstract»

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  • PDAS: Processor design automation system

    Publication Year: 1993, Page(s):144 - 149
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The PDAS (Processor Design Automation System) is a new approach to design automation that uses formal methods to achieve a new level of design power and the ability to formally validate designs. The idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate... View full abstract»

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  • A framework for macro- and micro-time to model VHDL attributes

    Publication Year: 1993, Page(s):520 - 525
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete ... View full abstract»

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  • An iterative combinational logic synthesis technique using spectral information

    Publication Year: 1993, Page(s):358 - 363
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The spectral information of a Boolean function provides data regarding the correlation between the input variables and the output of the function. A spectral based methodology for combinational logic synthesis using linear transforms is introduced. An analysis of the properties of the spectra obtained from these transforms is provided and a synthesis algorithm using spectral techniques is presente... View full abstract»

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  • Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm

    Publication Year: 1993, Page(s):22 - 27
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    This paper describes a new partitioning algorithm, BISECT, which is an extension of the Fiduccia-Mattheyses (FM) algorithm that recursively combines clustering and iterative improvement. A post analysis of sequences of moves in one pass generates disjoint subsets of nodes for clustering. After clustering BISECT is applied again on the compacted circuit. BISECT is stabler, achieves results that can... View full abstract»

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  • An approach to CAD database support of design consistency control

    Publication Year: 1993, Page(s):326 - 331
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    CAD database services which support CAD tools in preserving design consistency are presented. Design consistency is briefly defined. Interactive design tools require support with respect to the specification of consistency rules, check points, and reactions to checks. Services of the object oriented IREEN database system designed to meet these requirements are presented. The authors introduce task... View full abstract»

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  • Computer-aided technique for optimal design of defect-tolerant VLSI with built-in redundancy

    Publication Year: 1993, Page(s):136 - 141
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Methods for taking account of the redundancy influence on the VLSI yield are developed. Using some fundamental redundancy arrangement methods, the interrelation between parameters of initial units and redundant hardware is discussed. On this basis, the generalized design approach is proposed. It can be adapted to demands of application-specific redundant unit design. Based on this approach the pro... View full abstract»

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  • On the implementation of an efficient performance driven generator for conditional-sum-adders

    Publication Year: 1993, Page(s):402 - 407
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and tn , the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay ⩽tn, if such a circuit exists View full abstract»

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  • A net-based semantics for VHDL

    Publication Year: 1993, Page(s):514 - 519
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs View full abstract»

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  • Fast Boolean matching for field-programmable gate arrays

    Publication Year: 1993, Page(s):352 - 357
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A key step in technology mapping for non-lookup-table (such as multiplexer) based FPGAs (field programmable gate arrays) is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm whic... View full abstract»

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  • Regular schedules for scalable design of IIR filters

    Publication Year: 1993, Page(s):52 - 57
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The authors present regular schedules, a class of parallel schedules for computing mth-order infinite-impulse response (IIR) filters. These schedules permit the implementation of IIR filters on a family of scalable parallel architectures with varying price/performance characteristics, enabling designers to effectively explore the design space of parallel IIR filter implementations. The technique i... View full abstract»

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  • GAUT: An architectural synthesis tool for dedicated signal processors

    Publication Year: 1993, Page(s):14 - 19
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    This paper describes a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUT takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The result... View full abstract»

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  • Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD

    Publication Year: 1993, Page(s):78 - 83
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The simulated annealing (SA) algorithm has been applied to every difficult optimization problem in VLSI (very large scale integration) CAD. Existing SA implementations use monotone decreasing, or cooling, temperature schedules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that challenges the correctness o... View full abstract»

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  • Dynamic variable reordering for BDD minimization

    Publication Year: 1993, Page(s):130 - 135
    Cited by:  Papers (12)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD... View full abstract»

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  • State assignment for finite state machines using T flip-flops

    Publication Year: 1993, Page(s):396 - 401
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Considerable progress in the area of state assignment for PLA and multi-level finite state machine realizations was made in the last ten years. Although many finite state machines can be more efficiently implemented if T flip-flops are used as memory elements, research has concentrated on finite state machines using D flip-flop memory. A state assignment algorithm for finite state machines using T... View full abstract»

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  • Industrial experimentation of high-level synthesis

    Publication Year: 1993, Page(s):506 - 511
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The use of the high-level synthesis system AMICAL for the architectural synthesis of the filter or subband synthesis described in the MPEG-AUDIO specification is described. AMICAL starts with a behavioral specification given in VHDL and generates a structural description that may feed existing silicon compilers acting at the logic and register transfer levels. AMICAL is an interactive tool, meanin... View full abstract»

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  • Boolean matching based on Boolean unification

    Publication Year: 1993, Page(s):346 - 351
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The authors consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and their associated don't-care sets. This is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems su... View full abstract»

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  • JOGM: A CMOS cell layout style using jogged transistor gates

    Publication Year: 1993, Page(s):184 - 188
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45° jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested View full abstract»

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