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ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Date 19-23 Sept. 1994

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Displaying Results 1 - 25 of 104
  • Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • Four channel DS1 framer

    Publication Year: 1994, Page(s):445 - 448
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A four channel DS1 framer chip has been developed for deployment in multichannel T1 systems, SONET add-drop multiplexers, T3 multiplexes, and ATM over T1 applications. Area reduction was realized through the use of a high speed clock, permitting use of shared resources and construction of simple arbiters for single port RAM. For further gate reduction, a state-machine based framing algorithm utili... View full abstract»

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  • A fast logarithm converter

    Publication Year: 1994, Page(s):450 - 453
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Divisions, square and square root operations or, in general, exponentiations are performed frequently in computer graphics algorithms, but are either slow if done by software or expensive if implemented in hardware. An elegant way to solve this problem is to transform the operands into the logarithm, turning divisions into subtractions and exponentiations into multiplications, and the results back... View full abstract»

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  • Taking advantage of reconfigurable logic

    Publication Year: 1994, Page(s):227 - 230
    Cited by:  Papers (9)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The availability of programmable logic devices based on static memory cells allows the implementation of “soft” hardware - that is, logic devices whose functions can be changed while they remain resident in system. A growing number of SRAM-based Field Programmable Gate Array (FPGA) users are taking advantage of this capability. In general, these applications of reconfigurable logic fal... View full abstract»

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  • Behavioral modeling techniques for analog and mixed signal design

    Publication Year: 1994, Page(s):319 - 322
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    A methodology for developing analog and mixed signal behavioral models is presented. The mathematical concepts for modeling various standard analog and mixed signal building blocks are discussed. For each component to be modeled, parameters ace developed based on the physical characteristics of that component to be modeled. Models of varying degrees of complexity are thus developed and can be used... View full abstract»

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  • Pipelined 50 MHz CMOS ASIC for 32 bit binary to residue conversion and residue to binary conversion

    Publication Year: 1994, Page(s):454 - 457
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    A custom CMOS ASIC is designed for a 32 bit binary to residue converter (BRC) to permit residue number system (RNS) operations using 8 moduli with 3 to 5 bit words. A custom ASIC design is also given for the corresponding residue to binary converter (RBC) to convert the 8 RNS moduli words to a unique 32 bit binary number. The result is a complete simulated pipelined design which supports a clock f... View full abstract»

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  • FPGA development tools: keeping pace with design complexity

    Publication Year: 1994, Page(s):232 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    As the density and complexity of FPGA-based designs increases beyond 10,000 gates, highly-integrated and automated development tools will be required. Several recent trends in development system capabilities are helping designers meet the twin challenges of growing design complexity and increasing time-to-market pressures View full abstract»

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  • Characterization of opens in logic circuits

    Publication Year: 1994, Page(s):358 - 361
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    We present an algorithm for extracting opens in rectilinear circuit layouts using a plane-sweep technique. An implementation of the algorithm is used to characterize realistic opens in combinational circuit layouts. The occurrence of three types of opens possible in standard cells is examined. The number of single and multiple stuck-at faults due to opens in benchmark circuits is determined, assum... View full abstract»

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  • AHDL modelling to support top-down design of mixed-signal ASICs

    Publication Year: 1994, Page(s):166 - 169
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    With the availability of analog hardware description languages (AHDL), there are new creative ways of solving mixed-signal simulation and modelling problems. Two top-down modelling approaches for a new mixed-signal Artificial Neural Network (ANN) are presented illustrating how AHDLs are making top-down design of mixed-signal ASICs realistic. The trade-offs involved are discussed View full abstract»

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  • Model-adaptable MOSFET parameter extraction method using a common intermediate model

    Publication Year: 1994, Page(s):323 - 326
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    In this paper, a model-adaptable MOSFET parameter extraction method is discussed. A salient feature of the method is that model dependency of initial value estimation, which is crucial for successful extraction with a numerical optimization technique, is eliminated as much as possible by introducing an intermediate model. We have verified the effectiveness of the method by adopting it to major SPI... View full abstract»

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  • A 60 MHz ASIC β bit serial/parallel multiplier

    Publication Year: 1994, Page(s):458 - 461
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    This paper presents a hardware implementation of a β-bit 16×16 serial/parallel multiplier (β=2). The circuit was implemented using differential pass transistor logic (DPTL). The chip has 3000 transistors and dissipates 150 mW at 5 V and 60 MHz. The multiplier was fabricated in 2-micron CMOS technology with a 1.7 mm×1.7 mm die, has been tested and is fully functional View full abstract»

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  • A gradient processor for high speed medical imaging

    Publication Year: 1994, Page(s):246 - 249
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents a gradient processor constructed with enhanced multiplier structures. The gradient processor is part of a shading processor being developed for a high performance medical imaging system with a display rate of at least 30 frames per second. The proposed system overcomes current image resolution and frame-rate limitations through the use of custom high-speed processors. The gradi... View full abstract»

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  • Dynamic power supply current monitoring of SRAMs

    Publication Year: 1994, Page(s):370 - 373
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, we report the results of a physical experiment aimed at assessing a new test method for CMOS SRAMs. The test method involves a new and simple philosophy for testing: monitor the switching behavior of a circuit rather than just the output logic state. Observing the dynamic (transient) power supply current can lead to drastic improvement in “real” defect coverage. We use t... View full abstract»

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  • A flexible repetitive CSD code filter processor unit in CMOS

    Publication Year: 1994, Page(s):261 - 264
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    We introduce a filter processor unit that realizes digital nonrecursive (FIR) and recursive (IIR) filtering with optimal selectable coefficient, data wordlength and filter order. This flexibility is achieved by combination of four identical filter modules. The design is carried out in a 1.0 μ CMOS process; additionally a multiplier-free second order ΣΔ-modulator is implemented. It o... View full abstract»

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  • A static technique for high-speed CMOS state machine design

    Publication Year: 1994, Page(s):108 - 111
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    This paper presents a technique for designing CMOS high-speed state machines with a clock frequency ranging from DC to greater than 130 MHz in 1.2-μm technology. This technique applies weak feedback to known high-speed dynamic circuits to achieve both static and high-speed capability. Two-phase nonoverlapping clocking is used to eliminate any possible races. Propagation delays of critical paths... View full abstract»

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  • Optimal buffered clock tree synthesis

    Publication Year: 1994, Page(s):130 - 133
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Given a topology and a library of buffers, we propose a clock buffer synthesis using a dynamic programming algorithm which finds optimum buffer sizes and insertion levels. At the same time, we optimize wire widths which further reduces propagation delay and the sensitivity of clock skew. Careful fine tuning by shifting buffer locations at the last stage preserves the zero skew property and reduces... View full abstract»

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  • A 1-MHz and 16-bit ΣΔ DAC with a 224th-order reconstruction FIR-filter using only 9 nonzero taps

    Publication Year: 1994, Page(s):29 - 32
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    This paper presents a 65-MHz clock rate and 32-times oversampling digital-to-analog sigma-delta converter in a standard 1 μm CMOS technology. The modulator have been designed for large bandwidth, large input range and low tonality. These demands have been met by a 6th-order lossy modulator. To utilize the modulator bandwidth and relax the reconstruction filter requirements a high-order FIR-filt... View full abstract»

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  • Performance-driven technology mapping for LUT-based FPGAs

    Publication Year: 1994, Page(s):182 - 185
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    An effective and iterative optimization technique is developed for technology mapping of lookup table based field programmable gate arrays. In the algorithm, minimal depth of a given optimized Boolean network is found and then the given cost function is minimized by “sweeping” nodes of the given Boolean network without increasing the depth optimization for reconvergent paths and duplic... View full abstract»

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  • On choosing the right error models for circuit testing

    Publication Year: 1994, Page(s):400 - 402
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    Error models help to correlate the fault model for a circuit with the error patterns observed at the output. This information is useful in both the design and the evaluation of a test strategy for the circuit. Two widely used error models are the symmetric and the independent model. In this paper, we propose a method to measure how closely a circuit follows each model, thus ensuring better test st... View full abstract»

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  • Low voltage, low power 13-bit linear voice codec with programmable analogue frontend

    Publication Year: 1994, Page(s):292 - 295
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A low-voltage, low-power 13-bit linear voice codec has been developed and implemented in 1.2 μm CMOS technology. At single supply voltage greater than 2.6 V and power dissipation of 20 mW it fulfils or exceeds all NET33 recommendations for digital handset terminals. Active area for a complete codec is 29 mm2. It can be used as an analogue frontend for DSP, digital cordless telephone,... View full abstract»

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  • Exploring ASIC design space at system level with a neural network estimator

    Publication Year: 1994, Page(s):67 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Estimators are critical tools in carrying out architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows the description of arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and pr... View full abstract»

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  • 50,000 gate ASIC prototyping PLD using four flex 8000 devices and a programmable interconnect

    Publication Year: 1994, Page(s):348 - 351
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Gate array designs are usually simulated to catch logic errors prior to silicon production. Emulation, or implementation and testing of the custom design in reprogrammable hardware, provides more exhaustive evaluation of design accuracy, but most hardware emulation systems are large and expensive. This paper presents a 50,000-gate programmable logic device (PLD) that has been developed to support ... View full abstract»

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  • A methodology for design verification

    Publication Year: 1994, Page(s):236 - 239
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and r... View full abstract»

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  • An analysis of shorts in CMOS standard cell circuits

    Publication Year: 1994, Page(s):362 - 365
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    In order to provide high levels of IC quality, we must be able to detect the presence of a very high percentage of the defects that may occur in circuits. Our long term goal is to address this problem by developing guidelines to design circuits to be more easily tested without requiring complex fault models or testing techniques. This paper is a first step towards this goal. This paper contains da... View full abstract»

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  • Low power via reduced switching activity and its application to PLAs

    Publication Year: 1994, Page(s):100 - 103
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    In this paper a systematic study of the expected switching activity (ESA) in combinational logic circuits is presented. Based on this study, a technique for reducing the power dissipation in two-level combinational logic is presented. The paper also discusses the switching activity in multilevel circuits View full abstract»

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