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Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

19-23 Sept. 1994

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Displaying Results 1 - 25 of 104
  • Personal appliance system and ASIC architecture

    Publication Year: 1994
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    Summary form only given as follows. A case analysis of four different solutions for Personal Communicators/PDAs is presented in tutorial form. The tutorial also addresses the design considerations for low-cost communication centric compute devices and technology trends which will shape the future of this new class of device. A look at the system requirements which are envisioned For this new class... View full abstract»

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  • Behavioral fault simulation and ATPG, system for VHDL

    Publication Year: 1994, Page(s):412 - 416
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (490 KB)

    Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fa... View full abstract»

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  • Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • AHDL modelling to support top-down design of mixed-signal ASICs

    Publication Year: 1994, Page(s):166 - 169
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    With the availability of analog hardware description languages (AHDL), there are new creative ways of solving mixed-signal simulation and modelling problems. Two top-down modelling approaches for a new mixed-signal Artificial Neural Network (ANN) are presented illustrating how AHDLs are making top-down design of mixed-signal ASICs realistic. The trade-offs involved are discussed View full abstract»

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  • Multi-GHz CMOS oscillators

    Publication Year: 1994, Page(s):41 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    A high frequency oscillator circuit in CMOS has been designed. The circuit uses inductors and capacitors to form a tank circuit while coupled CMOS inverters provide the positive feedback to sustain oscillations. The simulated performance is an order of magnitude greater than capable by conventional CMOS means View full abstract»

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  • Computer-aided design-verification vector generation

    Publication Year: 1994, Page(s):144 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    This paper describes the features and usage of a CAD tool that assists ASIC designers in the generation of design-verification vectors. The designer describes the ASIC interfaces as well as the desired operations to be performed in an assembly language format from which the CAD tool generates the actual input stimulus and timing relationships for the design-verification simulation View full abstract»

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  • A CMOS low voltage high performance interface

    Publication Year: 1994, Page(s):44 - 48
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Low voltage CMOS interface circuitry with self-correcting pull-up and pull-down output resistances to match the printed circuit board transmission line impedance, suitable for use in both series and parallel high-speed digital communication between integrated circuits and suitable for interfacing CMOS to heterogeneous logic (e.g. ECL), is described. The output driver impedance is controlled by the... View full abstract»

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  • Hierarchical mixed-level simulation of VHDL descriptions

    Publication Year: 1994, Page(s):170 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    We present a hierarchical multilevel VHDL simulator for large systems described at the transistor, gate and higher levels. We exploit the hierarchy and regularity in VHDL descriptions to reduce the memory requirements drastically. The simulation algorithm handles MOS digital designs with bidirectional signal flow. We have augmented VHDL descriptions with signal strengths and timing; and also propo... View full abstract»

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  • Synchronous performance and reliability improvement in pipelined ASICs

    Publication Year: 1994, Page(s):383 - 390
    Cited by:  Papers (15)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    The clock frequency of a synchronous circuit can be increased at the expense of increased system latency, area, and power using synchronous optimization techniques such as pipelining and retiming. Pipelining is well developed methodology, having been applied to almost every computer architecture from microprocessors to supercomputers. Retiming, on the other hand, has only recently become popular a... View full abstract»

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  • Recent developments in simulation

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    This tutorial presents an overview of recent developments in simulation. It will review the traditional SPICE techniques then introduce the more recent work including relaxation, waveform relaxation and asymptotic waveform evaluation View full abstract»

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  • Graphical specification of digital systems using interval temporal logic

    Publication Year: 1994, Page(s):148 - 151
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    This paper considers by means of an example how the behaviour of a digital circuit can be synthesised from a detail specification described in Interval Temporal Logic (ITL) which itself can be derived from a timing diagram View full abstract»

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  • Constant delay logic technology

    Publication Year: 1994, Page(s):49 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    The design of a digital IC is complicated by the range of timing that must be considered in the design process. Delay variations are commonly associated with power supply variations, temperature and process parameter variations. This paper documents one approach to reducing the delay variations, resulting from environmental conditions and process parameter variations, encountered in digital logic ... View full abstract»

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  • A proposed training curriculum in ASIC design

    Publication Year: 1994, Page(s):209 - 212
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    In this paper we propose comprehensive curriculum of training courses in the area of ASIC design. The curriculum consists of six program areas containing intensive courses, each ranging from two to four days in duration. The majority of the courses are hands-on, where the students work on PCs or workstations. All include in-class exercises to reinforce the topics learned. There are several points ... View full abstract»

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  • Macromodeling CMOS circuits for event driven simulation

    Publication Year: 1994, Page(s):174 - 177
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Using a piece-wise linear source for modeling the input transitions, the logic delays and output transition times are characterized and accurately macromodeled with errors typically less than 1%. Two different logic levels are used at the 70% and 30% points in the transitions to define the “logic events” to circumvent characterized negative delay times. Input capacitance characterizati... View full abstract»

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  • A fast Reed-Solomon and cyclic redundancy check encoding algorithm for optical disk error control

    Publication Year: 1994, Page(s):250 - 253
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Error control schemes have been applied to insure data integrity in high density digital mass storage medium. Specifically, optical disk applications are especially susceptible to various types of disturbances, and therefore require higher levels of error detection and correction capabilities. In this paper, efficient algorithms for implementing Cyclic Redundancy Check (CRC) and Reed-Solomon (RS) ... View full abstract»

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  • A digital CMOS programmable clock generator

    Publication Year: 1994, Page(s):280 - 287
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The digital CMOS software programmable clock generator (PCG) was designed as a macro cell to provide quadrature clocks for the Hobbit based Personal Communicators. The PCG produces a highly accurate variable frequency system clock from 20 kHz to 100 MHz (10 kHz to 50 MHz in quadrature), while using a single inexpensive crystal oscillator as a reference. Both the frequency and tolerance of PCG can ... View full abstract»

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  • Implementing a CMOS boundary-scan architecture tutorial

    Publication Year: 1994, Page(s):392 - 399
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This tutorial discusses the implementation of a boundary-scan architecture in CMOS. The boundary-scan testability features and principles, as discussed in the Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, are reviewed. Next, we describe the necessary steps to convert those principles into a practical boundary-scan architecture implementation. Our implementation was for ... View full abstract»

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  • Behavioral modeling techniques for analog and mixed signal design

    Publication Year: 1994, Page(s):319 - 322
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    A methodology for developing analog and mixed signal behavioral models is presented. The mathematical concepts for modeling various standard analog and mixed signal building blocks are discussed. For each component to be modeled, parameters ace developed based on the physical characteristics of that component to be modeled. Models of varying degrees of complexity are thus developed and can be used... View full abstract»

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  • Simple yet effective replication for FPGA partitioning

    Publication Year: 1994, Page(s):152 - 155
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    This paper deals with the partitioning of large digital designs for multiple FPGA based implementation. Partitioning for FPGAs is very constrained problem due to severe pin limitations. The approach described here uses efficient heuristics for replicating logic blocks. It is shown through experimentation that utilization can greatly be improved by replicating very small number of logic blocks. In ... View full abstract»

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  • Optimal buffered clock tree synthesis

    Publication Year: 1994, Page(s):130 - 133
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Given a topology and a library of buffers, we propose a clock buffer synthesis using a dynamic programming algorithm which finds optimum buffer sizes and insertion levels. At the same time, we optimize wire widths which further reduces propagation delay and the sensitivity of clock skew. Careful fine tuning by shifting buffer locations at the last stage preserves the zero skew property and reduces... View full abstract»

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  • Education in ASIC design using the SET concept

    Publication Year: 1994, Page(s):196 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    To keep pace with technological changes prevalent in engineering today, the academic community must devise novel approaches to bridge the gap between academia and industry. The Student Engineering Team (SET) concept presented in this paper addresses this issue without major restructuring of current curricula. It is illustrated by describing a student project which involves the development of a VLS... View full abstract»

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  • A methodology for design verification

    Publication Year: 1994, Page(s):236 - 239
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and r... View full abstract»

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  • Combining the top-down approach with bottom-up advantages in logic synthesis

    Publication Year: 1994, Page(s):54 - 57
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The current trend in logic synthesis of top-down ASIC designs has been towards offering the same advantages associated with bottom-up designs such as transistor level optimization with advanced algorithms. This paper proposes a method to exploit these benefits during logic synthesis. Top-down and bottom-up strategies are discussed and a way is shown how to combine both advantages of both methodolo... View full abstract»

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  • A first pass ASIC development methodology using logic emulation

    Publication Year: 1994, Page(s):214 - 218
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper describes a printer controller design utilizing a logic emulator to verify the functionality of the ASIC prior to fabrication. The utilization of logic emulation for ASIC prototyping enables both hardware and software development as well as system verification to proceed in parallel. This methodology allowed Apple to develop a new printer controller ASIC with first pass success, signifi... View full abstract»

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  • Exploring ASIC design space at system level with a neural network estimator

    Publication Year: 1994, Page(s):67 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Estimators are critical tools in carrying out architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows the description of arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and pr... View full abstract»

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