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VLSI Signal Processing, VI, 1993., [Workshop on]

Date 20-22 Oct. 1993

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Displaying Results 1 - 25 of 58
  • Proceedings of IEEE Workshop on VLSI Signal Processing

    Publication Year: 1993
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    Freely Available from IEEE
  • A scheduling framework for minimizing memory requirements of multirate DSP systems represented as dataflow graphs

    Publication Year: 1993 , Page(s): 188 - 196
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    Numerous design environments for signal processing use specification languages with semantics closely related to synchronous dataflow (SDF), a restricted form of dataflow that has proven efficient for describing and compiling multirate signal processing algorithms. An SDF representation allows the compiler freedom to explore different ways to sequence the computations in a program, and to evaluate the associated tradeoffs, such as those involving throughput, code size, and buffering requirements. To guide the scheduling process, compilers may apply some form of clustering, in which multiple computations are grouped together according to different criteria. The authors develop clustering techniques to synthesize minimum code size implementations of SDF programs, and describe techniques to incorporate arbitrary clustering strategies into a minimum code size scheduler View full abstract»

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  • Correction of lens-distortion for real-time image processing systems

    Publication Year: 1993 , Page(s): 316 - 324
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The authors present the design of a real-time imaging system, incorporating the correction of lens-distorted images. It may be used in medical applications (e.g. real-time X-ray image intensifiers), industrial robot vision products or consumer electronics. The system contains two different VLSI-circuits: a transformer and an interpolator. The transformer calculates an address that points to a pixel in the input image. Since this address hardly ever is an exact pixel position, a cube-spline interpolator is used to calculate the pixel-intensity at the desired position View full abstract»

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  • Video compression for portable communication using pyramid vector quantization of subband coefficients

    Publication Year: 1993 , Page(s): 444 - 452
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The authors describes a video compression scheme that performs pyramid vector quantization (PVQ) of subband coefficients and a VLSI architecture for the PVQ decoder. This algorithm not only provides good compression performance, but also results in a low complexity, low power VLSI implementation. Furthermore, this algorithm demonstrates good error resiliency under severe channel distortion without the use of error correction codes. PVQ also allows encoding and decoding to be computation-based instead of memory-based, as in standard VQ, thus allowing for real-time video coding and eliminating the need for large memories. The algorithm and its performance are described in detail, and the chip architecture of the PVQ decoder is presented View full abstract»

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  • Generation of hardware machine models from instruction set descriptions

    Publication Year: 1993 , Page(s): 242 - 250
    Cited by:  Papers (13)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The authors describe how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from new generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example View full abstract»

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  • Synthesis methods for domain-specific multiprocessor systems including memory design

    Publication Year: 1993 , Page(s): 417 - 425
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    The authors' work is concerned with methods to synthesize heterogeneous, domain specific multiprocessor systems. Their results are mainly based on scheduling and allocation methods developed for data path synthesis. If unlimited computing resources are available, efficient solutions to the scheduling problem are known View full abstract»

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  • Specification, partitioning and design of a DAB channel decoder

    Publication Year: 1993 , Page(s): 21 - 29
    Cited by:  Papers (9)  |  Patents (4)
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    Digital Audio Broadcasting (DAB) is a logical consequence of the digital sound carriers such as Compact Disc and Digital Compact Cassette. In a later stage it may replace the traditional radio systems such as FM, leading to CD quality audio reception under almost all circumstances. The authors describe the design issues of a channel decoder for a DAB receiver and its path to an efficient ASIC implementation View full abstract»

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  • Portability methods in parametrized DSP module generators

    Publication Year: 1993 , Page(s): 260 - 268
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    Parametrized module generators can be widely utilized in the VLSI implementations of digital signal processing systems. By making the generators portable one can significantly simplify their later reutilization. The portability can be addressed either on system level, on macroblock level, or on leaf cell level. The applicable methods for achieving the portability on different levels are classified and reviewed. Practical and efficient methods for facilitating the technology porting to the next generation technologies are highlighted in example cases View full abstract»

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  • Systematic design optimization of a competitive soft-concatenated decoding system

    Publication Year: 1993 , Page(s): 105 - 113
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    Due to the advances in VLSI technology complete digital communication systems can today be implemented on single application specific VLSI circuits. The optimum choice of implementation parameters, such as signal wordlengths, is a critical design task since poor parameter choices can lead to costly designs. On the other hand, the high number of parameters to be selected span a large search space that is very difficult to handle. The authors present a new systematic approach to parameter selection and apply this approach to the design optimization of a decoding system for a concatenated coding scheme. Two convolutional codes are concatenated and both are decoded by soft decision decoding. This is facilitated by means of soft output decoding of the inner code. The performance of the scheme is better than that of the well known standard code with 64 states for moderate BER at equivalent implementation cost. The proposed coding scheme is thus an attractive alternative whenever high bit error rate performance is prerequisite, e.g. for digital HDTV transmission View full abstract»

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  • A minimally redundant radix-4 systolic array for high performance IIR filtering

    Publication Year: 1993 , Page(s): 168 - 176
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    The authors consider the radix-4 implementation of a parallel multiplier accumulator suitable for performing recursive filtering. A new parallel multiplier is presented which exploits the minimally redundant radix-4 number representation to nearly halve the area of previous radix-2 design and provide a 20% speed advantage. The architecture supports fine grain pipelining and has a computation time which is independent of wordlength View full abstract»

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  • Large matrix inversion using state space techniques

    Publication Year: 1993 , Page(s): 406 - 414
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    A new computational technique is presented by which large structured matrices can be inverted. The specified matrix is viewed as the input-output operator of a time-varying system. Recently developed state space algorithms which apply to such systems are then used to compute a QR factorization first and subsequently the inverse of the matrix, starting from a state realization of the matrix. The new algorithms apply in principle to any matrix. They are efficient if the structure of the matrix is such that the number of states of its time-varying state realization is small in comparison to its dimensions View full abstract»

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  • Systolic array for recursive least squares by inverse iterations

    Publication Year: 1993 , Page(s): 435 - 443
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    A novel systolic array for implementing recursive least squares based on the method of inverse iterations is described. It is based on Givens rotations and takes the form of a relatively simple orthogonally connected array. Since the inverse iterations method involves a major computational feedback loop, the derivation of a pipelined processor array is highly non-trivial View full abstract»

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  • Optimal wordlength assignment for the discrete wavelet transform in VLSI

    Publication Year: 1993 , Page(s): 325 - 333
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    Dedicated VLSI implementation of DSP functions allows unequal wordlengths to be assigned to different intermediate variables in order to trade precision for area, power and speed. The authors present a method for determining the optimal wordlengths for the filter bank tree of the Discrete Wavelet Transform (DWT). In several applications such as image or speech coding, only the lower half subband is iteratively decomposed in the filter bank tree structure until a desired frequency resolution is achieved. As a result, the roundoff noise contribution (due to finite wordlength assignment) to the highest subband can be substantially different from that of the other subbands. The fixed point roundoff error expressions for DWT are derived from a statistical model. The optimal wordlength assignment problem is then formulated as balancing the roundoff noise power for each subband, while satisfying a desired total output noise constraint. It is shown to be a Quadratic Programming (QP) problem in general. For the particular case under consideration, it is then simplified and shown to be reducible to a Constrained Least Squares (CLS) problem. A solution to this CLS problem determines the optimal wordlengths. The results illustrate that it is possible to achieve a significant reduction in the wordlength assigned to the output of the high-pass filter(s) in the analysis filter bank. A reduced wordlength in turn implies a more efficient data compression. Thus, the incorporation of precision constraints can yield additional bit-savings in applications like subband coding View full abstract»

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  • A cryptographic chip for ISDN and high speed multi-media applications

    Publication Year: 1993 , Page(s): 12 - 20
    Cited by:  Patents (1)
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    The design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequence generation (Substream) and cryptographic hashing (Subhash). In Substream mode the chip can be used for stream encryption/decryption under control of a 256-bit key. A cryptographic resynchronization mechanism is provided for fast accessibility encrypted data by legitimate parties. Application fields include the real-time encryption of digital HDTV signals as well as high speed telecommunication and networking such as ATM. The chip has been fabricated within the INVOMEC/EUROCHIP educational VLSI Design Facilities in MIETEC 2.4μ CMOS technology. Measured samples are operating at encryption/decryption rates of 286 Mbits/sec and hashing rates of 572 Mbits/sec. The operation of the chip is demonstrated by setup showing the real-time encryption and decryption of digitized PAL color composite video signals. The designed cryptographic module can be used as a stand-alone device or embedded as a mega-block in a larger chip View full abstract»

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  • On computing the 2-D modulated lapped transform in real-time [and VLSI implementation]

    Publication Year: 1993 , Page(s): 361 - 369
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    The Lapped Orthogonal Transforms have successfully been used in image coding and motion estimation since they alleviate the blocking effect, common in transform domain techniques. The authors consider the hardware implementation of the two-dimensional Modulated Lapped Transform. A time-recursive approach in algorithm design is adopted that yields a modular, regular, highly parallel architecture requiring local communication. Overall, the architecture proposed for the N × N MLT requires O(N) processing elements, O(N2) storage elements and can be realized very efficiently in VLSI. Moreover, there is no restriction on N. Being fully pipelined this architecture may achieve the throughput rate of N cycles per N × N successive input data frame, and thus it is suitable for real time computation of the 2-D MLT View full abstract»

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  • VLSI architectural synthesis for an acoustic echo cancellation application

    Publication Year: 1993 , Page(s): 84 - 92
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    An architectural synthesis tool dedicated to Digital Signal Processing, GAUT, is presented. Synthesis is achieved under both real time and silicon cost constraints. The algorithm is first described using a high level behavioral language. The control and data flow graph (CDFG) obtained is synthesized into processing control, memorization and communication units. These specifications are in VHDL, thus enabling the interconnection with CAD and simulation tools. An application of acoustic echo cancellation was synthesized, and it is show that the method may also be used to evaluate the complexity of various signal processing algorithms that satisfy the application constraints View full abstract»

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  • Using a frequency weighted error function to improve performance of adaptive filters

    Publication Year: 1993 , Page(s): 379 - 387
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    The authors presents an enhancement to the error measurement function of an adaptive process. This enhancement enables the error to be weighted differently in different parts of the spectrum. The result is used to produce an adaptive process that adapts better to a given system, over a selective range of frequencies. The equations for an adaptive FIR system are derived. Finally some simulation results using the suggested method with an LMS process, are given View full abstract»

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  • Fast and accurate Toeplitz matrix triangulation for linear prediction

    Publication Year: 1993 , Page(s): 343 - 351
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    The authors present a new O(mn) algorithm for triangularizing an m × n Toeplitz matrix. The algorithm is based on the previously developed recursive algorithms that exploit the Toeplitz structure and compute each row of the triangular factor via updating and downdating steps. We monitor the conditioning of the downdating problems, and use the method of corrected semi-normal equations to obtain higher accuracy for ill-conditioned downdating problems. Numerical experiments show that the new algorithm improves the accuracy significantly while the computational complexity stays in O(mn) View full abstract»

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  • Image processing board for real-time extraction of line symbols from video sequences for AGV

    Publication Year: 1993 , Page(s): 30 - 38
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    For a vision based vehicle guidance system a compact image processing unit has been developed which extracts straight lines as symbols for the street boundaries. This unit consists of two ASICs for the segmentation of symbols and a microcontroller for high level processing. The implemented sequence of algorithms comprises gradient operation, edge thinning, line verification, Hough transformation and a rule based post processing. Although the image processing unit is originally developed for vehicle guidance the hardware can be used for other industrial and robotic applications as well View full abstract»

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  • The cell level description of systolic block regularised QR filter

    Publication Year: 1993 , Page(s): 298 - 306
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    A general theory invented by Kulhavy provides the firm background for regularisation of identification with guaranteed properties. It pays for the generality by an increase of computational complexity. For this reason an order in magnitude faster, block regularised parameter estimator has been proposed. The author presents the cell-level description of the systolic array implementation of the block regularised algorithm, preserving the excellent properties of Kulhavy regularisation View full abstract»

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  • Constrained least squares estimation of sinusoidal frequencies and application to time frequency analysis of chirp signals

    Publication Year: 1993 , Page(s): 334 - 342
    Cited by:  Papers (1)
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    In this paper, we consider the problem of least squares estimation of the frequency of a single noiseless sinusoidal signal and derive a least squares algorithm to estimate the frequency parameters. We show the effects of adding noise to the signal. Secondly, we propose two adaptive versions of the algorithm and apply them to determine the instantaneous frequency of a modulated tone. We illustrate results by several chirp signals. By adding mild amounts of noise, we show that the algorithm is fairly robust. We feel that the computational simplicity of this algorithm makes it a competitive alternative to the modern time frequency signal analysis methods for monocomponent signals View full abstract»

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  • A high performance vector quantisation chip

    Publication Year: 1993 , Page(s): 159 - 167
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    A demonstrator chip is described for real time speech vector quantisation applications. The chip has been fabricated in a 1.2 micron CMOS technology and contains 38,000 transistors. It occupies a die area of only (4.8 × 4.6) mm2 and can perform over 80 million multiplyaccumulate operations per second. The chip fully demonstrates the benefits which result from using a regular dedicated VLSI architecture View full abstract»

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  • An efficient multi-window display-memory architecture for full-motion video signals

    Publication Year: 1993 , Page(s): 66 - 74
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    A new architecture is proposed that drastically reduces the memory requirements for full motion video processing functions such as scan-conversions source synchronization and zooming for multiple video input sources. It has a simple modular structure which incorporate a few inexpensive DRAMs with a total storage capacity of one single video-frame. Reduction of memory capacity and real-time processing power is achieved by computing (off-line) an efficient schedule for all memory-access requests associated with a specific window configuration. This schedule is then instantly compiled into micro-programs which are down-loaded into the real-time controllers of the architecture View full abstract»

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  • A multi-cycle operational signal processing core for an adaptive equalizer for magnetic system application

    Publication Year: 1993 , Page(s): 150 - 157
    Cited by:  Papers (3)
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    An adaptive equalizer has been developed using multi-cycle operational signal processing cores; an equalizing filtering core and a coefficient calculating core including an IIR stabilizing filter. The authors propose an IIR stabilizing filter core and discuss the stability of the adaptive equalizer. The proposed IIR filter core needs less than half number of gates of an FIR filter core realized in a straight ford way of design, and it keeps excellent stability. Each core, an equalizing filtering core and a coefficient calculating core, operates seven cycle time of 20ns during a sampling period. The number of gates was a third of straight ford design where one operator is employed during a sampling period. The proposed architecture made it possible to realize a fully digital equalizer with maximum likelihood detection and clock recovery View full abstract»

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  • Highly concurrent architectures for recursive median filters

    Publication Year: 1993 , Page(s): 471 - 479
    Cited by:  Papers (1)
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    The authors present highly concurrent (i) array architectures (ii) stack filter architectures and (iii) sorting network architectures for recursive median filters. In order to pipeline these architectures to any level, the authors develop clustered look ahead and scattered look ahead realizations of the recursive median filters. These realizations are based on approximating the recursive median filter with a weighted recursive median filter. New array architectures and stack filter architectures are developed for weighted recursive median filters that support clustered look ahead, and new sorting network architectures for weighted recursive median filters that support scattered look ahead. These architectures can be pipelined to any level with a corresponding linear increase in the hardware complexity. In addition, these architectures can also be used to implement the larger class of weighted order statistic filters View full abstract»

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