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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

16-18 Nov. 1993

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  • Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (638 KB)
    Freely Available from IEEE
  • LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets

    Publication Year: 1993, Page(s):160 - 165
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Deterministic testing is by far the most interesting built-in self-test (BIST) technique because of the minimal number of test patterns required and of the known fault coverage. However, it is still not applicable since none of the existing deterministic test pattern generators (TPGs) is at the same time efficient and small. The LFSROM architecture which is presented herein is thus an attempt to s... View full abstract»

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  • Fault modelisation of external shorts in CMOS circuits

    Publication Year: 1993, Page(s):237 - 242
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    As the density of VLSI CMOS circuits increases, external shorts are expected to become a very important failure. This paper analyzes the electrical behavior of static CMOS gates with external shorts. The fault modelization of such shorts is then considered in the context of functional testing. It is demonstrated that the detectability of a short with respect to functional testing depends on the sh... View full abstract»

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  • The driver/receiver conflict problem in interconnect testing with boundary-scan

    Publication Year: 1993, Page(s):210 - 214
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper explores the driver/receiver conflict problem in interconnect testing with bidirectional pins and 3-state output pins in boundary-scan. The objective is to have a higher-level (higher than chip) designer be aware of this conflict. Some existing algorithms are reviewed View full abstract»

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  • Additive cellular automata as an on-chip test pattern generator

    Publication Year: 1993, Page(s):166 - 171
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Cellular Automata (CA) has been already proposed for generation of pseudo-random, pseudo-exhaustive and two-pattern test vectors. In the present work, a new concept of intermediate boundary CA has been projected that circumvents the problems associated with the generation of pseudo-random patterns using null and periodic boundary CA. Generation of an arbitrary set of deterministic test patterns fo... View full abstract»

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  • A C-testable DCVS GF(2m) multiplier

    Publication Year: 1993, Page(s):204 - 209
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2m ) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is 13m+1 for a GF(2 m) multiplier View full abstract»

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  • Reliable fail-safe systems

    Publication Year: 1993, Page(s):32 - 37
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A fault-tolerant scheme is presented which is based on two copies of a self-checking module and a fail-safe interface. The interface preserves the modules' safety and becomes fault-tolerant by embedding appropriate self-testing capabilities. We show that, for self-checking module area overheads not exceeding the theoretical upper bound of √3-1 (73%), our fault-tolerant scheme is more reliabl... View full abstract»

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  • Bayesian inference for fault diagnosis in real-time distributed systems

    Publication Year: 1993, Page(s):333 - 338
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    We propose fault location strategies based on a Bayesian decision-theoretic approach. The proposed B-algorithm can locate the failed units in a distributed system with complexity which is linear in the number of subsystems in the network, making it suitable for hard real-time applications. The method is probabilistic and comparison-based, employing multiple incomplete test concepts View full abstract»

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  • State encoding and functional decomposition for self-checking sequential circuit design

    Publication Year: 1993, Page(s):293 - 297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking r... View full abstract»

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  • Optimal interconnect diagnosis

    Publication Year: 1993, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Interconnect diagnosis is an important problem in very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts among a given set of nets using the minimum number of tests. In this paper, we prove matching lower bounds for two non-adaptive diagnosis problems, and give an optimal algorithm for the adaptive... View full abstract»

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  • An algorithm for test generation of combinational circuits research and implementation for critical path tracing

    Publication Year: 1993, Page(s):26 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    An algorithm for test pattern generation of combinational logic circuits - critical path tracing is presented in this paper. Differing from other fault oriented test generation algorithms, this algorithm is circuit oriented and generates test pattern from primary outputs towards primary inputs in a circuit. In addition, it does not need fault simulation, i.e., when a test pattern is obtained all t... View full abstract»

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  • Achieving minimal hardware multiple signature analysis for BIST

    Publication Year: 1993, Page(s):311 - 316
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper proposes a new method for achieving minimal hardware multiple intermediate signature analysis whereby n signatures are checked against a single reference. With a single reference, checking multiple signatures requires the same amount of hardware as for checking only one. However, checking multiple signatures has many advantages. In comparison to the method described by Y. Wie and A Ivah... View full abstract»

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  • Computer aided testing system for LC cell's optical properties

    Publication Year: 1993, Page(s):330 - 332
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    This paper introduces our CAT system which is set up for testing the optical properties of LC (liquid crystal) cell. In this system, the transmission spectra of the LC cell at different voltages applied on LC film can be tested by computer control automatically. Simultaneously, the CIE1931 and CIE1971 chromaticity are calculated out in the program View full abstract»

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  • A global BIST methodology

    Publication Year: 1993, Page(s):154 - 159
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper presents a BIST methodology for CMOS gate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete self-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes affo... View full abstract»

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  • General design principles of self-testing code-disjoint PLAs

    Publication Year: 1993, Page(s):287 - 292
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper presents general principles of designing self-testing (ST) code-disjoint (CD) PLAs under fault model which covers three classes of typical PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for ST and CD is that the input code of a PLA is closed. The formal condition... View full abstract»

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  • An approach to large program testing with tool WHEN

    Publication Year: 1993, Page(s):132 - 137
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The problem to test large application and system programs efficiently in supercomputer systems is discussed. Many difficulties exist when large programs are concerned. In order to overcome some of these difficulties, we design a novel software tool named WHEN, which has been used to solve some dynamic internal testing problems, such as flexible flowtracing, debugging of deep rooted errors or fault... View full abstract»

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  • On the testability of cascaded Reed Muller circuits

    Publication Year: 1993, Page(s):268 - 273
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    One of the advantages of using Reed Muller representations to design logic circuits is known as the high testability of the realized circuits. However, there is little known about the testability of any type of multi-level Reed Muller circuits. In this paper, we analyze the testability of a class of multi-level Reed Muller circuits which are generated by the synthesis tool FACTOR. FACTOR uses matr... View full abstract»

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  • A current testing for CMOS static RAMs to reduce testing costs

    Publication Year: 1993, Page(s):231 - 236
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    This paper presents a methodology to reduce the testing costs of a CMOS static RAMs (SRAMs), based on a current testing. In this test method, the structure of SRAMs is modified so that all the cells can be driven simultaneously. A fault in the memory cell array can be detected by only observing the abnormal current. Since the whole cell array could be treated as if it were a single cell, the lengt... View full abstract»

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  • The complexity of determining the sequential diagnosability number in the Malek's comparison model

    Publication Year: 1993, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The problem of determining the sequential diagnosability number of a system in the Malek's comparison model is an important one. In this paper, we show that the decision version of this problem is co-NP complete for general systems, and we present an O(|E| |V|3/2 log 2(|V|)) algorithm for determining the sequential diagnosability number for a class of systems corresponding to... View full abstract»

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  • An approach to the analysis of the current testability of IC analog sections

    Publication Year: 1993, Page(s):82 - 87
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Integrated circuits considering mixed analog and digital section parts are becoming a strategic target of the microelectronic design methodologies. Focussing our attention on the testing aspect and knowing the interest and efficiency of current testing in digital circuits the possibility to extend this technique to analog parts is analyzed in this work. An analysis of the behavior of typical analo... View full abstract»

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  • Proof that Akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs

    Publication Year: 1993, Page(s):14 - 19
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clarify that Akers' test pattern generator can generate an MLTS for such CUT View full abstract»

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  • Neural network realization of Markov model of TMR systems with compensating failures

    Publication Year: 1993, Page(s):44 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Reliability synthesis as a reverse of reliability analysis has the same importance as reliability estimation. One important issue in reliability synthesis is to find failure rates and repair rates of units, given the desired reliability requirement. Compensation of failures can be very significant for fail-fast TMR systems. This paper presents a new model of TMR systems in which fail-fast rates an... View full abstract»

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  • On properties and implementations of inverting ALSC for use in built-in self-testing

    Publication Year: 1993, Page(s):305 - 310
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Clockwise inverting sequences of original pseudo-random ones are considered effective for two-pattern testing of CMOS circuits. This paper describes a class of circuits which can generate such sequences and conveniently referred as inverting ALSC (autonomous linear sequential circuit). The simulation results show that inverting ALSC generated sequences have strong dependency on the original cyclic... View full abstract»

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  • Application of homing sequences to synchronous sequential circuit testing

    Publication Year: 1993, Page(s):324 - 329
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    A test generation procedure for synchronous sequential circuits is proposed, that is based on the multiple observation times approach, and uses homing sequences, instead of conventionally used synchronizing sequences, to initialize the circuit. A procedure for computing homing sequences in sequential circuits, for which a state-table description is too large to be practical, is described, and expe... View full abstract»

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  • A new method for system diagnosis

    Publication Year: 1993, Page(s):147 - 152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    With the advent of parallel computing systems, the fault diagnosis of such systems becomes increasingly challenging and critical. In this paper, we first introduce the concept of binary decision diagram (BDD), based on which we present an efficient way to locate the faulty units according to what we call fault symptom (FS). The new technique is then proved to be optimal (shortest) in time-consumin... View full abstract»

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