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Test Symposium, 1993., Proceedings of the Second Asian

Date 16-18 Nov. 1993

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  • Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (638 KB)
    Freely Available from IEEE
  • The complexity of determining the sequential diagnosability number in the Malek's comparison model

    Publication Year: 1993, Page(s):191 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The problem of determining the sequential diagnosability number of a system in the Malek's comparison model is an important one. In this paper, we show that the decision version of this problem is co-NP complete for general systems, and we present an O(|E| |V|3/2 log 2(|V|)) algorithm for determining the sequential diagnosability number for a class of systems corresponding to... View full abstract»

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  • GID-testable two-dimensional sequential arrays for self-testing

    Publication Year: 1993, Page(s):225 - 229
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    This paper presents an approach for easily testable two-dimensional sequential arrays. This approach is an extension of GID (Group Identical and Different)-testability of combinational arrays in our previous work. In a GID-testable two-dimensional array, the primary x and y outputs are organized into groups and every group has more than one output. GID-testability not only ensures that identical t... View full abstract»

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  • Design of efficient totally self-checking checkers for m-out-of-n code

    Publication Year: 1993, Page(s):281 - 286
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper presents a new design method of efficient totally self-checking (TSC) checkers for m-out-of-n code. The design procedure has three steps. First, we append an appropriate number of 1's to the m/n code to get a k/2k code, and design a TSC checker for this k/2k code which can be easily constructed by the conventional method. Then, we delete the appended 1's and simplify the circuit to get ... View full abstract»

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  • An approach to large program testing with tool WHEN

    Publication Year: 1993, Page(s):132 - 137
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The problem to test large application and system programs efficiently in supercomputer systems is discussed. Many difficulties exist when large programs are concerned. In order to overcome some of these difficulties, we design a novel software tool named WHEN, which has been used to solve some dynamic internal testing problems, such as flexible flowtracing, debugging of deep rooted errors or fault... View full abstract»

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  • Multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths

    Publication Year: 1993, Page(s):185 - 190
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    We describe a method for multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths generated by a seven-valued calculus. Our method determines the set of all possible stuck-at faults from the faulty response observed at the primary output, based on deducing internal values along the sensitized path. By using the fault-free response observed at the prim... View full abstract»

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  • Design of monitored self-checking sequential circuits for enhanced fault models

    Publication Year: 1993, Page(s):298 - 303
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper discusses the design of monitored self-checking sequential circuits for the detection of single and multiple unidirectional stuck-at faults, as well as delay faults. It is shown how the monitoring machine approach provides a uniform error detection mechanism for the detection of these faults. Designs based on this method are shown to compare favourably, in terms of hardware overheads an... View full abstract»

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  • A systematic method to classify scan cells

    Publication Year: 1993, Page(s):219 - 224
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A scan cell (S-cell) is a basic storage unit for a scan-based sequential circuit. Depending on different requirements on the circuit under test, many design variations of S-cells exist. In this paper a systematic method to classify all practical S-cells is presented. Based on a novel graph representation and a set of design criteria, we find that all practical S-cells can be classified into 19 sch... View full abstract»

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  • Detection of multiple faults using SSFTS in CMOS logic circuits

    Publication Year: 1993, Page(s):274 - 279
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback ... View full abstract»

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  • Testing of parallel programs based on primitive dependence graph

    Publication Year: 1993, Page(s):126 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Because of the nondeterministic timing ordering behavior of parallel primitives, testing of parallel programs is more difficult than that of serial programs. In this paper, we present a new testing strategy for parallel programs---static testing of parallel programs with their primitive dependence graphs. We have developed methods to analyze the timing ordering dependences between primitives and t... View full abstract»

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  • Test set partitioning and dynamic fault dictionaries for sequential circuits

    Publication Year: 1993, Page(s):179 - 184
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    This paper describes techniques for partitioning test sets and maintaining diagnostic information in partition dictionaries that are appropriate for efficient dynamic fault location. The partitioned test sets and partition dictionary produce a small list of candidate faults, which are further distinguished by a dynamic fault dictionary, created at the time of diagnosis. The dictionaries used are s... View full abstract»

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  • Neural network realization of Markov model of TMR systems with compensating failures

    Publication Year: 1993, Page(s):44 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Reliability synthesis as a reverse of reliability analysis has the same importance as reliability estimation. One important issue in reliability synthesis is to find failure rates and repair rates of units, given the desired reliability requirement. Compensation of failures can be very significant for fail-fast TMR systems. This paper presents a new model of TMR systems in which fail-fast rates an... View full abstract»

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  • A C-testable DCVS GF(2m) multiplier

    Publication Year: 1993, Page(s):204 - 209
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2m ) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is 13m+1 for a GF(2 m) multiplier View full abstract»

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  • State encoding and functional decomposition for self-checking sequential circuit design

    Publication Year: 1993, Page(s):293 - 297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking r... View full abstract»

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  • Achieving minimal hardware multiple signature analysis for BIST

    Publication Year: 1993, Page(s):311 - 316
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper proposes a new method for achieving minimal hardware multiple intermediate signature analysis whereby n signatures are checked against a single reference. With a single reference, checking multiple signatures requires the same amount of hardware as for checking only one. However, checking multiple signatures has many advantages. In comparison to the method described by Y. Wie and A Ivah... View full abstract»

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  • Design and implementation of a JTAG boundary-scan interface controller

    Publication Year: 1993, Page(s):215 - 218
    Cited by:  Papers (1)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    In this paper we present an architecture for JTAG boundary-scan interface controller which we have implemented as a basic RISC microprocessor chip. We also present a JTAG test language which makes the interface between machine and users very friendly View full abstract»

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  • Parallel computation of LFSR signatures

    Publication Year: 1993, Page(s):75 - 80
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost a factor of n, where n is the number of proce... View full abstract»

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  • Limitations of built-in current sensors (BICS) for IDDQ testing

    Publication Year: 1993, Page(s):243 - 248
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Quiescent current (IDDQ) drawn by a static CMOS device is extremely small and is of the order of nanoamperes. Under many faults, (IDDQ) can increase by several orders of magnitude. Either an external or an on-chip current sensor can be used to detect enhanced static current drawn by a static CMOS device. An on-chip sensor, termed a BICS (Built-In Current Sensor) can be signif... View full abstract»

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  • Subjective fault evaluation method of electronic circuits

    Publication Year: 1993, Page(s):94 - 99
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    In this paper, fault evaluation problems, which are to determine whether electronic circuits are faulty or not, are discussed and a new fault evaluation method for electronic circuits, which is based on a fuzzy inference technique, is proposed. In our method, evaluation characteristics of an expert test engineer are defined by means of directed graphs. By using the graphs, fault evaluation results... View full abstract»

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  • FASSAD: Fault simulation with sensitivities and depth-first propagation

    Publication Year: 1993, Page(s):66 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) progra... View full abstract»

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  • On the testability of cascaded Reed Muller circuits

    Publication Year: 1993, Page(s):268 - 273
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    One of the advantages of using Reed Muller representations to design logic circuits is known as the high testability of the realized circuits. However, there is little known about the testability of any type of multi-level Reed Muller circuits. In this paper, we analyze the testability of a class of multi-level Reed Muller circuits which are generated by the synthesis tool FACTOR. FACTOR uses matr... View full abstract»

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  • Optimization of deterministic test sets using an estimation of product quality

    Publication Year: 1993, Page(s):119 - 124
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths View full abstract»

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  • T-BIST: A built-in self-test for analog circuits based on parameter translation

    Publication Year: 1993, Page(s):172 - 177
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    In this paper we propose a technique for verifying whether or not the tested parameters are within the acceptance range. This technique called T-BIST is based on the conversion of each detected parameter to a DC voltage. The resulting DC voltage is proportional to the measured parameter and can be easily manipulated and tested. The test of the DC voltage value consists in comparing it to two refer... View full abstract»

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  • Study of fault propagation using fault injection in the UNIX system

    Publication Year: 1993, Page(s):38 - 43
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper presents a fault propagation study for the UNIX operating system (Sun OS 4.1.2). Both hardware and software faults are injected in the UNIX kernel by using FINE - a fault injection and monitoring environment - to investigate the propagation of various types of faults. Based on the experimental results, fault propagation models are built and transient reward analysis is performed to eval... View full abstract»

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  • Optimal interconnect diagnosis

    Publication Year: 1993, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Interconnect diagnosis is an important problem in very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts among a given set of nets using the minimum number of tests. In this paper, we prove matching lower bounds for two non-adaptive diagnosis problems, and give an optimal algorithm for the adaptive... View full abstract»

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