Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

16-18 Nov. 1993

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  • Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

    Publication Year: 1993
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    Freely Available from IEEE
  • LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets

    Publication Year: 1993, Page(s):160 - 165
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Deterministic testing is by far the most interesting built-in self-test (BIST) technique because of the minimal number of test patterns required and of the known fault coverage. However, it is still not applicable since none of the existing deterministic test pattern generators (TPGs) is at the same time efficient and small. The LFSROM architecture which is presented herein is thus an attempt to s... View full abstract»

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  • Fault modelisation of external shorts in CMOS circuits

    Publication Year: 1993, Page(s):237 - 242
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    As the density of VLSI CMOS circuits increases, external shorts are expected to become a very important failure. This paper analyzes the electrical behavior of static CMOS gates with external shorts. The fault modelization of such shorts is then considered in the context of functional testing. It is demonstrated that the detectability of a short with respect to functional testing depends on the sh... View full abstract»

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  • FASSAD: Fault simulation with sensitivities and depth-first propagation

    Publication Year: 1993, Page(s):66 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) progra... View full abstract»

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  • A two-phase fault simulation scheme for sequential circuits

    Publication Year: 1993, Page(s):60 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A two-phase fault simulation scheme for sequential circuits is proposed. The scheme is done by first performing the true value simulation with several initial patterns and then by performing the fault simulation with the rest of patterns. With the fault simulation approach, some faults which consume much simulation time can be easily and quickly identified and dropped early. As a result, significa... View full abstract»

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  • Error localization in test outputs: A generalized analysis of signature compression

    Publication Year: 1993, Page(s):317 - 322
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Signature compression is widely used to reduce the volume of information generated by testing. Localization of the faulty component in the system under test, starting from the signature analysis, may be a complex problem related to identification of the erroneous bits in the sequence being compressed and to the error model of the system. A first technique for low-multiplicity errors is based on er... View full abstract»

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  • A distributed message routing algorithm for fault-tolerant hypercube systems

    Publication Year: 1993, Page(s):55 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A distributed message routing algorithm for faulty hypercube systems is described. To improve the efficiency, the algorithm adopts a heuristic backtracking strategy and each node provides an array to record its all neighbors faulty link information to avoid unnecessary searching for the known faulty links. Furthermore, the faulty link information is dynamically accumulated and the technique of heu... View full abstract»

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  • An approach to large program testing with tool WHEN

    Publication Year: 1993, Page(s):132 - 137
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The problem to test large application and system programs efficiently in supercomputer systems is discussed. Many difficulties exist when large programs are concerned. In order to overcome some of these difficulties, we design a novel software tool named WHEN, which has been used to solve some dynamic internal testing problems, such as flexible flowtracing, debugging of deep rooted errors or fault... View full abstract»

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  • Achieving minimal hardware multiple signature analysis for BIST

    Publication Year: 1993, Page(s):311 - 316
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper proposes a new method for achieving minimal hardware multiple intermediate signature analysis whereby n signatures are checked against a single reference. With a single reference, checking multiple signatures requires the same amount of hardware as for checking only one. However, checking multiple signatures has many advantages. In comparison to the method described by Y. Wie and A Ivah... View full abstract»

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  • Software upset analysis: A case study of the HS1602 microprocessor

    Publication Year: 1993, Page(s):49 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    This paper describes a simulation based approach to quantify the impact of low-level transient errors at the software execution level. Automated analysis, for the run-time injection of transients at the device level and the assessment of the resulting impact on the program-control flow, is described. Using test workloads, the type of upsets at the program-flow level which can result from fault inj... View full abstract»

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  • Detection of multiple faults using SSFTS in CMOS logic circuits

    Publication Year: 1993, Page(s):274 - 279
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback ... View full abstract»

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  • Testing of parallel programs based on primitive dependence graph

    Publication Year: 1993, Page(s):126 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Because of the nondeterministic timing ordering behavior of parallel primitives, testing of parallel programs is more difficult than that of serial programs. In this paper, we present a new testing strategy for parallel programs---static testing of parallel programs with their primitive dependence graphs. We have developed methods to analyze the timing ordering dependences between primitives and t... View full abstract»

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  • On properties and implementations of inverting ALSC for use in built-in self-testing

    Publication Year: 1993, Page(s):305 - 310
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Clockwise inverting sequences of original pseudo-random ones are considered effective for two-pattern testing of CMOS circuits. This paper describes a class of circuits which can generate such sequences and conveniently referred as inverting ALSC (autonomous linear sequential circuit). The simulation results show that inverting ALSC generated sequences have strong dependency on the original cyclic... View full abstract»

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  • Neural network realization of Markov model of TMR systems with compensating failures

    Publication Year: 1993, Page(s):44 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Reliability synthesis as a reverse of reliability analysis has the same importance as reliability estimation. One important issue in reliability synthesis is to find failure rates and repair rates of units, given the desired reliability requirement. Compensation of failures can be very significant for fail-fast TMR systems. This paper presents a new model of TMR systems in which fail-fast rates an... View full abstract»

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  • On the testability of cascaded Reed Muller circuits

    Publication Year: 1993, Page(s):268 - 273
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    One of the advantages of using Reed Muller representations to design logic circuits is known as the high testability of the realized circuits. However, there is little known about the testability of any type of multi-level Reed Muller circuits. In this paper, we analyze the testability of a class of multi-level Reed Muller circuits which are generated by the synthesis tool FACTOR. FACTOR uses matr... View full abstract»

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  • Optimization of deterministic test sets using an estimation of product quality

    Publication Year: 1993, Page(s):119 - 124
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths View full abstract»

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  • Computer aided testing system for LC cell's optical properties

    Publication Year: 1993, Page(s):330 - 332
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    This paper introduces our CAT system which is set up for testing the optical properties of LC (liquid crystal) cell. In this system, the transmission spectra of the LC cell at different voltages applied on LC film can be tested by computer control automatically. Simultaneously, the CIE1931 and CIE1971 chromaticity are calculated out in the program View full abstract»

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  • A new method for system diagnosis

    Publication Year: 1993, Page(s):147 - 152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    With the advent of parallel computing systems, the fault diagnosis of such systems becomes increasingly challenging and critical. In this paper, we first introduce the concept of binary decision diagram (BDD), based on which we present an efficient way to locate the faulty units according to what we call fault symptom (FS). The new technique is then proved to be optimal (shortest) in time-consumin... View full abstract»

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  • General design principles of self-testing code-disjoint PLAs

    Publication Year: 1993, Page(s):287 - 292
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper presents general principles of designing self-testing (ST) code-disjoint (CD) PLAs under fault model which covers three classes of typical PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for ST and CD is that the input code of a PLA is closed. The formal condition... View full abstract»

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  • Design of monitored self-checking sequential circuits for enhanced fault models

    Publication Year: 1993, Page(s):298 - 303
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper discusses the design of monitored self-checking sequential circuits for the detection of single and multiple unidirectional stuck-at faults, as well as delay faults. It is shown how the monitoring machine approach provides a uniform error detection mechanism for the detection of these faults. Designs based on this method are shown to compare favourably, in terms of hardware overheads an... View full abstract»

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  • Study of fault propagation using fault injection in the UNIX system

    Publication Year: 1993, Page(s):38 - 43
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper presents a fault propagation study for the UNIX operating system (Sun OS 4.1.2). Both hardware and software faults are injected in the UNIX kernel by using FINE - a fault injection and monitoring environment - to investigate the propagation of various types of faults. Based on the experimental results, fault propagation models are built and transient reward analysis is performed to eval... View full abstract»

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  • The driver/receiver conflict problem in interconnect testing with boundary-scan

    Publication Year: 1993, Page(s):210 - 214
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper explores the driver/receiver conflict problem in interconnect testing with bidirectional pins and 3-state output pins in boundary-scan. The objective is to have a higher-level (higher than chip) designer be aware of this conflict. Some existing algorithms are reviewed View full abstract»

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  • An algorithm for test generation of combinational circuits research and implementation for critical path tracing

    Publication Year: 1993, Page(s):26 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    An algorithm for test pattern generation of combinational logic circuits - critical path tracing is presented in this paper. Differing from other fault oriented test generation algorithms, this algorithm is circuit oriented and generates test pattern from primary outputs towards primary inputs in a circuit. In addition, it does not need fault simulation, i.e., when a test pattern is obtained all t... View full abstract»

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  • Optimal interconnect diagnosis

    Publication Year: 1993, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Interconnect diagnosis is an important problem in very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts among a given set of nets using the minimum number of tests. In this paper, we prove matching lower bounds for two non-adaptive diagnosis problems, and give an optimal algorithm for the adaptive... View full abstract»

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  • Testing scheduling and control in a parallel processing environment

    Publication Year: 1993, Page(s):262 - 267
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    In this paper, the testing scheduling problem based on circuit partitioning is formulated into index coloring of the parallel testing graph (PTG). It is known that the index coloring problem is exponential in time cost, but the testing scheduling problem is proved to be polynomially solvable in theory. According to this result, an optimal testing scheduling algorithm is offered in quadratic time. ... View full abstract»

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