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Proceedings of IEEE International Workshop on Memory Technology, Design, and Test

8-9 Aug. 1994

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  • Proceedings of IEEE International Workshop on Memory Technology, Design, and Test

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (113 KB)
    Freely Available from IEEE
  • The automatic generation of march tests

    Publication Year: 1994, Page(s):86 - 91
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Many memory tests have been designed in the past, one class of tests which has been proven to be very efficient in terms of fault coverage as well as test time, is the class of march tests. Designing march tests is a tedious, manual task. This paper presents a method which can, given a set of fault models, automatically generate the required march tests. It has been implemented in the programming ... View full abstract»

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  • GOS defects in SRAM: fault modeling and testing possibilities

    Publication Year: 1994, Page(s):66 - 71
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A detailed analysis of the behavior of CMOS SRAM memories with gate oxide short defects is presented. Simulation results are obtained using a previously developed circuit model of the defect experimentally validated. Depending on the transistor affected by a gate oxide short, different SRAM faulty behaviors, as coupling faults or dynamic faults, can occur. Merits of logic and current testing are c... View full abstract»

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  • Using sinusoidal stimuli and Fourier analyses for memory IC testing

    Publication Year: 1994, Page(s):92 - 97
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper explores the utilization of sinusoidal stimuli and Fourier analyses to test static RAM integrated circuits. Two different tests are investigated, a writing test with a sinusoidal stimulus on the DATA line and a reading test with a sinusoidal stimulus on an address line. Up to now, results show that numerous types of faults and defects can be detected and even identified. Sensitivity of ... View full abstract»

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  • A time saving testing scheme for mask ROM based on structure oriented failures

    Publication Year: 1994, Page(s):72 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    This paper proposes a time saving testing scheme for mask ROM. The scheme generates and applies test patterns based on a structure oriented failure mode to test ROM. An 8 mega-bit ROM is used as a vehicle to demonstrate this scheme and the results show that an increase of testing time speed can be achieved if the yield of the memory is low (<50%) View full abstract»

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  • Built-in random testing for dual-port RAMs

    Publication Year: 1994, Page(s):2 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, a random testing method for dual-port RAMs to detect double-coupling faults using a BIST scheme is discussed. A double-coupling fault is possibly caused by accessing two cells simultaneously, and is peculiar to dual-port RAMs. Our test method is based on the consideration of geometric locations in double accessing, and it aims at reducing the overhead of a BIST circuit View full abstract»

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  • Mega bit BiCMOS SRAM chip package modelling and performance analysis

    Publication Year: 1994, Page(s):10 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    In this paper, a closed-form expression for CMOS SRAM chip propagation delay is developed. This allows accurate calculation of the signal propagation delay of multilayer interconnects within the CMOS SRAM chip and also takes into account the delay of the CMOS SRAM cells driving the branched transmission line and the driving SRAM cell loading aspects of the interconnect line. Simulation results are... View full abstract»

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  • Automatic on-line memory tests in workstations

    Publication Year: 1994, Page(s):98 - 103
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    This paper presents a new approach called Stochastic Memory Allocation (SMA) to enhance the safety of workstations. It applies deterministic functional memory tests to the main memory of a workstation having parts of it selected stochastically in a sequential manner. The tests are carried our during normal work dynamically in parallel to other running processes. Important parameters are the amount... View full abstract»

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  • A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs

    Publication Year: 1994, Page(s):119 - 124
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper describes a transparent built-in self-test (BIST) scheme for random-access memories (RAMs) that detects single V-coupling faults. Such faults-as defined by Nair, Thatte, and Abraham (1978)-can be used to model many standard fault types such as stuck bits, transition faults, coupling faults, and pattern sensitivities. Variations of the proposed scheme can generate near-deterministic test... View full abstract»

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  • Mechanical stress induced void and hillock formations in thin films

    Publication Year: 1994, Page(s):22 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    In an effort to enhance our understanding of stress induced void formations in thin films voids were created in initially stress-free lead films at room temperature through a direct application of mechanical tensile stresses instead of a thermally-induced stress. Application of mechanical compressive stresses resulted in the formation of hillocks. In-situ observation inside an SEM indicates that t... View full abstract»

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  • On fault modeling and testing of content-addressable memories

    Publication Year: 1994, Page(s):78 - 83
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using t... View full abstract»

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  • Design of an active memory system for network applications

    Publication Year: 1994, Page(s):58 - 63
    Cited by:  Papers (3)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    We describe an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. A network or I/O ... View full abstract»

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  • Total dose radiation hardening and testing issues of GaAs static memories

    Publication Year: 1994, Page(s):135 - 140
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    A test chip in GaAs (E/D) technology has been designed and implemented in 1.2 μm MOSIS GaAs design rules. The unpackaged devices have been subjected to 1.5 keV Al-Kα X-rays and degradations in zero bias threshold voltage and device transconductance of n-channel E and D-MESFETs have been studied. A modified GaAs SRAM cell design, incorporating a circuits design to minimize degra... View full abstract»

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  • A self-diagnostic BIST memory design scheme

    Publication Year: 1994, Page(s):7 - 9
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper proposes a BIST structure for embedded RAMs. The structure has the self-diagnostic capability with only a minimal overhead. It degrades a little on the speed performance of the embedded RAM. Two sets of test patterns, MARCH and CHECKERBOARD, which detect most of the memory faults, are adopted in the scheme. This self-diagnosis capability makes this RAM BIST scheme able to be incorporate... View full abstract»

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  • BIST for ring-address SRAM-type FIFOs

    Publication Year: 1994, Page(s):112 - 118
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Testing FIFOs involves testing the embedded memory cell array, the addressing mechanisms, and the FIFO functionality logic (such as Empty and Full flags); each with their specific fault models. A test algorithm for the popular ring-address SRAM-type FIFOs has been published [Go94]; it consists of 36 steps and has a test length of 2n2+10n+12+2·Del (where n is the number of cells i... View full abstract»

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  • An on-chip test scheme for SRAMs

    Publication Year: 1994, Page(s):16 - 20
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Semiconductor technology continues to progress dramatically. With the increasing density, the testing of RAM chips has become progressively more difficult. In this paper, a new approach to simplify the testing of large SRAMs (static RAMs), embedded in VLSI chips or as stand-alone chips, by incorporating additional circuitry is proposed View full abstract»

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  • A fault-tolerant multiprocessor cache memory

    Publication Year: 1994, Page(s):52 - 57
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In multiprocessor systems, cache memories serve two purposes, namely the reduction of the average access time to the shared memory and the minimization of interconnection network requirements for each processor. However, in a cache, interference between operations from the processor and operations for data coherence degrades the cache performance. We propose a cache with only one single dual-port ... View full abstract»

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  • Memory process and test techniques for known good die

    Publication Year: 1994, Page(s):130 - 134
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper discusses four methods of die mount into temporary packages that allow full electrical parameter and temperature range testing to be performed. For evaluation of each method an IDT 71B74 8K x 8-bit cache TAG RAM is used. The four methods are: 1) tape automated bonding (TAB); 2) temporary wirebond into traditional IC packages; 3) temporary contact with micro-probe packages; and 4) solder... View full abstract»

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  • Transparent memory BIST

    Publication Year: 1994, Page(s):106 - 111
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper presents a new methodology for testing of bit-oriented and word-oriented RAMs based on circular test sequences, which can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches. The proposed approach is a transparent BIST technique combined with on-line error detection, which preserves the initial contents of the memory ... View full abstract»

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  • Fully-parallel multi-megabit integrated CAM/RAM design

    Publication Year: 1994, Page(s):46 - 51
    Cited by:  Papers (1)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Previous implementations of large-capacity Content Addressable Memories (CAMs) have employed advanced fabrication techniques or serialized operation. This paper describes a more generally applicable fully-parallel solution based on circuit and architectural innovation. A “pre-classified” CAM is integrated into the same array as its target RAM, and both use the same core cells. Architec... View full abstract»

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  • Radiation hardening of dynamic memories by the use of a new dummy cell concept

    Publication Year: 1994, Page(s):126 - 129
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The soft error rate (SER) of DRAMs with advanced structures can be reduced significantly by the use of a new dummy cell concept. Compared to conventional dummy cell concepts, this concept applies a fully sized dummy cell. By optimising the dummy cell precharge voltage and the timing for activation of the dummy word line, the overall SER of the chip is reduced by two orders of magnitude. This is be... View full abstract»

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  • A high speed embedded cache design with non-intrusive BIST

    Publication Year: 1994, Page(s):40 - 45
    Cited by:  Papers (11)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper describes a 155 MHz wide-word cache design and its test integration features. Design techniques for high speed CAM with single ended match line sensing and highly integrated RAM are described. A new cache BIST algorithm based on the SMARCH algorithm is presented. New techniques are described for the insertion of cache BIST access points into a high speed data path without compromising m... View full abstract»

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  • Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing

    Publication Year: 1994, Page(s):32 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A powerful failure analysis method for mega bit CMOS SRAM chip presented in this paper, is very useful in the CAD environment. The SRAM chip functional test allows the detection of permanent/intermittent faults which could cause the SRAM chip to function incorrectly. These faults are stuck-at-1 or stuck-at-0 based on physical failures like metallization shorts and capacitive coupling. Then, a lase... View full abstract»

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  • Electrical failure analysis in high density DRAMs

    Publication Year: 1994, Page(s):26 - 31
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    As density and complexity increase, the search for new test and analysis techniques can impact the role of failure analysis especially in the correct identification of failure mechanisms for root cause fixes to ensure timely introduction of a new product in a relatively competitive market. Design for Testability (DFT) offers some flexibility in trying to meet the demands made on the production tes... View full abstract»

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