Application-Specific Array Processors, 1993. Proceedings., International Conference on

25-27 Oct. 1993

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  • Proceedings of International Conference on Application Specific Array Processors (ASAP '93)

    Publication Year: 1993
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    Freely Available from IEEE
  • The Xor embedding: An embedding of hypercubes onto rings and toruses

    Publication Year: 1993, Page(s):15 - 28
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (761 KB)

    Many parallel algorithms use hypercubes as the communication topology among processes, which make them suitable to be executed on a hypercube multicomputer. In this way the communication cost is kept to a minimum since processes can be allocated to processors in such a way that only communication between neighbor processors is required. However, the scalability of hypercube multicomputer is constr... View full abstract»

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  • A wavefront array processor for on the fly processing of digital video streams

    Publication Year: 1993, Page(s):101 - 108
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (462 KB)

    The authors present a wavefront array processor architecture developed at ETCA and dedicated to real-time processing of digital video streams. The core of the architecture is a mesh-connected three-dimensional network of 1024 custom processing elements. Each processing element can perform up to 50 millions 8- or 16-bit operations per second, working with a 25 MHz clock frequency. Thus algorithms a... View full abstract»

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  • A real-time systolic algorithm for on-the-fly hidden surface removal

    Publication Year: 1993, Page(s):238 - 249
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (543 KB)

    Hidden surface removal for real-time realistic display of complex scenes requires intensive computation and justifies usage of parallelism to provide the needed response time. The authors present a systolic algorithm that identifies visible segments on a scanline with the "real-time" characteristic: visible segments are output on-the-fly as soon as segments are input to the systolic array. The pro... View full abstract»

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  • A CAD tool for electromagnetic simulation on the associative string processor

    Publication Year: 1993, Page(s):583 - 592
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    The associative string processor (ASP) is a scalable fine grained SIMD architecture, optimized for image processing tasks. In this paper the authors describe a new application for this available architecture. The finite different time domain (FDTD) method is a technique used to solve electromagnetic boundary value problems. The technique produces results in the time domain which can then be post-p... View full abstract»

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  • Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture

    Publication Year: 1993, Page(s):192 - 195
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (196 KB)

    Mathematical models are frequently used to evaluate the physical properties of matter; they involve intensive computation: processing times and loan costs soar, using general purpose computers. Remarkable improvements are promised by special purpose architectures, in particular for the parallel execution of the most time consuming routines; the Monte Carlo-Metropolis method has been examined, and ... View full abstract»

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  • A 1D linearly expandable interconnection network performance analysis

    Publication Year: 1993, Page(s):572 - 582
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB)

    The authors describe the design and evaluation of a linear interconnection network for the image processing parallel architecture GFLOPS. This is a SIMD/MIMD architecture which can treat a wide range of application from low level to high level. The different memory banks of this structure are connected to the processors through a one stage interconnection network. This network is linearly expandab... View full abstract»

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  • An array-processor based architecture for classification problems

    Publication Year: 1993, Page(s):148 - 151
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (204 KB)

    The authors describe the design and implementation of an application-specific digital architecture aimed at the solution in real time of the “K nearest neighbors” algorithm for classification problems, whose computational weight is very high. The system described here is an array-processor architecture in which the data base is split among several units that at the same time apply the ... View full abstract»

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  • I/O data management on SIMD systolic arrays

    Publication Year: 1993, Page(s):273 - 284
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    A mechanism for overlapped I/O management operations and computations on a SIMD linear systolic arrays is presented. This mechanism is based on two synchronized controllers allowing a speedup factor of two over SIMD machines without overlapped facility. Optimal code generation is achieved using the ReLaCS environment, specifically designed for the architectural features of overlapped SIMD systolic... View full abstract»

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  • Parallel processing architectures for rank order and stack filters

    Publication Year: 1993, Page(s):65 - 76
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (536 KB)

    To achieve additional speedup in rank order and stack filter architectures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential when the architecture reaches the throughput limits caused by the underlying technology. ... View full abstract»

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  • Systolic normalization of rational numbers

    Publication Year: 1993, Page(s):502 - 513
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    The authors present a systolic algorithm for normalization of rational numbers which is scalable to arbitrary length operands, and they discuss the possibility of implementing it within a rational arithmetic coprocessor for the use of computer algebra systems. A preliminary estimation shows that the performance for 32 bit operands is comparable to that of a fast RISC processor, but for long operan... View full abstract»

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  • Resource constrained scheduling of uniform algorithm

    Publication Year: 1993, Page(s):29 - 40
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain nonconvex index domains, (3) effecient branc... View full abstract»

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  • Time-optimal visibility-related algorithms on meshes with multiple broadcasting

    Publication Year: 1993, Page(s):226 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (568 KB)

    The compaction step of integrated circuit design motivates the study of various visibility problems among vertical segments in the plane. One popular variant is referred to as the Vertical Segment Visibility problem (VSV, for short) and is stated as follows. Given a collection S of n disjoint vertical line segments in the plane, for every endpoint of a segment in S determine the first line segment... View full abstract»

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  • M3: A high performance signal processor for RADAR applications

    Publication Year: 1993, Page(s):164 - 167
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (164 KB)

    Real time radar computing requires high processing performances and fast and efficient I/O capabilities. These goals have been achieved by means of a new multiprocessor architecture based on the Motorola DSP 96002. This system was developed entirely in the FIAR laboratories, and now is a state-of-the-art unit in their avionic radar family. The authors describe a computer system developed specifica... View full abstract»

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  • Systolic design of a new finite field division/inverse algorithm

    Publication Year: 1993, Page(s):188 - 191
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (172 KB)

    A systolic architecture of a newly developed algorithm for performing division and inversion over GF(2m) has been successfully realized. It is novel in that the normal inverse/multiplication steps are integrated and the generator polynomial is selectable. The new design with its inherent regularity offers an expandable, fully pipelined high performance circuit, that is very suitable to ... View full abstract»

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  • Efficient architecture of a programmable block matching processor

    Publication Year: 1993, Page(s):560 - 571
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (560 KB)

    An efficient VLSI architecture of a programmable block matching processor for the emulation of a wide spectrum of full search and reduced complexity search block matching algorithms is presented. Optimized efficiency is obtained by using a quadratic systolic array architecture with global accumulation, combined with a programmable meander-like data flow. Flexibility is further increased by cascada... View full abstract»

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  • Response-pipelined CAM chips - Building blocks for large associated arrays

    Publication Year: 1993, Page(s):144 - 147
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (256 KB)

    The authors introduce the architecture of a new type of fully parallel content addressable memory chips that serve as building blocks for large associated arrays. These new chips can be easily cascaded to increase the logical word size or the number of words and yet allow the search rate to be maintained constant irrespective of the logical word size or word count. Prototype CMOS implementations o... View full abstract»

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  • A period-processor-time-minimal schedule for cubical mesh algorithms

    Publication Year: 1993, Page(s):261 - 272
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (548 KB)

    The paper, using a direct acyclic graph (dag) model of algorithms, investigates precedence constrained multiprocessor schedules for the n × n × n directed mesh. This cubical mesh is fundamental, representing the standard algorithm for square matrix product, as well as many other algorithms. Its completion requires at least 3n - 2 multiprocessor steps. Time-minimal multiprocessor schedu... View full abstract»

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  • Scheduling partitioned algorithms on processor arrays with limited communication supports

    Publication Year: 1993, Page(s):53 - 64
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    It is important that array designs, especially the scheduling of partitioned arrays, must cope with various kinds of communication constraints such as interconnection topology, channel bandwidth, and inhomogeneous communication delay. The interprocessor communication requirements can be dictated by the dependence vectors and size of the partitioned tiles. A folded constraint graph is created to de... View full abstract»

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  • Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross Benchmark

    Publication Year: 1993, Page(s):172 - 175
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (220 KB)

    Handling a continuous flow of variable size images is a requirement for real time computer vision machines. A modular system based on a small size SIMD cellular array of 1-bit processing elements has been developed with this goal in mind and it is now evaluated against the Abingdon Cross Benchmark specifications. The benchmark tests the combination of algorithms and architecture and generates a qu... View full abstract»

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  • A novel architecture for a decision-feedback equalizer using extended signal-digit feedback

    Publication Year: 1993, Page(s):490 - 501
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A novel bit-level systolic array architecture for implementing a bit parallel decision-feedback equalizer (DFE) is presented. Core of the architecture is an array multiplier using redundant arithmetic in combination with bit-level feedback. The use of signal-digit (SD) circuitry allows one to feed back each digit as soon as it is available. So the recursive computation can be executed with the mos... View full abstract»

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  • Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis

    Publication Year: 1993, Page(s):428 - 441
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (636 KB)

    A method is presented for mapping conditional affine resources equations (CAREs) into systolic-type architectures. The tasks of localization and of space-time reindexing are formulated as a single branch and broad search problem. The combined formulation allows these problems to be solved concurrently and thus ensures that true optimal solutions are derived. The employed space-time reindexing meth... View full abstract»

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  • Implementation of large neural associative memories by massively parallel array processors

    Publication Year: 1993, Page(s):357 - 368
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (548 KB)

    The authors discuss the use of massively parallel array processors for simulating large neural associative memories. Although based on standard matrix operations the simulation of neural associative memories requires special parallel algorithms because a sparse coding of the input and output information is needed. Four different implementations with different mapping strategies and different array... View full abstract»

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  • Volume rendering by wavefront architecture

    Publication Year: 1993, Page(s):214 - 225
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    To achieve real time processing for volume rendering, it is necessary to employ parallel processing techniques. Therefore, a ray casting wavefront architecture is proposed. The architecture offers the following advantages. By a special memory organization, the processor array can perform fast rotation along x, y, z axes without incurring costly memory transformation. The projection phase and post-... View full abstract»

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  • Mapping arbitrary projections for volume rendering onto an array processor

    Publication Year: 1993, Page(s):160 - 163
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (228 KB)

    The authors propose a new mapping technique for volume rendering on massively parallel computer. Previous mappings of volume rendering algorithms onto array processors either required large amounts of interprocessor communication or lacked the generality needed to deal with arbitrary rotations and perspective projections. The mapping developed here is based on an enhanced ray-tracking algorithm. I... View full abstract»

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