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Application-Specific Array Processors, 1993. Proceedings., International Conference on

25-27 Oct. 1993

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Displaying Results 1 - 25 of 63
  • Proceedings of International Conference on Application Specific Array Processors (ASAP '93)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (146 KB)
    Freely Available from IEEE
  • A simple expert system for the reasoning of systolic designs

    Publication Year: 1993, Page(s):128 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    The author presents a simple expert system developed for the reasoning of systolic designs. It is based on the STA formalism, the spatial inductive techniques developed earlier, and a temporal induction technique (briefly introduced in this paper) to perform formal verification of systolic array designs. Induction techniques exploit the regularity and locality attributes of systolic arrays. The sy... View full abstract»

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  • Systolic evaluation of functions: Digit-level algorithm and realization

    Publication Year: 1993, Page(s):514 - 525
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The author presents a novel algorithm for the evaluation of functions. The algorithm is systolic and may be realized as a fully scalable and very regular design consisting of merely full-adders and registers. The algorithm evaluates a polynomial according to the Horner scheme, i.e., it performs a cascade of multiply-and-add operations. Data are represented as two's complement fixed-point numbers t... View full abstract»

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  • Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross Benchmark

    Publication Year: 1993, Page(s):172 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Handling a continuous flow of variable size images is a requirement for real time computer vision machines. A modular system based on a small size SIMD cellular array of 1-bit processing elements has been developed with this goal in mind and it is now evaluated against the Abingdon Cross Benchmark specifications. The benchmark tests the combination of algorithms and architecture and generates a qu... View full abstract»

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  • On synthesizing application-specific array architectures from behavioral specifications

    Publication Year: 1993, Page(s):124 - 127
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The authors describe a design framework, Architect, being developed for synthesizing application-specific array architectures from behavioral specifications to Register-Transfer (RT) descriptions , which can be identified as a number of cooperating tasks; signal transformations, hardware mapping expressed as, in general, nonlinear mapping and scheduling function with hardware constraints, memory m... View full abstract»

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  • Systolic normalization of rational numbers

    Publication Year: 1993, Page(s):502 - 513
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The authors present a systolic algorithm for normalization of rational numbers which is scalable to arbitrary length operands, and they discuss the possibility of implementing it within a rational arithmetic coprocessor for the use of computer algebra systems. A preliminary estimation shows that the performance for 32 bit operands is comparable to that of a fast RISC processor, but for long operan... View full abstract»

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  • COLUMNUS - An SIMD architecture for pattern recognition and simulations of statistical physics

    Publication Year: 1993, Page(s):168 - 171
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Many interesting problems including simulations of statistical physics, pattern recognition and neural networks can be treated efficiently by performing calculations in parallel on a large number of discrete, often even binary variables. As general-purpose computers are not well adapted to these problems, the authors have developed an SIMD array of bit-sequential processors providing an extended s... View full abstract»

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  • A CAD tool for electromagnetic simulation on the associative string processor

    Publication Year: 1993, Page(s):583 - 592
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The associative string processor (ASP) is a scalable fine grained SIMD architecture, optimized for image processing tasks. In this paper the authors describe a new application for this available architecture. The finite different time domain (FDTD) method is a technique used to solve electromagnetic boundary value problems. The technique produces results in the time domain which can then be post-p... View full abstract»

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  • Subband filtering: Cordic modulation and systolic quadrature mirror filter tree

    Publication Year: 1993, Page(s):109 - 123
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The decomposition (analysis) of a finite-energy signal into a relatively small number of mutually independent signals which allows reconstruction (synthesis) of the original signal is called subband filtering. Subbands can be processed in parallel or recursively. In the latter case, one obtains a so-called quadrature mirror filter tree. The former case leads to cosine-modulated filter banks. The a... View full abstract»

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  • Communication-minimal mapping of uniform loop nests onto distributed memory architectures

    Publication Year: 1993, Page(s):1 - 14
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    The authors deal with mapping techniques for uniform loop nests. Target machines are SPMD distributed memory parallel computers. They use affine-by-variable mapping to synthesize a virtual grid architecture from the original loop nest. The key to the mapping strategy is the communication graph, which enables us to derive optimal mappings, i.e., where the number of communications is proved to be mi... View full abstract»

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  • A novel architecture for a decision-feedback equalizer using extended signal-digit feedback

    Publication Year: 1993, Page(s):490 - 501
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A novel bit-level systolic array architecture for implementing a bit parallel decision-feedback equalizer (DFE) is presented. Core of the architecture is an array multiplier using redundant arithmetic in combination with bit-level feedback. The use of signal-digit (SD) circuitry allows one to feed back each digit as soon as it is available. So the recursive computation can be executed with the mos... View full abstract»

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  • Volume rendering by wavefront architecture

    Publication Year: 1993, Page(s):214 - 225
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    To achieve real time processing for volume rendering, it is necessary to employ parallel processing techniques. Therefore, a ray casting wavefront architecture is proposed. The architecture offers the following advantages. By a special memory organization, the processor array can perform fast rotation along x, y, z axes without incurring costly memory transformation. The projection phase and post-... View full abstract»

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  • M3: A high performance signal processor for RADAR applications

    Publication Year: 1993, Page(s):164 - 167
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    Real time radar computing requires high processing performances and fast and efficient I/O capabilities. These goals have been achieved by means of a new multiprocessor architecture based on the Motorola DSP 96002. This system was developed entirely in the FIAR laboratories, and now is a state-of-the-art unit in their avionic radar family. The authors describe a computer system developed specifica... View full abstract»

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  • A 1D linearly expandable interconnection network performance analysis

    Publication Year: 1993, Page(s):572 - 582
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    The authors describe the design and evaluation of a linear interconnection network for the image processing parallel architecture GFLOPS. This is a SIMD/MIMD architecture which can treat a wide range of application from low level to high level. The different memory banks of this structure are connected to the processors through a one stage interconnection network. This network is linearly expandab... View full abstract»

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  • Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture

    Publication Year: 1993, Page(s):192 - 195
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Mathematical models are frequently used to evaluate the physical properties of matter; they involve intensive computation: processing times and loan costs soar, using general purpose computers. Remarkable improvements are promised by special purpose architectures, in particular for the parallel execution of the most time consuming routines; the Monte Carlo-Metropolis method has been examined, and ... View full abstract»

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  • A wavefront array processor for on the fly processing of digital video streams

    Publication Year: 1993, Page(s):101 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    The authors present a wavefront array processor architecture developed at ETCA and dedicated to real-time processing of digital video streams. The core of the architecture is a mesh-connected three-dimensional network of 1024 custom processing elements. Each processing element can perform up to 50 millions 8- or 16-bit operations per second, working with a 25 MHz clock frequency. Thus algorithms a... View full abstract»

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  • I/O data management on SIMD systolic arrays

    Publication Year: 1993, Page(s):273 - 284
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A mechanism for overlapped I/O management operations and computations on a SIMD linear systolic arrays is presented. This mechanism is based on two synchronized controllers allowing a speedup factor of two over SIMD machines without overlapped facility. Optimal code generation is achieved using the ReLaCS environment, specifically designed for the architectural features of overlapped SIMD systolic... View full abstract»

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  • Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator

    Publication Year: 1993, Page(s):152 - 155
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    The phasecorrelation algorithm - as a method for motion estimation - is a key component of todays TV and tomorrows HDTV-systems. One advantage of hardware realization of this algorithm for efficient real time processing - in opposite to blockmatching - is the possibility to process multiple pixels per system clock cycle. A suitable partition using three different VLSI-circuits to perform the phase... View full abstract»

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  • Reduced area multipliers

    Publication Year: 1993, Page(s):478 - 489
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    As developed by Wallace (1964) and Dadda (1965), a high-speed method for the parallel multiplication of two binary numbers is to reduce their partial products to two numbers whose sum is equal to the product. The resulting two numbers are then summed using a fast carry-propagate adder. The authors present a multiplier, the reduced area multiplier, with a novel reduction scheme which results in few... View full abstract»

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  • VLSI array synthesis for polynomial GCD computation

    Publication Year: 1993, Page(s):536 - 547
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Polynomial GCD (greatest common divisor) finding is an important problem in algebraic computation, especially in decoding error correcting codes. The authors show a new systolic array structure for the polynomial GCD problem using a systematic array synthesis technique. The VLSI implementation of the array structure is area-efficient and achieves maximum throughput with pipelining. The dependency ... View full abstract»

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  • A highly-parallel match architecture for AI production systems using application-specific associative matching processors

    Publication Year: 1993, Page(s):180 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Here, a highly-parallel two-layer match architecture using specific associative matching processors (AMPs) is proposed to speed up the execution time of match process of AI production systems. Each AMP comprises a 2D array of content-addressable memories, called CAM blocks. The architecture first compiles the left-hand (LHS) of each production into a symbolic form, and then assigns a number of con... View full abstract»

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  • Resource constrained scheduling of uniform algorithm

    Publication Year: 1993, Page(s):29 - 40
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain nonconvex index domains, (3) effecient branc... View full abstract»

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  • Low-power polygon renderer for computer graphics

    Publication Year: 1993, Page(s):200 - 213
    Cited by:  Papers (3)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Polygon rasterization is the most computational and memory intense stage in rendering synthesized computer images. The authors present a low-power, real-time hardware implementation for this task. Rasterization of two-dimensional Gouraud-shaded polygons at 90,000 polygons/sec is achievable with computational power consumption of about 12 mW at 1.5 V operation, using an array configuration of 16 re... View full abstract»

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  • A new formulation of the mapping conditions for the synthesis of linear systolic arrays

    Publication Year: 1993, Page(s):297 - 308
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The authors present a new formulation for mapping algorithms into linear systolic arrays. The closed-form necessary and sufficient mapping conditions are derived to identify mappings without computation conflicts and data link collisions. These mapping conditions are easy to check because their constituent variables are the space-time mapping matrix and the problem size parameters. The design of o... View full abstract»

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  • Mapping arbitrary projections for volume rendering onto an array processor

    Publication Year: 1993, Page(s):160 - 163
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    The authors propose a new mapping technique for volume rendering on massively parallel computer. Previous mappings of volume rendering algorithms onto array processors either required large amounts of interprocessor communication or lacked the generality needed to deal with arbitrary rotations and perspective projections. The mapping developed here is based on an enhanced ray-tracking algorithm. I... View full abstract»

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