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Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors

17-19 Sept. 1990

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Displaying Results 1 - 25 of 107
  • Approximate time-domain models of three-dimensional interconnects

    Publication Year: 1990, Page(s):201 - 205
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB)

    The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances (where n is the number of conductors), an equ... View full abstract»

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  • Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels

    Publication Year: 1990
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (54 KB)

    Summary form only given. The real-time application of trellis coding to partial response channels is described for a rate 8/10 matched-spectral-null (MSN) trellis code on the (1-D) partial response channel. The architectural and design issues of an experimental chip that implements the functions of encoding, decoding, and Viterbi detection are discussed. Two novel techniques in the design of the V... View full abstract»

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  • Proceedings. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.90CH2909-0)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (273 KB)
    Freely Available from IEEE
  • Fault grading of large digital systems

    Publication Year: 1990, Page(s):290 - 293
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Cost-effective and accurate fault simulation of very large digital designs on engineering workstations is proposed. The hierarchical approach reduces memory requirements drastically by storing the structure of common repeated subcircuits only once. The approach allows flexible multilevel simulation. The simulation algorithms are at the switch-level so that general MOS digital designs with bidirect... View full abstract»

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  • Wavefront array processor for video applications

    Publication Year: 1990, Page(s):307 - 310
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A single-chip MIMD wavefront array processor for video applications is presented. The processor topology is an array of individually programmable mesh-connected cells; processors may be cascaded indefinitely in one or two dimensions. 12-b word width, superscalar RISC cell architecture, and the 125-MHz clock rate are tailored toward the requirement of digital video signal processing. The processor ... View full abstract»

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  • High speed VLSI logic simulation using bitwise operations and parallel processing

    Publication Year: 1990, Page(s):171 - 174
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A novel gate-level high-speed VLSI logic simulation technique with assignable delay is presented that uses bitwise logic operations together with the segmented waveform relaxation method (SWRM). The implementation of the technique on parallel computers is described. Although the proposed technique is similar to the compiled-code method, it does not generate a compiled-code and can handle different... View full abstract»

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  • An efficient parallel algorithm for channel routing

    Publication Year: 1990, Page(s):400 - 403
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The channel-routing of a set of multiterminal nets in the standard two-layer model is considered. The sequential algorithms based on the greedy strategy do not seem to be easily parallelizable. Proposed is an efficient parallel algorithm for routing channels with cyclic constraints. The algorithm runs in time O(n2/p+log2p), with p ... View full abstract»

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  • Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams

    Publication Year: 1990, Page(s):286 - 290
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A Boolean technology mapping with permissible functions is presented. This technique makes use of complementary intermediate logic functions of circuits. Therefore, complementary outputs of ECL gates can be easily handled. High-quality synthesized ECL circuits and CMOS circuits free of logical redundancies are generated. Technology-independent networks are converted into technology-dependent virtu... View full abstract»

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  • Reliable design of multichip nonblocking crossbars

    Publication Year: 1990, Page(s):70 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A major problem in the design of VLSI crossbar networks is the simultaneous-switching noise (also known as Delta-I noise), caused by the simultaneous activation of a large number of line-drivers at the output leads of the VLSI package. In a nonblocking configuration, one can reduce the maximum number of active line-drivers in a chip by using extra columns of chips. Tight upper and lower bounds are... View full abstract»

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  • Rule-based testability rule check program

    Publication Year: 1990, Page(s):95 - 98
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A practical rule-based testability rule checker for VLSI testing adopting a tunable rule-base shell suited for rule checking is described. The checking process is divided into symbolic simulation and violation detection. The testability rules applied in the violation detection and the circuit primitive operation rules applied in the symbolic simulator are treated as rule bases. Circuit primitives ... View full abstract»

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  • Exploitation of operation-level parallelism in a processor of the CRAY X-MP

    Publication Year: 1990, Page(s):20 - 23
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Available operation-level parallelism and its exploitation in the CRAY X-MP processor are studied. Considered are the sizes and contributions to execution time of basic blocks, instruction and operation issue rates and issue stalls, and operation execution overlap for entire executions of three large programs, FLO52, TRFD, and QCD1, taken from the Perfect Club benchmark set. The large basic blocks... View full abstract»

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  • Optimized bit level architectures for IIR filtering

    Publication Year: 1990, Page(s):302 - 306
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modifie... View full abstract»

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  • 68040 integer module

    Publication Year: 1990, Page(s):183 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The central CPU for the 68040 processor is the integer unit (IU). The IU contains multiple 32-bit data and address paths with heavily pipelined instruction execution control for improved performance. Frequently used instructions and addressing modes have been optimized for single cycle execution. Additionally, independent control for each pipe state yields increased throughput. Implementation of c... View full abstract»

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  • Test generation in circuits constructed by input decomposition

    Publication Year: 1990, Page(s):107 - 111
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Beca... View full abstract»

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  • HAL III: function level hardware logic simulation

    Publication Year: 1990, Page(s):167 - 170
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-l... View full abstract»

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  • Multiterminal-net routing by grid stretching

    Publication Year: 1990, Page(s):396 - 399
    Cited by:  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Let R be a rectangle uniformly partitioned by w-1 vertical line segments and h-1 horizontal line segments. The problem of routing through the rectangle, called the RRP problem (also referred to as the switch-box routing problem), is considered. It is denoted by I=(R, N), and consists of finding a layout under the knock-knee wiring model for the... View full abstract»

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  • SYLON-REDUCE: an MOS network optimization algorithms using permissible functions

    Publication Year: 1990, Page(s):282 - 285
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    An algorithm, SYLON-REDUCE, that uses the concept of permissible functions to optimize an MOS network directly is presented. SYLON-REDUCE uses a more coherent, algorithmic approach, adapting the MOS cell synthesis procedure of algorithm DIMN, to resynthesize the cells in the network. Better networks can be obtained for most functions. It is shown that technology-specific synthesis and optimization... View full abstract»

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  • Complexity issues in RAM-DFE design for magnetic disk drives

    Publication Year: 1990, Page(s):215 - 219
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Design of a high-speed adaptive decision feedback equalizer (DFE) for detection of magnetic disk data is described. A RAM is used in the feedback path instead of the usual transversal filter, and the equalizer is referred to as the RAM-DFE. The RAM compensates for trailing nonlinear intersymbol interference in the disk data. The structure and operation of the RAM-DFE is described, and it is shown ... View full abstract»

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  • Reliability analysis of a computer system for a data collection application

    Publication Year: 1990, Page(s):66 - 69
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Reliability analysis of a computer system for a data collection application is described. The system is built around a central minicomputer platform that serves as a database manager and transaction processor. The components of the platform include the processor, memory, I/O cards, power supply, and the disks and disk controller. Users have workstations that are connected to the central processor ... View full abstract»

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  • QRAM-Quick access memory system

    Publication Year: 1990, Page(s):417 - 420
    Cited by:  Papers (3)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A quick access memory (QRAM) was developed that realizes a cost-effective high-performance memory architecture. The QRAM improves the effective data access speed by making maximum use of the page mode of memory, and hence acts like a pseudo-cache memory. For high performance and usability, it has three special features: built-in address latches/comparators, a direct handshake facility, and a multi... View full abstract»

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  • Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer

    Publication Year: 1990, Page(s):86 - 89
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    The VLSI design of a one-chip vector processor (VP) for parallel digital signal processing (DSP) systems is described. The VP aims at a peak performance of 100 MFLOPS (32-b) for typical digital signal processing applications. To achieve this performance based on existing CMOS technology, a very-long-instruction-word-type pipeline architecture was used. The pipeline processing architecture and the ... View full abstract»

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  • Compacting randomly generated test sets

    Publication Year: 1990, Page(s):153 - 156
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A technique using genetic algorithms is presented for the generation of compact test sets for combinational VLSI circuits. The technique combines a previously proven method for random test pattern generation with adaptive searching capabilities to produce high-quality test sets. A series of experiments demonstrated that the technique performed consistently better than the traditional method. On av... View full abstract»

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  • Empirical evaluation of randomly-wire multistage networks

    Publication Year: 1990, Page(s):380 - 385
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Experimental data are presented indicating that multistage interconnection networks with randomly positioned wires are likely to be substantially better for message routing applications than traditional multistage networks, such as the butterfly. The data are presented for a variety of routing models, including store-and-forward routing, cut-through routing, and circuit switching, as well as for s... View full abstract»

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  • On the estimation of logic complexity for design automation applications

    Publication Year: 1990, Page(s):368 - 371
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Many logic design automation procedures would benefit from a priori knowledge of complexity of the resulting realization. There are no universally accepted notions of space/time complexity criteria, as such measures are greatly influenced by the target topologies and technology. Even though an accurate measure of logic complexity is extremely difficult to compute, it is possible to obtain rough es... View full abstract»

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  • 2.5 Gbits/sec telecommunications gate array

    Publication Year: 1990, Page(s):259 - 262
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Describes a gate array designed specifically for fiber-optic telecom or datacom mux/demux applications at up to 2.5 Gb/s. The device is fabricated in GaAs technology and uses standard ECL power forms and I/O levels. This gate array can convert a 2.5-Gb/s serial data stream to or from a 16-bit-wide parallel data at 155 Mb/s. Process technology, chip architecture, circuit design, and performance are... View full abstract»

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