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Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Date 17-19 Sept. 1990

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  • Proceedings. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.90CH2909-0)

    Publication Year: 1990
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    Freely Available from IEEE
  • Design and application trade-offs between high-density and high-speed ASICs

    Publication Year: 1990 , Page(s): 269 - 272
    Cited by:  Patents (1)
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    Two CMOS application-specific integrated circuit (ASIC) families are presented. The first ASIC family with 1.0 μm channel length, is based on a sea-of-cells (SOC) architecture and a double-level-metal (DLM) structure. It offers chip density up to 100 K wirable circuits and higher I/O pin count using plastic-flat-pack (PFP) packaging. The second ASIC family with 0.5 μm channel length offers up to 75 K wirable gates with boundary scan I/Os and array built-in self-test (ABIST). Single-chip-module (SCM), and multiple-chip-module (MCM) pin-in-hole packages are used to save space at the card level. Specific features are described, focusing on the complementarity offering of these two families and on the design tradeoffs between high-density and high-speed ASIC applications View full abstract»

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  • Towards a VLSI packaging design support environment (PDSE); concepts and implementation

    Publication Year: 1990 , Page(s): 443 - 448
    Cited by:  Papers (1)  |  Patents (4)
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    A software shell for assisting in VLSI package design is discussed. Called packaging design support environment (PDSE), the shell integrates tools for modeling and simulation of electrical characteristics of VLSI packages. Parameter extractors tools calculate inductance and capacitance for multiconductor, multidielectric, two-dimensional structures with loss dielectrics. The simulation tools compute pulse response characteristics of uniform, multiple, coupled, and lossless transmission lines. The PDSE shell provides facilities for supporting the package design cycle. Such support facilities include an interface to couple PDSE with a CAD design database, model and simulation experiment libraries, simulation management procedures that guide evaluation of alternative design models, and data analysis support tools. Expert systems techniques are being incorporated into PDSE. View full abstract»

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  • An efficient parallel algorithm for channel routing

    Publication Year: 1990 , Page(s): 400 - 403
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    The channel-routing of a set of multiterminal nets in the standard two-layer model is considered. The sequential algorithms based on the greedy strategy do not seem to be easily parallelizable. Proposed is an efficient parallel algorithm for routing channels with cyclic constraints. The algorithm runs in time O(n2/p+log2p), with p processors, on a shared memory parallel random access machine (PRAM) model where 1⩽pn2√ and n is the size of the input. An efficient adaptation of this algorithm on a Sequent Balance 21000 multiprocessor system is reported View full abstract»

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  • Reliability analysis of a computer system for a data collection application

    Publication Year: 1990 , Page(s): 66 - 69
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    Reliability analysis of a computer system for a data collection application is described. The system is built around a central minicomputer platform that serves as a database manager and transaction processor. The components of the platform include the processor, memory, I/O cards, power supply, and the disks and disk controller. Users have workstations that are connected to the central processor through a local area network (LAN). The central processor also has connections to different test and data collection points located in a wide area network (WAN). The analysis identified the disk subsystems as a potential reliability bottleneck, in the system. Disk mirroring was identified as a potential reliability improvement View full abstract»

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  • The complexity of adaptive annealing

    Publication Year: 1990 , Page(s): 404 - 407
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    The number of decrements necessary if the changes in the equilibrium density are bounded is derived for a simulated annealing problem. This gives an expression for the CPU-time of the process when all chains have the same length. This expression can also be used for tuning the annealing schedule for a given total CPU-time, while keeping the disturbance of the equilibrium as small as possible. The expression is also valid for generic annealing processes that use a constant factor to obtain the next value of t (the commonly used schedule) View full abstract»

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  • DEBBIE: a configurable user interface for CAD frameworks

    Publication Year: 1990 , Page(s): 135 - 140
    Cited by:  Papers (1)  |  Patents (4)
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    The requirements for CAD framework user interfaces and the implementation of the DEBBIE user interface system in the HILDA CAD framework environment are discussed. By using DEBBIE designers are allowed to work on a conceptual level, free from data/tool management, to do creative design work. Many design tasks are automated to speed up the design processes. With a configurable user interface, designers can make the system look/act the way they want it to instead of trying to learn what the system forces on them. By allowing them easy integration and activation of tools, designers can pick and choose the best design tools available without worrying about compatibility of different tools. With standard tool interface programs, designers also spend much less time learning to use new tools. An overview of DEBBIE and general requirements of user interface for CAD frameworks are presented View full abstract»

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  • A linear time algorithm for optimal CMOS functional cell layouts

    Publication Year: 1990 , Page(s): 449 - 453
    Cited by:  Papers (2)
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    To obtain a minimum width cell layout of a static CMOS circuit in the Uehara-vanCleemput (1981) style the circuit is often modeled as a pair of dual series-parallel multigraphs. The problem then reduces to finding a minimal number of edge-disjoint dual paths that cover the pair of graphs. Presented is an O(l) time heuristic algorithm for this problem, where l is the number of literals in an input prefix logic expression. It utilises the decomposition tree structure of the dual multigraphs. The algorithm produces optimal solutions to all the examples available in the literature. The algorithm is able to process very complicated logic expressions and almost always produces cell layouts of minimum width in less than a second View full abstract»

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  • Test generation in circuits constructed by input decomposition

    Publication Year: 1990 , Page(s): 107 - 111
    Cited by:  Papers (3)
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    The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using a single stuck-type fault model View full abstract»

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  • Estimating aliasing in CA and LFSR based signature registers

    Publication Year: 1990 , Page(s): 157 - 160
    Cited by:  Papers (3)
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    Aliasing estimations for cellular automata (CA) and linear feedback shift registers (LFSR) data compactors are presented. As data compaction is a heavily relied on technique for built-in self-test (BIST) the results should be of practical, as well as theoretical interest. Aliasing estimation techniques for multiple-input data compactors are considered. In particular, exact and approximate computation techniques are developed and discussed for CA and LFSR registers. Aliasing estimates for CA and LFSR structures are provided for the ISCAS-85 benchmark circuits for single stuck-at and single delay faults View full abstract»

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  • Derivation of signal flow direction in MOS VLSI: an alternative

    Publication Year: 1990 , Page(s): 206 - 209
    Cited by:  Papers (2)
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    Novel rules to derive the signal flow in a VLSI-design are presented. This method is based on design-style independent logical principles, which makes it suitable for circuits that have not been checked on their electrical correctness. The use of two global principles has an important influence for more complicated designs, but also results in an efficiency penalty which may be kept reasonable by introducing graph reduction rules and heuristics. The different steps in the tagging process are explained and illustrated with examples. The dataflow rules are integrated in the overall DIALOG system to perform electrical verification, and they offer an invaluable help to break up the verification problem in subproblems and to cope with feedback in designs, by introducing the concept of intended unilateral blocks View full abstract»

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  • A floating point unit for the 68040

    Publication Year: 1990 , Page(s): 187 - 190
    Cited by:  Papers (1)  |  Patents (1)
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    The Motorola 68040 floating point unit (FPU) combines three independent state machines, two data paths, and over 100000 transistors to achieve 8-Mflops peak performance and over 3-Mflops Linpack double-precision performance at the introductory speed of 25 MHz. It is optimized for minimum latency and maximum pipelined performance on frequently used double-precision floating point instructions. The FPU is architecturally divided into three piped stages, the conversion unit (CU), the execution unit (XU), and the normalization unit (NU). The control logic is tested using scan to achieve very high ATPG fault coverage while the data paths are tested using functional patterns View full abstract»

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  • A 75 MHz CMOS digital convolver

    Publication Year: 1990 , Page(s): 311 - 314
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    A dynamic logic digital convolver utilizing a 1-μm commercial CMOS process has been developed. The convolver is a linear systolic array with a time-bandwidth product of 1024 and a processing gain of nearly 30 dB. It features a single-phase clock with dynamic D flip-flops as the basic storage elements. The device, in a four-chip set, acts as a matched filter which is intended to compare a noise-like signal against a reference signal. The input buffers incorporate ESD protection diodes and convert TTL to CMOS levels. The output buffers use transistors sized to drive 20-pF loads with CMOS levels (TTL-compatible) signals with rise and fall times of less than 1 ns. Design and performance of the convolver are determined View full abstract»

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  • Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine

    Publication Year: 1990 , Page(s): 391 - 395
    Cited by:  Papers (6)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    Tabula Rasa is a user reconfigurable hardware system under development in AT&T Bell Labs. Its purpose is to assist in the development of new hardware systems, and possibly to serve as a computing engine in its own right. The core of the system is a full-custom CMOS chip. This chip has electrically programmed logic and routing, and allows an external monitor to observe, control, and reconfigure the circuit during operation. Unlike currently available programmable logic devices this chip is targeted specifically at the development rather than the production environment. One or more of these chips could be wired into the development version of an application system, to add flexibility and simplify the design process by making the design more controllable and observable. In another type of application, an array of these chips could be assembled into a dedicated processor attached to a workstation. The architecture of the chip, some of the tradeoffs involved, and the CAD challenges needed to support it are outlined View full abstract»

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  • Simultaneous bidirectional signalling for IC systems

    Publication Year: 1990 , Page(s): 430 - 433
    Cited by:  Papers (16)  |  Patents (11)
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    A design and implementation of an input/output (I/O) circuit capable of simultaneous bidirectional transmission in CMOS integrated circuits are presented. Conventional techniques for improving communication bandwidth between VLSI chips use the tri-state bidirectional drivers and/or add more I/O pins to a given chip. The design of simultaneous bidirectional transmission of signals between two chips results in optimal performance while maintaining the same pin count. The circuitry has a low output-voltage swing and occupies relatively small silicon area, so that both high speed and low power dissipation are achieved. Included also is the design of a current driver that can properly terminate a given transmission line without the use of any off-chip termination resistors. The design remains functional under significant process variation. Simulation results show that the I/O circuit can be clocked with a frequency over 50 MHz under the worst-case condition for a typical 2-μm CMOS process. This implies a bandwidth of more than 100 Mb/s per I/O pin View full abstract»

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  • On-the-fly circuit to measure the average working set size

    Publication Year: 1990 , Page(s): 471 - 474
    Cited by:  Papers (1)  |  Patents (1)
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    Two economic methods (Markov chain method and filtering method) which estimate the average working set size of a program on the fly are presented. Both methods are simple enough to be implemented inside a VLSI processor chip with small space requirements, or outside the chip to probe the memory reference traffic. The on-the-fly circuit tools that can estimate the average working set size of a program without much loss of accuracy make unnecessary the problematic and expensive procedures (hardware monitoring or simulation) of collecting the reference traces. Such tools can be used in all studies that require program locality measurements, including the study of a program locality, the effectiveness study of locality improvement techniques, and the study of optimizing compiler's effect on program locality. Since both methods require only one comparison and an increment of one or two counters per memory reference, they can be easily implemented as circuits to probe the reference traffic between the processor and the main memory View full abstract»

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  • An analog parallel distributed solution to the shortest path problem

    Publication Year: 1990 , Page(s): 130 - 134
    Cited by:  Papers (2)
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    The evolution of analog VLSI has led to increased application of analog circuitry in solving problems previously solved digitally or numerically. Specifically, analog parallel distributed (APD) methods have been used. These methods are applicable to problems that can be modeled using the mathematical functions characteristic of analog circuits. One such problem is the single-source shortest path problem (SPP). An SPP algorithm that is derived by applying an APD approach to solving Bellman's equation is proposed. Correctness of the algorithm is proved for the case of zero-initial conditions. Simulations of the system (algorithm) yield correct results in all cases. A decomposition technique is developed to analyze the dynamic behavior of the algorithm in detail. The complexity, accuracy, and settling time of a physical implementation of the system are also discussed View full abstract»

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  • New ideas on symbolic manipulations of finite state machines

    Publication Year: 1990 , Page(s): 224 - 227
    Cited by:  Papers (16)
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    Formal verification of finite state machines (FSM) using symbolic manipulations is addressed. It is shown that the use of symbolic manipulations algorithms for the traversal of a FSM can be sublinear in the number of state and input patterns for some classes of machines. A symbolic manipulation algorithm can be directly used as a method for the transformation of a FSM which preserves the observable behavior. It is also shown that a backward traversal of a FSM can also be performed using symbolic techniques View full abstract»

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  • ASIC design using the high-level synthesis system CALLAS: a case study

    Publication Year: 1990 , Page(s): 141 - 146
    Cited by:  Papers (4)  |  Patents (1)
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    The Siemens high-level synthesis system CALLAS was used to synthesize an ASIC for moving-object detection consisting of 3400 equivalent gates. The digital signal processing (DSP) problem was formulated on algorithmic level in the hardware description language DSDL as a three-page algorithm. Only a few days were needed from specification to the chip layout. Design steps included were high-level behavior simulation, library mapping, and standard cell layout generation using a state-of-the-art physical design system. The authors give a brief overview of the CALLAS system, introduce the DSP example, and discuss the synthesis process and the simulations performed View full abstract»

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  • Application specific microprocessor [NS3200/EP family]

    Publication Year: 1990 , Page(s): 351 - 354
    Cited by:  Papers (8)  |  Patents (7)
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    An alternative approach for embedded system processor architecture is presented. Methods to evaluate and define the modules within such a processor are discussed. Three examples of new embedded system processors from the National Semiconductors 32000/EP family are described. These are: the integrated system processor NS32CG160 developed for laser beam printer applications; the embedded system processor NS32GX320 for laser/FAX applications; and the imaging signal processor NS532FX16 designed for Group 3 FAX machines. Integration of system components and improved internal organization should deliver better solutions for the embedded application designer View full abstract»

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  • Automatic generation of control circuits in pipelined DSP architectures

    Publication Year: 1990 , Page(s): 324 - 327
    Cited by:  Papers (4)
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    Novel algorithms for synthesis of control circuits in pipelined signal processing architectures are presented. The algorithms generate appropriate latching and switching of intermediate signals for a functionally correct operation. Sufficient theory of pipelining is developed to ensure iteration independence of the registers used in control circuits of the dedicated architectures. The interprocessor control circuits are being incorporated into CAD systems for dedicated designs. Algorithms for automatic generation of all control circuits for a specified sequencing and scheduling of operations, for single and multiple clock, and for single and multiple implementation styles are presented View full abstract»

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  • A hierarchical floorplanning approach

    Publication Year: 1990 , Page(s): 332 - 338
    Cited by:  Papers (7)  |  Patents (1)
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    A hierarchical floorplanner for general cell layout that exploits accurate shape functions that describe constraints on the leaf cells in order to produce good floorplans is presented. The leaf cells may have highly constrained shapes, or more flexible shapes. The floorplanner trades off the locations, sizes shapes, and pin positions of the cell against each other in order to minimize the layout area and the amount of interconnections. To the extent that the shape functions are accurate, there is no need for design iterations. By imposing a hierarchy in the form of a multiwave cluster tree, the number of floorplanning options is restricted and the problem is simplified by allowing the floorplanner to operate on one hierarchical cell at a time. The shape functions and the hierarchical approach make it possible to directly compute locations, sizes, shapes, and pin positions for the leaf cells View full abstract»

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  • Built-in self-test with weighted random pattern hardware

    Publication Year: 1990 , Page(s): 161 - 166
    Cited by:  Papers (24)
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    The authors address scan-based built-in self-test (BIST) of digital circuits that are highly resistant to testing with uniform random patterns. Introducing a procedure, the precompute test patterns for random-pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in the number of distributions (hardware memory) and the length of the total test time. The hardware implementation is based on a canonic weighting circuit that interfaces to a circulating memory and a pseudo-random source View full abstract»

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  • Placement algorithms for CMOS cell synthesis

    Publication Year: 1990 , Page(s): 454 - 458
    Cited by:  Papers (4)  |  Patents (1)
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    Heuristic placement algorithms for the layout synthesis of CMOS logic cells are described. The techniques are not restricted to fully complimentary CMOS, and focus on a novel strategy for FET pair ordering which takes advantage of splitting wide FETs to eliminate diffusion gaps. These algorithms are applicable to strip-based layout synthesis from transistor netlists. Existing CMOS cell synthesis systems neither fully include the costs nor utilize the benefits of FET splitting. The system described does this, in some cases results in an area saving. In general, it trades diffusion gaps for useful FETs. Since some technologies penalize diffusion gaps heavily, and others, such as sea-of-gates, forbid them altogether, such a tradeoff seems increasingly appropriate View full abstract»

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  • Optimized bit level architectures for IIR filtering

    Publication Year: 1990 , Page(s): 302 - 306
    Cited by:  Papers (7)
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    Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) one every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation View full abstract»

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