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Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Date 17-19 Sept. 1990

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Displaying Results 1 - 25 of 107
  • Approximate time-domain models of three-dimensional interconnects

    Publication Year: 1990, Page(s):201 - 205
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB)

    The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances (where n is the number of conductors), an equ... View full abstract»

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  • Proceedings. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.90CH2909-0)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (273 KB)
    Freely Available from IEEE
  • Heuristic minimization of Boolean relations using testing techniques

    Publication Year: 1990, Page(s):277 - 281
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Minimization of Boolean relations is important from the point of view of synthesis, especially in synthesis for testability. A very fast heuristic procedure for finding an optimal sum-of-products representation for a Boolean relation is described. Starting with a function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a ... View full abstract»

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  • A design environment for high performance VLSI signal processing

    Publication Year: 1990, Page(s):147 - 152
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    An environment for the full-custom design of high-sample-rate digital signal processing (DSP) VLSI circuits is described. An overall design methodology that allows for tradeoffs between algorithms, architecture, and layout is presented. Key CAD tools used in this methodology include architecture mapping, generators, symbolic layout, clock network analysis, and timing simulation. These tools allow ... View full abstract»

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  • Testability driven synthesis of interacting finite state machines

    Publication Year: 1990, Page(s):273 - 276
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Sequential testability aspects in the decomposition of finite state machines (FSMs) are addressed. It is shown that the sequential testability of an FSM can be enhanced more easily when the machine is recognized to be, or is synthesized as, an interconnection of smaller machines. An exhaustive classification of redundant faults that can occur in a single FSM embedded in an interacting sequential c... View full abstract»

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  • ASIC design using the high-level synthesis system CALLAS: a case study

    Publication Year: 1990, Page(s):141 - 146
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The Siemens high-level synthesis system CALLAS was used to synthesize an ASIC for moving-object detection consisting of 3400 equivalent gates. The digital signal processing (DSP) problem was formulated on algorithmic level in the hardware description language DSDL as a three-page algorithm. Only a few days were needed from specification to the chip layout. Design steps included were high-level beh... View full abstract»

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  • Pin assignment for improved performance in standard cell design

    Publication Year: 1990, Page(s):339 - 342
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Chip performance optimization is a crucial task in the modern design process. A method to improve the longest delay in a circuit built for standard cells is discussed. The method used to improve the designs is attractive because it does not require an increase in active area. All the improvements are achieved by a careful pin assignment. An efficient pin assignment algorithm is proposed. It has be... View full abstract»

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  • A pipelined microprocessor for logic programming languages

    Publication Year: 1990, Page(s):355 - 359
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS... View full abstract»

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  • Fast parallel communication on mesh connected machines with low buffer requirements

    Publication Year: 1990, Page(s):78 - 81
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Even though exact algorithms exist for permutation routing of n2 on a n×n mesh of processors which require constant size queues, the constants are very large, and the algorithms very complicated to implement. A novel, simple heuristic is presented for this problem. The main contribution of the parallel algorithm is that it uses constant and very small qu... View full abstract»

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  • Design and application trade-offs between high-density and high-speed ASICs

    Publication Year: 1990, Page(s):269 - 272
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Two CMOS application-specific integrated circuit (ASIC) families are presented. The first ASIC family with 1.0 μm channel length, is based on a sea-of-cells (SOC) architecture and a double-level-metal (DLM) structure. It offers chip density up to 100 K wirable circuits and higher I/O pin count using plastic-flat-pack (PFP) packaging. The second ASIC family with 0.5 μm channel length offers u... View full abstract»

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  • On-the-fly circuit to measure the average working set size

    Publication Year: 1990, Page(s):471 - 474
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Two economic methods (Markov chain method and filtering method) which estimate the average working set size of a program on the fly are presented. Both methods are simple enough to be implemented inside a VLSI processor chip with small space requirements, or outside the chip to probe the memory reference traffic. The on-the-fly circuit tools that can estimate the average working set size of a prog... View full abstract»

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  • DEBBIE: a configurable user interface for CAD frameworks

    Publication Year: 1990, Page(s):135 - 140
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The requirements for CAD framework user interfaces and the implementation of the DEBBIE user interface system in the HILDA CAD framework environment are discussed. By using DEBBIE designers are allowed to work on a conceptual level, free from data/tool management, to do creative design work. Many design tasks are automated to speed up the design processes. With a configurable user interface, desig... View full abstract»

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  • A hierarchical floorplanning approach

    Publication Year: 1990, Page(s):332 - 338
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A hierarchical floorplanner for general cell layout that exploits accurate shape functions that describe constraints on the leaf cells in order to produce good floorplans is presented. The leaf cells may have highly constrained shapes, or more flexible shapes. The floorplanner trades off the locations, sizes shapes, and pin positions of the cell against each other in order to minimize the layout a... View full abstract»

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  • Empirical evaluation of randomly-wire multistage networks

    Publication Year: 1990, Page(s):380 - 385
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Experimental data are presented indicating that multistage interconnection networks with randomly positioned wires are likely to be substantially better for message routing applications than traditional multistage networks, such as the butterfly. The data are presented for a variety of routing models, including store-and-forward routing, cut-through routing, and circuit switching, as well as for s... View full abstract»

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  • Application specific microprocessor [NS3200/EP family]

    Publication Year: 1990, Page(s):351 - 354
    Cited by:  Papers (7)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    An alternative approach for embedded system processor architecture is presented. Methods to evaluate and define the modules within such a processor are discussed. Three examples of new embedded system processors from the National Semiconductors 32000/EP family are described. These are: the integrated system processor NS32CG160 developed for laser beam printer applications; the embedded system proc... View full abstract»

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  • New ideas on symbolic manipulations of finite state machines

    Publication Year: 1990, Page(s):224 - 227
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Formal verification of finite state machines (FSM) using symbolic manipulations is addressed. It is shown that the use of symbolic manipulations algorithms for the traversal of a FSM can be sublinear in the number of state and input patterns for some classes of machines. A symbolic manipulation algorithm can be directly used as a method for the transformation of a FSM which preserves the observabl... View full abstract»

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  • Task assignment by parallel simulated annealing

    Publication Year: 1990, Page(s):74 - 77
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Simulated annealing for obtaining approximate solutions to combinatorial optimization problems is addressed. The serial algorithm, however, can require extensive computation time. Most parallel algorithms for simulated annealing are problem-specific and/or violate the serial decision sequence, thereby allowing errors not present in the serial algorithm. Maintaining the serial sequence is necessary... View full abstract»

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  • Test architecture of the Motorola 68040

    Publication Year: 1990, Page(s):191 - 194
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The 68040 is a third generation 32-bit microprocessor that implements the 68000 family instruction set. The philosophy for the design for test (DFT) effort on the 68040 is to address each class of logic in a different manner. In it there is the typical breakdown of data paths, ROM/PLA structures, embedded RAMs, random logic (sequential and nonsequential), and finite state machines. In each of thes... View full abstract»

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  • An approach to 150 K gate low power ECL cell based integrated circuits

    Publication Year: 1990, Page(s):263 - 268
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A technology and a design system for implementing VLSI ECL circuits with 50 to 150 K gates is described. The technology provides high-density ECL logic and BiCMOS RAMs, while the design system avoids many of the hand checks previously required for successful ECL designs. System design considerations, standard cell based design methodology, design verification, and process technology are outlined View full abstract»

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  • Design of a custom processing unit based on Intel i486 architectures and performances trade-offs

    Publication Year: 1990, Page(s):467 - 470
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The architecture of a customized processing unit using an Intel i486 microprocessor as an efficient general-purpose processor is described. The objectives for the optimization of the i486 performances are: the design of a set of customized support chips to control the processor bus, the memory management, the arbitrations, the interrupts, and the I/O data transfer; the use of 80-ns DRAM (dynamic r... View full abstract»

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  • Design of robustly testable static CMOS parity trees derived from binary decision diagrams

    Publication Year: 1990, Page(s):103 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have... View full abstract»

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  • Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels

    Publication Year: 1990
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    Summary form only given. The real-time application of trellis coding to partial response channels is described for a rate 8/10 matched-spectral-null (MSN) trellis code on the (1-D) partial response channel. The architectural and design issues of an experimental chip that implements the functions of encoding, decoding, and Viterbi detection are discussed. Two novel techniques in the design of the V... View full abstract»

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  • Figures of merit for system path time estimation

    Publication Year: 1990, Page(s):49 - 55
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A model to help in the evaluation of various technologies for large systems is presented. The space modeled is considered to be made up of a number of VLSI chips sufficient to comprise a CPU and cache arranged on a single planar package. The inputs consist of technology constraints and system design parameters. From these, a number of design characteristics are computed based on formulas derived f... View full abstract»

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  • An analog parallel distributed solution to the shortest path problem

    Publication Year: 1990, Page(s):130 - 134
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The evolution of analog VLSI has led to increased application of analog circuitry in solving problems previously solved digitally or numerically. Specifically, analog parallel distributed (APD) methods have been used. These methods are applicable to problems that can be modeled using the mathematical functions characteristic of analog circuits. One such problem is the single-source shortest path p... View full abstract»

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  • Combined hardware selection and pipelining in high performance data-path design

    Publication Year: 1990, Page(s):328 - 331
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Pipelining and hardware selection are important optimization tasks in the design of high-performance data paths. At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal required clock frequency. An algorithm which optimally selects hardware blocks from a library for implementing these abstrac... View full abstract»

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