Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors

17-19 Sept. 1990

Filter Results

Displaying Results 1 - 25 of 107
  • Approximate time-domain models of three-dimensional interconnects

    Publication Year: 1990, Page(s):201 - 205
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB)

    The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances (where n is the number of conductors), an equ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels

    Publication Year: 1990
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (54 KB)

    Summary form only given. The real-time application of trellis coding to partial response channels is described for a rate 8/10 matched-spectral-null (MSN) trellis code on the (1-D) partial response channel. The architectural and design issues of an experimental chip that implements the functions of encoding, decoding, and Viterbi detection are discussed. Two novel techniques in the design of the V... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Proceedings. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.90CH2909-0)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (273 KB)
    Freely Available from IEEE
  • The complexity of adaptive annealing

    Publication Year: 1990, Page(s):404 - 407
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The number of decrements necessary if the changes in the equilibrium density are bounded is derived for a simulated annealing problem. This gives an expression for the CPU-time of the process when all chains have the same length. This expression can also be used for tuning the annealing schedule for a given total CPU-time, while keeping the disturbance of the equilibrium as small as possible. The ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Heuristic minimization of Boolean relations using testing techniques

    Publication Year: 1990, Page(s):277 - 281
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Minimization of Boolean relations is important from the point of view of synthesis, especially in synthesis for testability. A very fast heuristic procedure for finding an optimal sum-of-products representation for a Boolean relation is described. Starting with a function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast parallel communication on mesh connected machines with low buffer requirements

    Publication Year: 1990, Page(s):78 - 81
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Even though exact algorithms exist for permutation routing of n2 on a n×n mesh of processors which require constant size queues, the constants are very large, and the algorithms very complicated to implement. A novel, simple heuristic is presented for this problem. The main contribution of the parallel algorithm is that it uses constant and very small qu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 68040 memory modules and bus controller

    Publication Year: 1990, Page(s):179 - 182
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The 68040 processor includes an instruction memory system, a data memory system, and a synchronous bus. These resources are controlled by three autonomous machines, the instruction memory controller (IMEMC), the data memory controller (DMEMC), and the bus controller (BC). The structure of the data paths, the main caches, the address-translation caches, and the controllers are presented, including ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient parallel algorithm for channel routing

    Publication Year: 1990, Page(s):400 - 403
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The channel-routing of a set of multiterminal nets in the standard two-layer model is considered. The sequential algorithms based on the greedy strategy do not seem to be easily parallelizable. Proposed is an efficient parallel algorithm for routing channels with cyclic constraints. The algorithm runs in time O(n2/p+log2p), with p ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo pin assignment for single-layer over-the-cell routing

    Publication Year: 1990, Page(s):343 - 346
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    In a CMOS double metal gate-array technology, only the M2 layer is available for over-the-cell routing. A systematic algorithms that intelligently converts global wires into pseudo-pins and assigns them to each row of cells is presented. The final positions of pseudo-pins provide a feasible solution for one-layer routine over the cells and minimize wire densities in the adjacent two-layer routing ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testability driven synthesis of interacting finite state machines

    Publication Year: 1990, Page(s):273 - 276
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Sequential testability aspects in the decomposition of finite state machines (FSMs) are addressed. It is shown that the sequential testability of an FSM can be enhanced more easily when the machine is recognized to be, or is synthesized as, an interconnection of smaller machines. An exhaustive classification of redundant faults that can occur in a single FSM embedded in an interacting sequential c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation in circuits constructed by input decomposition

    Publication Year: 1990, Page(s):107 - 111
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Beca... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Task assignment by parallel simulated annealing

    Publication Year: 1990, Page(s):74 - 77
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Simulated annealing for obtaining approximate solutions to combinatorial optimization problems is addressed. The serial algorithm, however, can require extensive computation time. Most parallel algorithms for simulated annealing are problem-specific and/or violate the serial decision sequence, thereby allowing errors not present in the serial algorithm. Maintaining the serial sequence is necessary... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Complexity issues in RAM-DFE design for magnetic disk drives

    Publication Year: 1990, Page(s):215 - 219
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Design of a high-speed adaptive decision feedback equalizer (DFE) for detection of magnetic disk data is described. A RAM is used in the feedback path instead of the usual transversal filter, and the equalizer is referred to as the RAM-DFE. The RAM compensates for trailing nonlinear intersymbol interference in the disk data. The structure and operation of the RAM-DFE is described, and it is shown ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design aids and test results for laser-programmable logic arrays

    Publication Year: 1990, Page(s):386 - 390
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The time required to customized a logic array circuit can be reduced to minutes by the use of laser programming without the access and resistance limitations of electrically programmable devices. A restructable logic array (RLA) that can be completely tested before packaging and can be fabricated in a standard CMOS process has been developed. Its key element is a connective laser link device. Circ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic classification of node types in switch-level descriptions

    Publication Year: 1990, Page(s):175 - 178
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and cannot affect the circuit operation, whereas a node is classified as a memory node if the memory of the node is maintained and can affect the circuit operation. Accurate classification ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiterminal-net routing by grid stretching

    Publication Year: 1990, Page(s):396 - 399
    Cited by:  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Let R be a rectangle uniformly partitioned by w-1 vertical line segments and h-1 horizontal line segments. The problem of routing through the rectangle, called the RRP problem (also referred to as the switch-box routing problem), is considered. It is denoted by I=(R, N), and consists of finding a layout under the knock-knee wiring model for the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pin assignment for improved performance in standard cell design

    Publication Year: 1990, Page(s):339 - 342
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Chip performance optimization is a crucial task in the modern design process. A method to improve the longest delay in a circuit built for standard cells is discussed. The method used to improve the designs is attractive because it does not require an increase in active area. All the improvements are achieved by a careful pin assignment. An efficient pin assignment algorithm is proposed. It has be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in self-test with weighted random pattern hardware

    Publication Year: 1990, Page(s):161 - 166
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The authors address scan-based built-in self-test (BIST) of digital circuits that are highly resistant to testing with uniform random patterns. Introducing a procedure, the precompute test patterns for random-pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards a VLSI packaging design support environment (PDSE); concepts and implementation

    Publication Year: 1990, Page(s):443 - 448
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    A software shell for assisting in VLSI package design is discussed. Called packaging design support environment (PDSE), the shell integrates tools for modeling and simulation of electrical characteristics of VLSI packages. Parameter extractors tools calculate inductance and capacitance for multiconductor, multidielectric, two-dimensional structures with loss dielectrics. The simulation tools compu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A file-based adaptive prefetch caching design

    Publication Year: 1990, Page(s):463 - 466
    Cited by:  Papers (2)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Prefetching techniques in disk caching are addressed. An adaptive prefetch design based on a run-time caching statistics of files is presented. Cache hit histories produced by prefetching are used as a measure of the file access sequentialities. Detailed cache design analysis is discussed using simulation results of a trace-driven model with traces collected from a personal system. The curves obta... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal semantics of UDL/I and its applications to CAD/DA tools

    Publication Year: 1990, Page(s):90 - 94
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    UDL/I is a hardware design language for ASIC design developed in a Japanese LSI design language standardization project. A formal semantics of UDL/I is presented. There is no established way to define semantics of hardware design languages, because there is no general computation model for them. A definition method of formal semantics for UDL/I and semantics suitable for a standard language are de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and application trade-offs between high-density and high-speed ASICs

    Publication Year: 1990, Page(s):269 - 272
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Two CMOS application-specific integrated circuit (ASIC) families are presented. The first ASIC family with 1.0 μm channel length, is based on a sea-of-cells (SOC) architecture and a double-level-metal (DLM) structure. It offers chip density up to 100 K wirable circuits and higher I/O pin count using plastic-flat-pack (PFP) packaging. The second ASIC family with 0.5 μm channel length offers u... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of robustly testable static CMOS parity trees derived from binary decision diagrams

    Publication Year: 1990, Page(s):103 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliable design of multichip nonblocking crossbars

    Publication Year: 1990, Page(s):70 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A major problem in the design of VLSI crossbar networks is the simultaneous-switching noise (also known as Delta-I noise), caused by the simultaneous activation of a large number of line-drivers at the output leads of the VLSI package. In a nonblocking configuration, one can reduce the maximum number of active line-drivers in a chip by using extra columns of chips. Tight upper and lower bounds are... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A global feedback detection algorithm for VLSI circuits

    Publication Year: 1990, Page(s):37 - 40
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    A global feedback detection algorithm for VLSI circuits is presented. It can identify all the global feedback loops within reasonable computational time. The overall algorithm is as follows: First, all the strongly connected components (SCC) are found using a modified version of the Tarjan algorithm which can handle circuits with flip-flops and latches. Second, each SCC recursively cuts the loops ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.