May 29 1990-June 1 1990

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Displaying Results 1 - 25 of 90
  • EURO ASIC '90 (Cat. No.90TH0316-0)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (455 KB)
    Freely Available from IEEE
  • A new algorithm for diagnosis-oriented automatic test pattern generation

    Publication Year: 1990, Page(s):332 - 336
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Production testing does not only aim at detecting faulty devices, but its goals are often to repair the element or to investigate the cause of failure, so as to tune the manufacturing process. Diagnostic testing is thus becoming the object of attention both in industry and academia, thanks also to the increased power of tools like fault simulators, testability analysers, and ATPGs. Diagnostic test... View full abstract»

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  • Hierarchical test generation for data path

    Publication Year: 1990, Page(s):326 - 331
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A method of hierarchical test generation for data path is proposed. The test patterns are generated for the basic blocks of a classical data path library. These test patterns are propagated to the inputs and to the outputs of the data path by two methods. The first one, practically implemented, enumerates backpropagation paths based on structural considerations, selects one and then performs consi... View full abstract»

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  • Built-in self-test for generated blocks in an ASIC environment

    Publication Year: 1990, Page(s):320 - 325
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Techniques for Built-in Self-Test of RAMs embedded within ASIC's are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be... View full abstract»

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  • A routing concept for large sea-of-gates designs

    Publication Year: 1990, Page(s):225 - 229
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Sea-of-gates (SoG) is becoming a very important design style for ASICs. Due to a larger flexibility in placement and routing, SoG can achieve higher densities and gate count than conventional gate arrays. Ion this paper the authors describe a routing environment and a routing methodology utilizing all features of this new design style, aiming to automatically complete a large design with high gate... View full abstract»

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  • Real time graphics processor

    Publication Year: 1990, Page(s):314 - 316
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    A real-time fully programmable graphics processor, previously implemented with several custom and semi-custom ASICs, has been shrunk into a single 1 μm CMOS chip called Monochip Graphic Processor (MGP). Development of previous chip set started in 1979 to mid 1986, therefore different technologies and methodologies were used throughout the designs. Main challenge was to cope with almost 10 year ... View full abstract»

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  • A design-system for ASIC's with macrocells

    Publication Year: 1990, Page(s):220 - 224
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors report on a design system for the physical layout of ASIC's with macrocells, which has been developed during the last three years in the framework of a research contact with IBM Germany and used successfully in practice. The main idea is to apply a hierarchical placement procedure together with global routing and timing analysis. This technique enables one to guarantee at each step of ... View full abstract»

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  • Application of digital CMOS ASICs in a medical diagnostic imaging design

    Publication Year: 1990, Page(s):310 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A new line of medical diagnostic imaging instruments was designed using application-specific integration as a key technology. An outstanding price-performance ratio can be achieved using a system integration approach. Development- and production-costs are discussed, given the case of a low volume/high complexity product View full abstract»

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  • Global routing driven floorplanning

    Publication Year: 1990, Page(s):214 - 219
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A novel global routing driven floorplanning approach is presented. Rectangular cells such as in macrocell design are considered. The major contributions of the paper are: (1) a new model for the prediction of shape functions which enables one to consider a more general class of floorplan representations. (2) An improved two-dimensional partitioning procedure. (3) A dynamic updating scheme that con... View full abstract»

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  • A parallel processor ASIC for real time pattern recognition

    Publication Year: 1990, Page(s):306 - 309
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A real time pattern processing ASIC is described. By exploiting a 1 u, 3.3 V DLM CMOS technology, a 10 MHz 250 k transistor chip was designed for machine vision applications requiring recognition of objects in real time. The architecture, design, simulation methodology, and test strategy of the chip is discussed View full abstract»

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  • A design planner including a fast predictive floorplanning tool

    Publication Year: 1990, Page(s):208 - 213
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The design planner presented in this paper starts from a description of a circuit in terms of interconnected blocks which may be hard blocks (macrocells in a library, generated blocks like RAMs, PLAs) or soft blocks usually generated by synthesis tools. The design planner predicts the cost of a circuit in terms of area, yield and other issues (power, consumption, packaging), according to different... View full abstract»

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  • A mixed digital-analog simulation and test environment

    Publication Year: 1990, Page(s):7 - 10
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A mixed digital-analog simulation and test environment, MIXTEST, has been developed, bridging the gap between a design and test department by automatic translation of the simulation results from the mixed digital-analog simulator, MIXSIM, into a mixed test program. This system truly allows design for testability on mixed digital-analog circuits, by using a test machine database containing all rest... View full abstract»

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  • A test strategy for mixed analog/digital ASICS

    Publication Year: 1990, Page(s):300 - 304
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Typical examples of analog functions and their testing are described. It is shown, that these tests can be performed on digital testers. A test strategy for mixed ASICs is proposed, as an extension of techniques applicable to digital ASICs View full abstract»

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  • Analog circuit synthesis with simplified knowledge acquisition and fast transistor sizing

    Publication Year: 1990, Page(s):28 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Presents a system for analog CMOS circuit synthesis. It tries to overcome shortcomings of the rule based expert system approach at the stage of the circuit composition and provides sized netlists without simulation based optimization being necessary. A functional description of the required circuit is used to compose an application-appropriate schematic out of a set of parameterizable subcells. Tr... View full abstract»

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  • A MC680x0 compatible coprocessor for binary image processing

    Publication Year: 1990, Page(s):378 - 381
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A new ASIC coprocessor has been designed binary image processing applications. This dedicated IC has been fabricated in a 1.5 micron CMOS technology and contains 50000 gates. An important feature is that the chip is developed to be fully compatible with the Motorola MC680x0 family of processors. It works in coprocessor or peripheral mode on a 8-, 16- or a 32-bit bus View full abstract»

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  • VLSI area estimation tolerances-shape function generation vs. floorplanning

    Publication Year: 1990, Page(s):202 - 207
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Area estimation is an important task during the planning of VLSI systems. Several methods have been proposed. But how can one determine the reliability of an estimate? Can an estimate be 100% correct? The answer is no because the design process is not fully predictable. The predictability is an upper limit for the reliability of estimates. Reliability and predictability are defined and examples gi... View full abstract»

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  • ASIC design methods using VHDL

    Publication Year: 1990, Page(s):176 - 179
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The design of increasingly more complex custom and semicustom integrated circuits has traditionally forced the introduction of new design methodologies. Formal specifications, top-down design, and design-for-test have become standard practices for IC design teams. The adoption of VHDL (VHSIC Hardware Description Language), as an IEEE standard (IEEE-1076), and the recent availability of design auto... View full abstract»

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  • ADS analog digital system, a novel approach to CAD for mixed analog/digital ASICs

    Publication Year: 1990, Page(s):4 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The STKM2000 library is really a merged library: a merge between bipolar and CMOS technologies, a merge between analog and digital functions, a merge between CAD and design concepts. This `merged' library is able to answer to most of system requirements between sensors and actuators, from lower to video frequencies, from 2.7 V to 11 V applications, with the possibility of accurate functions. With ... View full abstract»

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  • A test vehicle for monitoring and improvement of CMOS reliability performance

    Publication Year: 1990, Page(s):444 - 448
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Monitoring reliability performance through accelerated testing on products is at least incomplete and failure analysis is difficult. Device level reliability stress tests are an attractive complement, and offer a wider range of overstresses, a clearer relationship between stress and failure, and reduced stress times. A 2.0 micron CMOS testchip has been built, containing stress patterns for interco... View full abstract»

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  • Analog-digital integrated test concerns

    Publication Year: 1990, Page(s):296 - 299
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Considers the practical test issues concerned with design verification of prototype mixed signal components. Mixed signal testing is treated as an extension to familiar digital test techniques View full abstract»

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  • Domain-specific analog/digital integrated circuits in the gate-forest environment

    Publication Year: 1990, Page(s):22 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    An innovative concept for domain-specific mixed analog/digital integrated circuits is introduced. Two exemplary ICs are detailed showing how flexible analog circuitry is merged with the customizable digital Gate-Forest to respond to specific multi-client demands. The domains of smart power and analog control are addressed. Direct-write E-beam supports short turn-around prototyping even for environ... View full abstract»

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  • Scan design in the Philips ASIC test environment

    Publication Year: 1990, Page(s):370 - 375
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability ana... View full abstract»

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  • An ASIC controller for the TMS 320, 2-generation digital signal processor

    Publication Year: 1990, Page(s):197 - 200
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA View full abstract»

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  • VHDL-Forum for CAD in Europe: an engineering & scientific point of view

    Publication Year: 1990, Page(s):172 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    As it is well known, the development of the hardware description language (HDL) VHDL was started in 1980 sponsored by the US Department of Defense. Today VHDL has become an important topic in research development, and CAE fields in the US as well as in Europe. Because of this development, user groups were established during the last years, namely the VHD Users' Group (US) and the VHDL-Forum for CA... View full abstract»

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  • Latch-up characterization of semicustom using ATE

    Publication Year: 1990, Page(s):439 - 443
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    An ATE approach for latch-up static test is proposed that allows a quick and complete characterization of devices even with a very high pin count. The software tool is described and some results presented View full abstract»

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