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Date May 29 1990-June 1 1990

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Displaying Results 1 - 25 of 90
  • EURO ASIC '90 (Cat. No.90TH0316-0)

    Publication Year: 1990
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    Freely Available from IEEE
  • Scan design in the Philips ASIC test environment

    Publication Year: 1990, Page(s):370 - 375
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability ana... View full abstract»

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  • Dedicated processor for partial differential equation solver

    Publication Year: 1990, Page(s):244 - 247
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A hardware solver for ΔΨ=f(Ψ), by the finite-difference method in 3D is presented. The general architecture is given: several identical processors run in a parallel mode in a PC-type environment. Each processor is a specific circuit (ASIC). The arithmetic unit has been integrated in a CMOS 2 μm technology. Using this circuit to simulate potential distribution in silicon devices sh... View full abstract»

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  • A semi-custom pad library

    Publication Year: 1990, Page(s):456 - 460
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Describes the design of a pad library for a semi-custom array family. It discusses the requirements defined by the application environment of semi-custom arrays. These requirements are subsequently translated into components and their respective characteristics. Three types of pads are distinguished: (1) power pads; (2) input, output, bi-directional and tri-state pads; and (3) special pads. The de... View full abstract»

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  • A highly flexible dual-port-RAM compiler

    Publication Year: 1990, Page(s):277 - 281
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A highly flexible dual-port-RAM compiler will be presented. A very robust design flow facilitates the integration of specially tailored dual-port-RAMs into ASIC designs even by non IC literate users. Generated modules contain all the necessary representations for use in the design system together with a proprietary standard cell library. The major application areas for dual-port-RAMs are cache mem... View full abstract»

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  • Design of an analog I/O ASIC for baseband conversion in digital mobile radio applications

    Publication Year: 1990, Page(s):15 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The design is discussed. The part is a complete input/output device with a single 5 V supply. As it is necessary for mobile systems to use the lowest possible power, the device has independent power down modes for both the transmit and receive sections of the chip. The part is housed in a space efficient 44 pin PQFP View full abstract»

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  • A mixed analog/digital ASIC for real time spectrum analysis

    Publication Year: 1990, Page(s):192 - 195
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A circuit dedicated to real time spectrum analysis has been implemented in a 3 microns CMOS technology. Power spectral density is measured with an error of less than 1% in a frequency range from 100 Hz to 50 kHz. Specific dynamic offset reduction techniques have been developed for the full custom analog part. Real time programming is possible through the standard cell digital part View full abstract»

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  • Comparison between a chip for realtime skeleting of images and its corresponding discrete realisation-a case study

    Publication Year: 1990, Page(s):382 - 385
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A chip and a corresponding PCB solution performing the special task of thinning is presented. Thinning, a common task in the field of image processing, preserves the overall structure of the image while making lines thinner and pixel spots smaller. While thinning (skeleting) is only available on special image processing architectures in realtime or has been implemented in `slow' software, both sol... View full abstract»

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  • A floating-point systolic array processing element using serial communication

    Publication Year: 1990, Page(s):240 - 243
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The authors describe the design of a processing element (PE) for systolic array applications. The PE which is configured as a multiplier-accumulator or an inner product step processor, supports most common systolic algorithms in signal processing and matrix arithmetic. Communication with neighbouring PEs is achieved through 18 on-chip serial links, each operating at 50 Mb per second. The 30 K tran... View full abstract»

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  • A design-system for ASIC's with macrocells

    Publication Year: 1990, Page(s):220 - 224
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors report on a design system for the physical layout of ASIC's with macrocells, which has been developed during the last three years in the framework of a research contact with IBM Germany and used successfully in practice. The main idea is to apply a hierarchical placement procedure together with global routing and timing analysis. This technique enables one to guarantee at each step of ... View full abstract»

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  • Designing an ASIC with the VLSI Technology ASIC synthesizer

    Publication Year: 1990, Page(s):257 - 260
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    Gives an overview of the VLSI Technology ASIC synthesizer. It is a synthesis tool that is able to compile whole chips from a hardware description language specification. Synthesis tools like this will increase the productivity of chip design to such an extent that current techniques of circuit design will someday be obsolete. The authors describe in this paper the capabilities that the ASIC Synthe... View full abstract»

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  • Domain-specific analog/digital integrated circuits in the gate-forest environment

    Publication Year: 1990, Page(s):22 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    An innovative concept for domain-specific mixed analog/digital integrated circuits is introduced. Two exemplary ICs are detailed showing how flexible analog circuitry is merged with the customizable digital Gate-Forest to respond to specific multi-client demands. The domains of smart power and analog control are addressed. Direct-write E-beam supports short turn-around prototyping even for environ... View full abstract»

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  • An ASIC controller for the TMS 320, 2-generation digital signal processor

    Publication Year: 1990, Page(s):197 - 200
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA View full abstract»

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  • CASTOR: state assignment in a finite state machine synthesis system

    Publication Year: 1990, Page(s):130 - 134
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The authors describe some of the state assignment heuristics, which are applied in the finite state machine synthesis system CASTOR. They concentrate on algorithms for two-level logic implementations, while work on algorithms for multi-level logic implementations is in progress. Input to the system is a description of the FSM in form of a state table. CASTOR generates an appropriate controller con... View full abstract»

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  • Latch-up characterization of semicustom using ATE

    Publication Year: 1990, Page(s):439 - 443
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    An ATE approach for latch-up static test is proposed that allows a quick and complete characterization of devices even with a very high pin count. The software tool is described and some results presented View full abstract»

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  • Extension of the MOSART circuit simulator to the analysis of BiCMOS circuits

    Publication Year: 1990, Page(s):350 - 353
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    MOSART is a MOS-VLSI time-domain simulator which implements the waveform relaxation analysis technique. The extension of the simulator to mixed bipolar-MOS circuits presented in this paper makes use of the particular structure of such circuits to decompose them without `breaking' the bipolar transistors. A modified decomposition algorithm along with some application examples are also presented View full abstract»

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  • Pegasus-an ASIC implementation of high-performance PROLOG processor

    Publication Year: 1990, Page(s):156 - 159
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Pegasus is a single chip RISC microprocessor dedicated to the PROLOG language. Although implementing many ideas for the fast execution of PROLOG programs, its datapath and control are still kept very simple in line with RISC design. A prototype chip of Pegasus was fabricated in 1.5μm CMOS technology and integrates 80000 transistors in a 9.7 mm square chip area. For quick fabrication and design ... View full abstract»

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  • A routing concept for large sea-of-gates designs

    Publication Year: 1990, Page(s):225 - 229
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Sea-of-gates (SoG) is becoming a very important design style for ASICs. Due to a larger flexibility in placement and routing, SoG can achieve higher densities and gate count than conventional gate arrays. Ion this paper the authors describe a routing environment and a routing methodology utilizing all features of this new design style, aiming to automatically complete a large design with high gate... View full abstract»

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  • Layout automation of CMOS analog building blocks with CADENCE

    Publication Year: 1990, Page(s):86 - 88
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. T... View full abstract»

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  • ASICs for an interface ring network

    Publication Year: 1990, Page(s):167 - 170
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    An application-specific-integrated-circuit (ASIC) family is presented in this paper. Its purpose is to interface a computer with the outer world with low cost and high flexibility, by means of a network of serially communicating ASICs. A communication protocol specially devised to be easily implemented by a set of ASICs is described, then details about the circuit design are given View full abstract»

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  • A test strategy for mixed analog/digital ASICS

    Publication Year: 1990, Page(s):300 - 304
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Typical examples of analog functions and their testing are described. It is shown, that these tests can be performed on digital testers. A test strategy for mixed ASICs is proposed, as an extension of techniques applicable to digital ASICs View full abstract»

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  • Verifying ASICs by symbolic simulation

    Publication Year: 1990, Page(s):468 - 473
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level is presented. The tool has been used extensively in a design center for ASICS, and several real-life applications of it are described. The basis of the new tool is formed by efficient algorithms for manipulating Boolean functions and finite-state machines. Among the applications of the tool a... View full abstract»

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  • VLSI area estimation tolerances-shape function generation vs. floorplanning

    Publication Year: 1990, Page(s):202 - 207
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Area estimation is an important task during the planning of VLSI systems. Several methods have been proposed. But how can one determine the reliability of an estimate? Can an estimate be 100% correct? The answer is no because the design process is not fully predictable. The predictability is an upper limit for the reliability of estimates. Reliability and predictability are defined and examples gi... View full abstract»

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  • Improved techniques for the synthesis and layout of mixed analog digital ASICs

    Publication Year: 1990, Page(s):38 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The most critical part of design automation of mixed analog digital circuits is layout related dependency of electrical characteristic of precision and sensitive analog parts of the ASIC. Circuit compilation principles and layout compilation principles are discussed. Design methodology, previously introduced, is refined to accommodate a wide variety of designs. A few design examples illustrating t... View full abstract»

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  • Integration of a microprogrammed CPU

    Publication Year: 1990, Page(s):113 - 116
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    For many airborne digital data processing applications, equipment suppliers have developed discrete circuit solutions based upon bit slice processors. The ASIC-based replacement of a preexisting discrete components computer was a good opportunity to introduce some architectural enhancements. The authors describe these evolutions as well as the design methodology. Two comparisons are performed usin... View full abstract»

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