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Proceedings of IEEE 11th Symposium on Computer Arithmetic

June 29 1993-July 2 1993

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  • Proceedings of IEEE 11th Symposium on Computer Arithmetic

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (60 KB)
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  • Exact rounding of certain elementary functions

    Publication Year: 1993, Page(s):138 - 145
    Cited by:  Papers (21)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    An algorithm is described which produces exactly rounded results for the functions of reciprocal, square root, 2x, and log 2 x. Hardware designs based on this algorithm are presented for floating point numbers with 16- and 24-b significands. These designs use a polynomial approximation in which coefficients are originally selected based on the Chebyshev series approximation a... View full abstract»

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  • The design of a 64-bit integer multiplier/divider unit

    Publication Year: 1993, Page(s):171 - 178
    Cited by:  Papers (4)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The highlights of the design of an integer multiplier/divider unit for a 64-b processor are presented. The final design is the result of a compromise between performance, complexity, and transistor count. It is optimized for two specific operations with the same hardware being shared by the remaining operations. Thus, for example, the multiplier can be configured for the execution of several diffe... View full abstract»

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  • n × n carry-save multipliers without final addition

    Publication Year: 1993, Page(s):54 - 61
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Carry-save multipliers require an adder at the last step to convert the carry-sum representation of the most significant half of the result into an irredundant form. A multiplication scheme where by this conversion is performed with a circuit operating in parallel with the carry-save array is presented. The resulting implementation, when a radix-2 adder array is used, produces a result on 2n bits ... View full abstract»

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  • BKM: A new hardware algorithm for complex elementary functions

    Publication Year: 1993, Page(s):146 - 153
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An algorithm for computing complex logarithms and exponentials is proposed. The algorithm is based on shift-and-add elementary steps, and it generalizes the Cordic algorithm. It can compute the usual real elementary functions. This algorithm is more suitable for computations in a redundant number system than Cordic, since there is no scaling factor for computation of trigonometric functions View full abstract»

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  • Comparing several GCD algorithms

    Publication Year: 1993, Page(s):180 - 185
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The execution times of several algorithms for computing the GCD of arbitrary precision integers are compared. These algorithms are the known ones (Euclidean, binary, plus-minus), and the improved variants of these for multidigit computation (Lehmer and similar), as well as new algorithms introduced by the author: an improved Lehmer algorithm using two digits in partial consequence computation, and... View full abstract»

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  • Design of a fast validated dot product operation

    Publication Year: 1993, Page(s):62 - 69
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    A double precision dot product operation is designed in which the final rounded result is validated by raising exception flags if either the result incurs catastrophic cancellation or the result is not accurate to one unit in the last place (ulp). The design guarantees one ulp accuracy in the absence of catastrophic cancellation. The user can thus obtain validated results at marginal extra cost wi... View full abstract»

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  • Efficient complex matrix transformations with CORDIC

    Publication Year: 1993, Page(s):122 - 129
    Cited by:  Papers (5)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    A two-sided unitary transformation (Q transformation) structured to permit integrated evaluation and application using CORDIC primitives is introduced. The Q transformation is shown to be useful as an atomic operation in parallel arrays for computing the eigenvalue/singular value decomposition of Hermitian/arbitrary matrices, and three specific Q transformations that are needed in such arrays are ... View full abstract»

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  • The Gauss machine: A Galois-enhanced quadratic residue number system systolic array

    Publication Year: 1993, Page(s):156 - 162
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The Gauss machine is a SIMD systolic array architecture that takes advantage of the Galois-enhanced residue number system (GEQRNS) to form reduced-complexity arithmetic elements. The Gauss machine is targeted at front-end signal and image processing applications. A discrete prototype that achieves a peak rating of 320 million complex arithmetic operations per second while operating at 10 MHz has b... View full abstract»

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  • Adaptive beamforming using RNS arithmetic

    Publication Year: 1993, Page(s):36 - 43
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The adaptive beamforming problem is solved using an algorithm-architecture-arithmetic combination that can be used for a small platform such as are found on aircraft or sonobuoys. The arithmetic used is the RNS system implemented on an array of processors that can be reassigned as the algorithm proceeds. The underlying algorithm is a modified Gaussian elimination. The (non-RNS) division operations... View full abstract»

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  • A modular multiplication algorithm with triangle additions

    Publication Year: 1993, Page(s):272 - 276
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    An algorithm for multiple-precision modular multiplication is proposed. In the algorithm, the upper half triangle of the whole partial products is first added up, and then the residue of the sum is calculated. Next, the sum of the lower half triangle of the whole partial products is added to the residue, and then the residue of the total amount is calculated. An efficient procedure for residue cal... View full abstract»

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  • Efficient multiprecision floating point multiplication with optimal directional rounding

    Publication Year: 1993, Page(s):228 - 233
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    An algorithm is described for multiplying multiprecision floating-point numbers. The algorithm can produce either the smallest floating-point number greater than or equal to the true product, or the greatest floating-point number smaller than or equal to the true product. Software implementations of multiprecision floating-point multiplication can reduce the computation time by a factor of two if ... View full abstract»

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  • Fast evaluation of polynomials and inverses of polynomials

    Publication Year: 1993, Page(s):186 - 192
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The parallel and online (i.e., digit serial, most significant digit first) evaluation of polynomials and inverses of polynomials is dealt with. New algorithms and architectures are proposed for such evaluations. A 3-D implementation model is presented View full abstract»

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  • Multi-parallel convolvers

    Publication Year: 1993, Page(s):70 - 77
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    A scheme for a convolver design, called a multiparallel convolver, that is based on concurrent processing of p adjacent samples that are input simultaneously to the p-parallel convolver is presented. The scheme uses p units, each of which receives the input samples and produces one convolution every p samples; these are called p-phase subconvolvers. The detailed design of the p-phase subconvolvers... View full abstract»

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  • An underflow-induced graphics failure solved by SLI arithmetic

    Publication Year: 1993, Page(s):10 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Floating-point underflow is often regarded as either harmless or as an indication that the computational algorithm is in need of scaling. A counterexample to this view is given of a function for which contour plotting is difficult due to floating-point underflow. The function arose as an asymptotic solution to a model problem in turbulent combustion in which two chemical species (fuel and oxidizer... View full abstract»

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  • A lazy exact arithmetic

    Publication Year: 1993, Page(s):242 - 249
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Systems based on exact arithmetic are very slow. In practical situations, very few computations need be performed exactly as approximating the results is very often sufficient. Unfortunately, it is impossible to know at the time when the computation is called for whether an exact evaluation will be necessary or not. The arithmetic library presented here achieves laziness by postponing any exact co... View full abstract»

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  • On digit-recurrence division implementations for field programmable gate arrays

    Publication Year: 1993, Page(s):202 - 209
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic-intensive programs with the benefits of custom hardware but without the high cost of custom silicon implementations. Efficient mappings are key to fast arithmetic implementations on FPGAs. A process for developing such mappings with lookup table based FPGAs is explored. The development process is illustrated with SRT ... View full abstract»

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  • Division with speculation of quotient digits

    Publication Year: 1993, Page(s):87 - 94
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selection, so that implementations are limited to low-radix stages. A scheme is presented in which the quotient-digit is speculated and, when this speculation is incorrect, a rollback or a partial advance is performed. This results in a division operation with a shorter cycle time and a variable number of c... View full abstract»

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  • Floating point Cordic

    Publication Year: 1993, Page(s):130 - 137
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A full-precision floating-point Cordic algorithm, suitable for the implementation of a word-serial Cordic architecture, is presented. The extension to existing block floating-point Cordic algorithms is in a floating-point representation for the angle. The angle is represented as a combination of exponent, microrotation bits, and two bits to indicate prerotations over π2 and π radians. Repres... View full abstract»

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  • A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency

    Publication Year: 1993, Page(s):163 - 170
    Cited by:  Papers (14)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    The authors describe a numeric processor with a kernel that is a tree of redundant binary adders and effects either a 17 × 69-b multiply-and-add or a 19 × 69-b multiply with exact redundant binary output and single cycle latency. Feedback paths selectively allow a high-order or low-order part of the adder tree output to be fed back in redundant binary form to the multiplicand and/or ad... View full abstract»

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  • Integer mapping architectures for the polynomial ring engine

    Publication Year: 1993, Page(s):44 - 51
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A finite polynomial ring structure for mapping inner product computations to parallel independent ring computations over 3-b moduli has been introduced by N.M. Wigley et al. (1992). The main algorithmic computation architecture can be implemented using well-established systolic array mapping principles, and a project to construct a Polynomial Ring Engine (PRE) is underway to exploit the VLSI imple... View full abstract»

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  • Very high radix division with selection by rounding and prescaling

    Publication Year: 1993, Page(s):112 - 119
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A division algorithm in which the quotient-digit selection is performed by rounding the shifted residual in carry-save form is presented. To allow the use of this simple function, the divisor (and dividend) is prescaled to a range close to one. The implementation presented results in a fast iteration because of the use of carry-save forms and suitable recodings. The execution time is calculated, a... View full abstract»

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  • Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing

    Publication Year: 1993, Page(s):28 - 35
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    This paper proposes combining system-level modular redundancy with the arithmetic modularity of residue number system (RNS) arithmetic to achieve fault tolerance in high speed digital signal processing (DSP) systems. Double, triple, and quadruple modular redundancy are combined with RNS modularity for realizing important DSP computational kernels. The discussion includes the development of the ser... View full abstract»

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  • On squaring and multiplying large integers

    Publication Year: 1993, Page(s):260 - 271
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Methods of squaring large integers are discussed. The obvious O(n 2) method turns out to be best for small numbers. The existing ≈ O(n1.585) method becomes better as the numbers get bigger. New methods that are ≈ O(n1.465) and ≈ O(n 2.404) are presented. All of these methods can be generalized to multiplication and turn out to be faster than a f... View full abstract»

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  • Exploiting trivial and redundant computation

    Publication Year: 1993, Page(s):220 - 227
    Cited by:  Papers (23)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    The notion of trivial computation, in which the appearance of simple operands renders potentially complex operations simple, is discussed. An example of a trivial operation is integer division, where the divisor is two; the division becomes a simple shift operation. The concept of redundant computation, in which some operation repeatedly does the same function because it repeatedly sees the same o... View full abstract»

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