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Software Support and CAD Techniques for FPGAs, IEE Colloquium on

Date 13 Apr 1994

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Displaying Results 1 - 9 of 9
  • Development tools ease programmable logic design portability

    Page(s): 2/1 - 2/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    The evolutionary nature of product development often leads to the re-use of portions of previous designs. With the latest programmable logic development systems, technology migrations are supported in multiple ways. High-level languages and the latest synthesis tools allow a high-level description of a design to be easily targeted to an FPGA or CPLD architecture. For schematic entry, "portable" library symbols that can be mapped to multiple architectures provide for migrations between differing programmable logic devices View full abstract»

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  • Neural networks in ballistocardiography (BCG) using FPGAs

    Page(s): 7/1 - 7/5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    Artificial neural networks have shown good capabilities in medical diagnostic applications. They offer the advantage that they are able to learn the representation by examples, which is of great benefit when the nature of the process is unknown or is difficult to characterise. On the other hand, the hardware implementation of the parallel network structure can dramatically improve the network efficiency. Here, a hardware implementation of neural network based ballistocardiogram (BCG) classification system with field programmable gate arrays (FPGAs) technology is presented. The specific trained neural network is implemented in Xilinx XC4000 series FPGAs View full abstract»

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  • Applying high-level synthesis techniques to FPGA-based design

    Page(s): 5/1 - 5/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    This paper describes a prototype of an automatic behavioural synthesis system targetted at FPGA-based reconfigurable digital systems. Experiments with the system, especially for synthesising random number generators, shows that register-transfer level hardware costs do not reflect hardware costs in terms of FPGA resource (e.g. Xilinx CLBs). This shows that extensive efforts that have been spent in the past for optimizing RTL-hardware costs need to be reconsidered. For this particular example, a simple register allocation (i.e. no register allocation at all) is much better than register allocation based on the left-edge algorithm. Experiments in synthesising random number generators involving both FPGAs and RAMs also shows that behavioural equivalent circuits with the same number and types of RTL-hardware units require different number of CLBs View full abstract»

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  • FPGA design with Mentor and Altera CAD software

    Page(s): 1/1 - 1/5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    This paper is an overview of top-down design with Mentor and Altera CAD tools. It outlines the entire process of designing hardware from writing VHDL to mapping the design to an FPGA. Intermediate steps including synthesis, optimisation, function simulation, layout and partitioning are also discussed. The conclusion derives from our experiences View full abstract»

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  • Postlayout simulation of FPGAs using verilog

    Page(s): 6/1 - 6/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    Postlayout simulation has proved to be an invaluable tool both for research and teaching purposes, allowing the designer to observe the operation of the device without the need for complex test equipment. A further benefit is that from within the Cadence environment it is possible to probe and trace internal signals, allowing the input and outputs of the logic blocks to be monitored View full abstract»

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  • Mapping VHDL descriptions of digital systems to FPGAs

    Page(s): 9/1 - 9/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    FPGAs provide a ready means of realising medium to large digital systems in a cost effective manner. As the complexity of these components increases there is a need to provide suitable high-level tools. All vendors offer suites of design tools for their products: these could be interfaces to standard schematic capture packages so that netlists can be provided. These netlists are then processed by the device-specific layout and interconnect tools to produce the final design. Tn addition to this route, some vendors offer editors which enable individual cells to be personalized, The trend in system design is to use high-level descriptions as much as possible, so that designs are to a large extent self-documenting. When high-level hardware description languages are employed then there are tools available which map or compile the design to the target hardware. These tools are in their infancy and hence they tend to deal only with subsets of the languages. The tools which this paper describes are concerned with automating the migration of a design created in VHDL to programmable logic View full abstract»

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  • FPGA development tools: keeping pace with design complexity

    Page(s): 3/1 - 3/3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    FPGA tool vendors are paying increased attention to the needs of logic designers. Dramatic advances are being made in the areas of design entry methods, synthesis, partitioning, placement and routing algorithms, system simulation, and tool integration, to name but a few. FPGA tools are evolving into fully integrated tool sets that support sophisticated synthesis-based design environments. The result is a boon to FPGA users, who have access to increasingly effective CAE tools supporting a wide variety of needs, desires, and budgets View full abstract»

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  • The route from VHDL to FPGA using synthesis

    Page(s): 8/1 - 8/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    VHDL started to be standardized by the American government in February 1986 as a hardware description language for specifying military systems. Since then it has undergone two major revisions by the IEEE. This paper describes the use of VHDL in the design of a transputer Global Link Adapter (GLA) and the route taken to produce a final Xilinx FPGA using Viewlogic View full abstract»

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  • Optimisation techniques based on the use of genetic algorithms (GAs) for logic implementation on FPGAs

    Page(s): 4/1 - 4/4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    The work described in this paper began some time ago as an investigation into two problems associated with logic minimisation or optimisation. These are respectively, the state assignment problem in the design of finite state machines, and the optimisation of combinational logic circuits using Reed-Muller (RM) techniques. When faced with such designs, the use of FPGAs to implement circuits is clearly appropriate. However, because of the limited resources available on FPGA parts, in terms of the number of available CLBs, and the increased difficulty that place and route software will experience in the layout of increasingly complex designs, it is felt that some form of optimisation of the design before implementation is still a necessary stage in the design process. This paper describes the implementation of algorithms which attempt to provide this type of optimisation for the two previously mentioned problems. The resultant software uses genetic algorithms to select, breed and test the fitness of potential solutions, and thereby recommend a near-optimal solution. In practice, these recommended solutions represent a considerable saving (in terms of gate count) on many circuit implementations, as experimental results demonstrate View full abstract»

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