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Electronic Components and Technology Conference, 1994. Proceedings., 44th

Date 1-4 May 1994

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  • 1994 Proceedings. 44th Electronic Components and Technology Conference

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    Freely Available from IEEE
  • Tantalum chip capacitor reliability in high surge and ripple current applications

    Page(s): 861 - 868
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    Relentless miniaturization of electronic circuitry and the general movement from through-hole to surface-mount manufacturing have generated explosive growth in the use of surface mount tantalum chip capacitors. Many of these applications involve substantial exposure to surge and ripple currents. Such exposure invites questions regarding the impact of surge and ripple current on the long-term reliability of tantalum chip capacitors. To facilitate a better understanding of the impact of surge and ripple current on tantalum chip capacitor reliability, theoretical analyses of generic circuits are supported with discussion of experimental data. Simple circuits that highlight the fundamental theoretical principles behind transient surge and steady-state ripple current applications are analyzed and pertinent reliability issues are discussed. The relationship of device ESR (equivalent series resistance) to surge and ripple current robustness and device temperature rise is established theoretically. Surge and ripple current test and measurement methods are briefly discussed and experimental test data are used to support many of the insights that are drawn from theory View full abstract»

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  • An interface for numerical analysis of convective heat transfer from printed circuit boards

    Page(s): 653 - 658
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    A geometrically-based user interface has been developed as a preprocessor for a numerical model of convective heat transfer from printed circuit boards (PCB). The physical problem is specified in a natural way as a collection of the control parameters and the objects that exist within the computational domain. Complicated configurations of discrete electronic components on a circuit board is represented by several simple physical objects with specified boundary conditions and heat-generating status. No reference to node or element number is needed and the input order of the objects can be arbitrary. The preprocessor program automatically sorts the coordinates of each object, subdivides the computational domain, eliminates the redundant coordinates and generates an object grid system that is consistent with the physical configurations of PCBs. This three dimensional geometrically-based object grid system is integrated to the main analysis codes for solving flow and temperature distribution. The geometrically-based model specification provides the hooks for a graphical user interface (GUI) which could be added later View full abstract»

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  • KGD levels and effects

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    Summary form only given, as follows. This paper presents the authors definition of Known Good Die, and discusses various KGD processes and associated yields. Die quality versus first time module assembly yield, and die reliability versus module failures in time (FIT) are also discussed. The author also examines KGD processing costs and tradeoffs to module costs View full abstract»

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  • Exceptional performance from the development, qualification and implementation of a silicone adhesive for bonding heatsinks to semiconductor packages

    Page(s): 260 - 269
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    The stress induced by the Coefficient of Thermal Expansion (CTE) mismatch of ceramic semiconductor packages bonded to aluminum heatsinks created a high risk of cracking. As packages increase in size and power, the need for an advanced adhesive with compliant properties, reliable bond strengths and high thermal performance is required. As a result of the work reported here, heatsink attach capabilities have been enhanced significantly with attractive cost benefits. Epoxy, silicone and polyimidesilaxoane adhesives were investigated for their process, material, reliability, and thermal performance. The project was divided into three phases: process development, qualification, and implementation. Concurrent engineering was emphasized to deliver a high-quality and low-cost process to production in a timely manner. In the initial development phase, over forty commercial and proprietary adhesives were evaluated based on the CTE, modulus and bond strength subjected to thermal cycling and moisture tests. A predictive thermo-mechanical and mechanical model was developed to define the required adhesive properties as a function of heatsinks weight and geometries. The wafer bow technique was used to estimate the induced stress from adhesive attach View full abstract»

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  • Iterative direct solution method for thermal analysis of electronic equipment

    Page(s): 644 - 652
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    The numerical procedure described in this work performs analysis of 3-dimensional structures by partitioning the geometry in basic blocks, which can be described as multi-layer-structures with rectangular base area. Combining such basic regions, complex geometries like stacked structures can be treated. The Laplacian equation describing the steady state heat flux is solved efficiently in three dimensions using a Fast Fourier Transform (FFT) algorithm. By the use of an iterative procedure handling of inhomogeneous, nonlinear boundary conditions on the top and bottom side of the geometry and modeling complex geometries by matching the solution at the interface of two or more basic blocks is possible. This allows to take into account boundary conditions calculated by the analytical solution of the Navier-Stokes equations describing convection and the Stefan Boltzmann law describing radiation. Experimental studies using infrared thermography, thermal sensors and laser doppler velocimetry were carried out. By measurement of the temperature distribution and the flow field it is shown, that the simultaneous solution of the heat flux in the solid structure and the heat-transfer by boundary approximation improves the accuracy of temperature computation and expands the application range of the Fourier method. It is shown, that parallel placed substrates with bare chips can be handled with high accuracy by the proposed model for laminar flow. The model gives good results for mountings up to 0.6 mm height. For low fluid velocities up to 1 m/s and natural convection the model works also for higher mountings (e.g. SMD). Further applications demonstrate the accuracy and applicability of the presented program. The simple model-creation and the numerical efficiency enables the handling of problems with a high number of components and high aspect ratios between the components and the board. Analytical models describing heat dissipation in special applications can be easily incorporated for simultaneous solution View full abstract»

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  • Electrical failure of multilayer ceramic capacitors caused by high temperature and high humidity environment

    Page(s): 847 - 853
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    In this paper, the electrical behavior of multilayer ceramic capacitors (MLCs) in strict dynamic high temperature-humidity-DC bias voltage (THB) conditions were studied and the failure model of MLCs under such conditions was proposed. It was found, if the environmental temperature and humidity rose too fast and the temperature of a MLC was lower than the dew point temperature of surrounding moist air, dewdrops would condense on the MLC surface. When DC voltage was applied, metallic ions from end terminations of the MLC would migrate along the condensed water film on the MLC surface and made a permanent short-circuiting path between two terminations. Silver and tin migrations were found by EDX detection in our experiment. It was also found that the applied DC electrical loading level had a strong influence on the fail rate of MLCs. The recovery rate of MLCs after the dynamic THB process decreased with applied DC voltage increasing. To reduce the effect of dewdrops of moist air on the reliability of MLCs, the method and speed of temperature and humidity rise are discussed View full abstract»

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  • Analysis of laser CVD SiN-Si system TFD characteristics by DLTS

    Page(s): 640 - 643
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    SiN-Si TFD (thin film diode) was fabricated by photo-chemically depositing SiN films on Si substrate by ArF excimer laser CVD and depositing Al electrodes on SiN films by evaporation. SiN films were deposited from SiH4 (95% SiH4+5% Ar), NH3 (99.99%) gas mixture with N2 carrier gas. The substrate temperatures and chamber pressures were varied to investigate the properties of SiN film and their effects on TFD characteristics. And the optimum condition for SiN deposition was achieved. Deposition rate and refractive index of SiN film showed a strong dependence on substrate temperature. This result is in accordance with the FT-IR analysis which apparently showed the dependence of N-H, Si-H and Si-N bonding strength on substrate temperature. High frequency C-V curve showed slight hysteresis and interface state density Nss obtained from DLTS signals with different DLTS timings (TD, TP, TS) decreased with increasing substrate temperature and a increased slightly with increasing chamber pressure View full abstract»

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  • Thermal characterization of a tape carrier package

    Page(s): 532 - 538
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    The unenhanced thermal performance of Tape carrier Package (TCP) packages on 8 layer boards with internal planes is 19 C/W. Simple PCB enhancements such as the addition of thermal vias, alone or with the use of low profile heatsinks, brings the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling options available. With forced convection cooling, devices with a power dissipation requirement of up to 4.7 C/W can be packaged in TCP format View full abstract»

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  • Impact of moisture/reflow induced delaminations on integrated circuit thermal performance

    Page(s): 527 - 531
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    Ambient moisture uptake in plastic surface mount IC packages can cause delamination of critical internal surfaces within the package during reflow assembly. Delaminations can result in reduced thermal cycling life performance or provide for a pathway for the ingress of chemicals and contaminates. The effects that moisture/reflow induced delaminations can have on the thermal performance of plastic packaged ICs are not entirely understood. In this paper, the thermal performance of moisture/reflow delaminated ICs is reported. The effective sensitivity of the thermal performance as a result of the moisture/reflow induced delaminations was measured by experimental thermal resistance measurements (θJA) and compared to theoretical calculations based on Finite Element Analysis (FEA). Both 3-D and 2-D FEA models were developed for predictive responses which gave excellent correlation to the experimental measurements. The results showed that interfacial delaminations can cause a measurable increase in θJA. The magnitude of the increase is found to be proportional to the power consumption of the device and dependent on the delamination gap thickness. Expected reliability degradation as a result of die temperature rise from the interfacial delaminations is most significant for plastic packaged devices of power ratings greater than about 1 W View full abstract»

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  • Concurrent packaging architecture design

    Page(s): 75 - 80
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    Packaging is one of the primary constraints on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of the physical structure of such systems is presented here. Architecture, electrical, performance and energy management aspects are included. The CAD tool AUDiT implements this design methodology. The concurrent design capability has been illustrated using a model system derived from the high speed Digital Equipment 3000/500 (Alpha) engineering workstation View full abstract»

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  • The impact of driver impedance upon transmission line impedance

    Page(s): 669 - 675
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    The principle feature of robust design for quality is parameter design: selecting the design parameters to minimize quality loss. The tolerance in interconnection characteristic impedance (Zo) can impact the cost of a printed circuit board (PCB), multichip module (MCM), or hybrid if the tolerance is too small and the cost of the interconnect has to absorb rejected parts. This paper extends a theory of controlled impedance design that is compatible with the principles of robust design for quality. Practical applications and broad implications of this theory are demonstrated. The results are pertinent to both designers and fabricators of interconnections for high speed digital systems. Designers of digital output drivers will see the effect of driver impedance upon transmission line impedance View full abstract»

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  • The passivation of GaAs by laser CVD

    Page(s): 635 - 639
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    In this study, properties of GaAs passivation films formed by laser CVD method are investigated. In order to develop GaAs devices, it is necessary to form insulators with good chemical stability, dielectric and interface properties on the GaAs surface in view of application to surface passivation and devices fabrication. SiN films were photolytically deposited by excimer laser with 193 nm wave length on P type (100) GaAs wafer in SiH4, NH3 and N2 gas mixture by varying the substrate temperature from 100°C to 300°C. The thickness and refractive index of the films as a function of substrate temperature were measured by a nanoscope and ellipsometer respectively. The chemical depth profiles of SiN films were obtained using Auger depth spectroscopy. In order to investigate interface properties of the SiN-P GaAs, MIS structure is made by Al electrode evaporation on SiN films and high frequency C-V and DLTS (Deep Level Transient Spectroscopy) measurements were carried out. And also, surface leakage current was measured between two Au/Ge evaporated electrodes separated 10 μm apart on P type GaAs wafer before and after SiN film formation. As the result, deposition rate of SiN films increases as substrate temperature increases, which is due to generation of more reactive species with increasing substrate temperature. Auger depth profiles indicate that diffusion length of Ga and As atoms toward SiN films is reduced as substrate temperature decreases. From the high frequency C-V curve, the hysteresis effect is reduced as substrate temperature decreases and interface trap density obtained from DLTS signals is lowered to 1012-1013 in the substrate temperature ranging from 100°C to 200°C. In addition the passivated SiN film on GaAs by laser CVD shows less surface leakage current compared with non-passivated GaAs View full abstract»

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  • Predicting solder joint shape by computer modeling

    Page(s): 1071 - 1078
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    Predictions of surface mount or through hole solder joint shape, based on the lead and pad geometry, solder volume, and material characteristics, can be used to improve soldering yield. This paper reports on a collaboration between Digital Equipment Corporation and Massachusetts Institute of Technology to develop a method to predict solder joint shapes. It concentrates on the application of a public domain software program called Surface Evolver to solder joint modeling. Surface Evolver uses numerical optimization techniques to compute the shape of capillary surfaces. Solder joints are one of many applications of Surface Evolver. It seems to be well suited to compute the shape of complex solder joints. Results from Surface Evolver are compared to shapes computed by other means, and to the shape of actual solder joints. Good agreement is obtained in most cases View full abstract»

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  • Efficiency of microlens arrays for projection LCD

    Page(s): 338 - 345
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    The properties relevant to the use of a microlens array in a projection LCD device are examined and discussed. In particular, the effect of the lens geometry, shape, focal length, cover glass thickness, and beam spread angle, are related to the optical performance as measured by the improvement in light transmission through the LCD. Experimental data suggest that the performance of a lens array with hexagonal cross-section and a focal length of 0.7 mm can lead to an 80% increase in the light through-put View full abstract»

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  • A novel, lower cost, thermally enhanced exposed silicon plastic package (ESPP)

    Page(s): 67 - 74
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    The plastic Quad Flat Package has evolved into a large, high pin count package, however higher reliability and thermal dissipation requirements constitute the boundary conditions it must overcome to evolve as a viable high density package. The present mold compounds used as encapsulants have poor thermal conductivities and represent a large portion of the thermal resistance in the plastic package. Existing thermally enhanced plastic packages are prone to delamination, and higher costs. A new plastic package is proposed herein that achieves a new level of reliability and performance, all at a cost lower than the standard plastic package. The ESPP package integrity is analyzed and compared to other thermally enhanced packages. Thermal performance is measured and compared to other packages View full abstract»

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  • Parallel optical interconnect modules with multifiber connectors

    Page(s): 324 - 329
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    The design, realisation, and characterisation of a multichannel DC-coupled parallel optical interconnection link with connectorized (pigtails) transmitter and receiver modules is reported. The link is electrically compatible to ECL voltage level, the aggregate data throughput is up to 12 Gbit/s (1 Gbit/s per channel). The transmitter modules consist of arrays of laser diodes with low threshold currents and 50 Ω matching networks, the receiver modules of photodiode arrays and amplifier arrays. All the opto-electronic and electronic components are fabricated as arrays with a pitch of 250 μm View full abstract»

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  • Rationalization of gold ball bond shear strengths

    Page(s): 733 - 740
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    Bond shear testing is becoming an indispensable tool for wirebonder machine set-up and bonding process monitoring. The lower acceptable limits, however, are defined based on historical data. This paper establishes the theoretical and statistical correlation between bond size, wire grain size, strain hardening and ultimate tensile strengths of the gold wire in relation to the Mode 1 (through the gold ball) shear strengths. Results of the study showed that the ball shear strength is strongly correlated with the bond aspect ratio which is the ratio of the ball diameter to the bond height. This parameter is easily obtainable from an automated vision inspection system and could provide initial information on the quality of the bond. The study also showed that the gold ball undergoes strain or work hardening during bonding. Bond shear strengths predicted from this work hardening conforms well with the actual data View full abstract»

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  • Modeling reactive ion etching of silicon dioxide films using neural networks

    Page(s): 273 - 278
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    Silicon dioxide films are useful as interlayer dielectrics for integrated circuits and multichip modules. Reactive ion etching (RIE) in RF glow discharges is used extensively to form via holes in SiO2 between metal layers of a multichip module. However, the precise modeling of RIE is difficult due to the extremely complex nature of particle dynamics within a plasma. Recently, empirical RIE models derived from neural networks have been shown to offer advantages in both accuracy and robustness over more traditional statistical approaches. In this paper, neural networks are used to build models of etch rate, anisotropy, uniformity, and selectivity for SiO2 films etched in a chloroform and oxygen plasma. Back-propagation neural nets were trained on data resulting from a 24 factorial experiment designed to characterize etch variation with RF power, pressure and gas composition. Etching took place in a Plasma Therm 700 series RIE system. Excellent agreement between model predictions and measured data was obtained View full abstract»

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  • Analysis of TAB inner lead fatigue in thermal cycle environments

    Page(s): 474 - 481
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    The inner leads of a Tape Automated Bonding (TAB) device can be subject to early fatigue failures in thermal cycle environments. This paper describes a 3-D non-linear finite element analysis of the failure mechanism, and verifies the results by experiment. Some TAB applications require environmental qualification and electrical testing in the unexcised tape carrier or retain a significant portion of the polyimide tape in the assembly. In these cases the Coefficient of Thermal Expansion (CTE) mismatch between the silicon die and polyimide tape can cause plastic strains in the inner leads. Several design variations are quantified. Those with first order effects were found to be encapsulant material, lead length, and lead material View full abstract»

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  • Packaging relaxed semiconductor lasers with diluted waveguide structure

    Page(s): 335 - 337
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    Without introducing extra processing steps, the idea of diluted waveguide is proposed and demonstrated to improve laser vertical modes. Such a new laser structures can simplify the work of laser-fiber coupling and relax the alignment tolerance. They may also be applied to obtain high power semiconductor lasers and polarization independent photonic devices View full abstract»

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  • Development of a high performance TQFP package

    Page(s): 57 - 62
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    A TQFP (Thin Quad Flat Pack) package has been developed that has very superior electrical and thermal performance when compared to a plastic molded TQFP package. The high performance TQFP is based on Olin's MQUAD technology; a packaging scheme where the plastic mold compound is replaced by an anodized aluminum base and lid adhesively sealed to the leadframe. The package uses the same IR or VPR board mounting profile as a plastic package, weighs the same as a plastic package, and is dimensionally equivalent to a plastic package View full abstract»

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  • Popcorn phenomena in a ball grid array package

    Page(s): 1101 - 1107
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    For the purpose of studying popcorn phenomena, plastic ball grid array packages with 119 I/O's were tested under the pre-conditioning test conditions. Observations using scanning acoustic tomography and optical microscopy were carried out to investigate the existence of delaminations and cracks in the package, and the cracking patterns after IR reflow. Package deformations and thermo-mechanical stress distributions in the package were calculated by the finite element method. Three types of substrates were tried to prove that open thermal viaholes under die pad could prevent popcorn cracking during IR reflow. From the experiments and the observations, it was concluded that package cracking, which was caused by the expansion of moisture concentrated at the die adhesive layer, could be prevented using open thermal viaholes under die pad. The open thermal viaholes acted as vent holes, through which the expanded water vapor could go outside, not causing popcorn cracking. The die-attach process using U.V. tape was effective in the assembly of the packages with open thermal viaholes View full abstract»

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  • Thin film metallization of three-dimensional substrates

    Page(s): 359 - 361
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    Metallization of three-dimensional (3D) molded polymer substrates by sputtering technology is an exciting alternative to traditional electroless plating processes. The technology offers the ability to rapidly coat the 3D circuit base without the use of precious metal catalysts or plating baths that may be environmentally harmful. Consequently, sputter coating of 3D circuits offers the advantages of high through-put and flexible manufacturing while minimizing disposable wastes. This paper focuses on the critical issues affecting the performance of sputtered thin film on 3D polymer substrates View full abstract»

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  • Role of materials evolution in VLSI plastic packages in improving reflow soldering performance

    Page(s): 177 - 185
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    Cracking of surface mounted plastic packages worsens with increasing die sizes and thinner packages, both are recent trends in packaging. The precursor to failure, delamination at a leadframe to polymer interface, suggests that improvements in mold compounds, die attach adhesives and leadframe surface finishes are key elements in a solution. Identifying which specific materials properties must be improved and to what degree is a major task, followed by working with vendors to supply improved materials. In this study, the strategy is to improve all weak interfaces in parallel, rather than simply strengthen the weakest link. An excellent measurement method capable of detecting small improvements in the measured reflow soldering performance of a test package (148 PQFP) quantified both its delamination and cracking performance. These studies identified a general weakness in polymer to Ag die pad interfaces, implying that improving the adherend is mandatory View full abstract»

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