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Proceedings of IEEE 3rd Asian Test Symposium (ATS)

15-17 Nov. 1994

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  • Proceedings of IEEE 3rd Asian Test Symposium (ATS)

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (55 KB)
    Freely Available from IEEE
  • Characteristics of a fuzzy test system

    Publication Year: 1994, Page(s):379 - 384
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Stable outgoing quality is assured by using a test system with a fuzzy controller, even when sudden changes of incoming quality occur. Non test is automatically selected, when incoming quality becomes far better than a target quality. The author studies how to check the stability condition of the fuzzy test system. The condition is that the value, the sample size at the t-th test divided by the si... View full abstract»

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  • Application of byte error detecting codes to the design of self-checking circuits

    Publication Year: 1994, Page(s):39 - 44
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code ... View full abstract»

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  • Design in fault isolating of ternary cellular arrays using ternary decision diagrams

    Publication Year: 1994, Page(s):201 - 206
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper proposes a method to design ternary cellular arrays with high testability. In it, stuck-at faults of switch cells are assumed. Testing of the array composed of switch cells can be executed easily because of the regular structure of the array. Moreover, if faulty cell is identified we can isolate the faulty cell from the remaining cells. The ternary functions represented by Ternary Decis... View full abstract»

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  • To verify manufacturing yield by testing

    Publication Year: 1994, Page(s):385 - 390
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The effect of test errors should be cancelled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the... View full abstract»

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  • Strongly fail-safe interfaces based on concurrent checking

    Publication Year: 1994, Page(s):45 - 50
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper presents a strongly fail safe interface which transforms binary signals, generated by a system with error detection capabilities and eventually with fault tolerant capabilities, into fail safe signals. That is to say into signals which in the presence of failures will be either correct or safe. The strongly fail-safe property is achieved by means of concurrent checking techniques. The i... View full abstract»

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  • Software design verification using FTA

    Publication Year: 1994, Page(s):208 - 213
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    We propose a verification approach for software specification. In order to avoid software design faults, our approach derives safety assertions using fault tree analysis, computes a behavioral graph of specification and analyzes statically whether this graph satisfies safety assertions. When there exists an assertion which can not hold, our method localizes software design faults. Moreover we show... View full abstract»

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  • Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides

    Publication Year: 1994, Page(s):360 - 365
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    First, we present switching networks and a reconstruction strategy for mesh-connected processor arrays with linear arrays of spares on their left/right/upper/bottom sides. Each faulty processor is compensated by a spare on any one of left/right/upper/bottom sides. The reconstruction is done by shifting vertically first and then horizontally. Such a new reconstruction strategy leads to the simple a... View full abstract»

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  • Evaluations of various TPG circuits for use in two-pattern testing

    Publication Year: 1994, Page(s):242 - 247
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Transition coverage has already been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-... View full abstract»

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  • Sequential test generation in massive observability environments

    Publication Year: 1994, Page(s):119 - 124
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper describes a sequential test generation method for circuits in massive observability environments such as those offered by quiescent current monitoring and gate arrays with embedded test points. Techniques to enhance the controllability of the circuit are also discussed and an algorithm for selecting storage elements to make accessible during the test mode is proposed View full abstract»

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  • Efficient techniques for multiple fault test generation

    Publication Year: 1994, Page(s):52 - 56
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques View full abstract»

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  • Efficient test sequence generation for localization of multiple faults in communication protocols

    Publication Year: 1994, Page(s):214 - 219
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Conformance test for communication protocols is indispensable for the production of reliable communications software. A lot of conformance test techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find ... View full abstract»

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  • Fault diagnosis technique for subranging ADCs

    Publication Year: 1994, Page(s):367 - 372
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    This paper describes a fault diagnosis technique for subranging analog to digital converters (ADCs). Functional fault in each of the analog component in the subranging ADC affects the transfer function differently. This property is employed for fault diagnosis. Deviation from ideal of the transfer function which is categorized into offset error, gain error, DNL, and INL data, are used for fault di... View full abstract»

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  • Detectability of spurious signals with limited propagation in combinational circuits

    Publication Year: 1994, Page(s):176 - 181
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation lim... View full abstract»

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  • A diagnostic network for massively parallel processing systems

    Publication Year: 1994, Page(s):348 - 353
    Cited by:  Papers (1)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Massively parallel processing systems consist of a large number of processing nodes to provide high performance primarily for data-intensive applications. In a system of such dimensions high availability cannot be achieved without relying on redundancy and reconfiguration. An important aspect of highly available design is rapid diagnosis and graceful degradation in the event of a failure. This pap... View full abstract»

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  • On crosstalk fault detection in hierarchical VLSI logic circuits

    Publication Year: 1994, Page(s):182 - 187
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A realistic crosstalk fault detector operating at hierarchical layout and logic level is presented. A set of filtering schemes are proposed to reduce considerably the set of probable single and multiple coupling faults with details on substrate resistivity and unbalanced buffer implications. Comparisons between flat and hierarchical layout approaches are reported together with the performances of ... View full abstract»

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  • C-testable multipliers based on the modified Booth algorithm

    Publication Year: 1994, Page(s):163 - 168
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    In this paper we show that the conventional implementation of the multiplier based on the modified Booth algorithm with 2-bit recording is not C-testable and then we propose simple modifications that result in a C-testable design. A test set of 80 vectors is sufficient to test each cell of our multiplier exhaustively, irrespectively of its size. All single stuck-at faults are detectable with only ... View full abstract»

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  • Data path synthesis for easy testability

    Publication Year: 1994, Page(s):317 - 322
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Synthesizing digital circuits which can be easily tested is an important and necessary aspect of a useful behavioral synthesis system. Testability at behavioral level can be enhanced by minimizing the number of self-adjacent registers (self-loops). This paper describes a technique for synthesizing an easy testable (loop-free) data path structure from a behavioral description of a design. The synth... View full abstract»

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  • Boolean process-an analytical approach to circuit representation

    Publication Year: 1994, Page(s):249 - 254
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    One of the most important and challenging problems in today's VLSI design is that of incorporating performance factors in the physical and logical design of VLSI circuits. In order to precisely describe circuit timing behavior, an analytical approach is introduced in this paper. A Boolean process is defined, which is a family of Boolean variables relevant to the time parameter t. A real-valued sam... View full abstract»

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  • Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis

    Publication Year: 1994, Page(s):126 - 131
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    A new method for the testing and fault detection of analog integrated circuits is presented. The power-supply current is monitored to detect possible faults in an analog circuit. The spectrum of the power-supply current is used to construct the statistical signature of the fault-free and faulty circuits. The decision of a circuit being fault-free or faulty is taken based on the Bayes decision rule... View full abstract»

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  • A sequential redundant fault identification scheme and its application to test generation

    Publication Year: 1994, Page(s):57 - 62
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This work presents an efficient method to identify sequential redundant faults. The method is based on a simple procedure to identify the flip-flops which cannot be initialized and the circuit lines which cannot be controlled to definite values. The redundant faults are classified into four types and the method can identify each type of them. The method has been experimentally incorporated into a ... View full abstract»

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  • Netlist automatic extractor: “An image processing based software for bare board test data generation”

    Publication Year: 1994, Page(s):220 - 225
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Bare PCB (printed circuit board) test data generation softwares are based on vectorized calculations. When they fail, the automatic network list extractor software developed by IMD/TIMA succeeds thanks to image processing and pattern recognition on bitmaps View full abstract»

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  • Test time reduction for scan-designed circuits by sliding compatibility

    Publication Year: 1994, Page(s):330 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A post generation method for test time reduction of scan-designed circuits is developed in this paper. Maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on ... View full abstract»

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  • Design verification by using universal test sets

    Publication Year: 1994, Page(s):261 - 266
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach View full abstract»

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  • A built-in IDDQ test circuit utilizing upper and lower limits

    Publication Year: 1994, Page(s):138 - 143
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A test circuit for the built-in IDDQ testing is proposed. The circuit can use two current values, an upper limit and a lower limit, to judge whether CUT is fault-free or not. The test circuit is applicable to fault detection for both digital and analog circuits. We show the efficiency of the test circuit using SPICE3 simulator View full abstract»

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