Proceedings of IEEE 3rd Asian Test Symposium (ATS)

15-17 Nov. 1994

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  • Proceedings of IEEE 3rd Asian Test Symposium (ATS)

    Publication Year: 1994
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  • Testable synthesis and testing of finite state machines

    Publication Year: 1994, Page(s):305 - 310
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    In this paper, me outline a method for testable synthesis of finite state machines (FSMs). We address the design for testability issue for testing FSMs with and without scan. The experimental results on the MCNC benchmarks show that our designs are 100% testable with small to moderate increase in area View full abstract»

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  • A partial scan algorithm based on reduced scan shift

    Publication Year: 1994, Page(s):336 - 341
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    This paper presents a partial scan algorithm, called PARES (Partial scan Algorithm based on REduced Scan shift), which designs partial scan circuits and generates short test sequences. PARES is based on the reduced scan shift, in which flip flops (FFs) required to be controlled and observed are determined for each test vector in order to reduce scan shift operations. PARES selects FFs which are mo... View full abstract»

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  • A sequential redundant fault identification scheme and its application to test generation

    Publication Year: 1994, Page(s):57 - 62
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    This work presents an efficient method to identify sequential redundant faults. The method is based on a simple procedure to identify the flip-flops which cannot be initialized and the circuit lines which cannot be controlled to definite values. The redundant faults are classified into four types and the method can identify each type of them. The method has been experimentally incorporated into a ... View full abstract»

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  • On full path delay fault testability of combinational circuits

    Publication Year: 1994, Page(s):311 - 316
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    We show that robust tests for all path delay faults in a combinational circuit are not necessary in order to avoid test invalidation due to undesired hazards. Further extension leads to the formulation of the necessary and sufficient conditions for any path delay fault in a multi-level combinational circuit to be testable without potential invalidation by undesired hazards. We prove that all algeb... View full abstract»

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  • Experiments of faults on the “Happa” system and a proposal of backup RAM technique

    Publication Year: 1994, Page(s):343 - 347
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    On the “Happa” parallel microcomputer system, faults were experimentally examined for the boundary of its operating range. Global bus faults, torus communication faults, and others were observed. A backup RAM technique is proposed for bus faults View full abstract»

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  • Test scheduling using test subsession partitioning

    Publication Year: 1994, Page(s):63 - 68
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    The tester time is expensive, which should be reduced as much as possible. Considering the fact that test response observation and test application only use a fraction of the whole testing time, a test subsession partitioning scheme is offered. Therefore, some further sources of the test scheduling problem are used. Subcircuits in conflict according to the definition are only partially in conflict... View full abstract»

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  • Efficient diagnostic fault simulation for sequential circuits

    Publication Year: 1994, Page(s):94 - 99
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    In this paper, an efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus reduces a great deal of diagnost... View full abstract»

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  • Data path synthesis for easy testability

    Publication Year: 1994, Page(s):317 - 322
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    Synthesizing digital circuits which can be easily tested is an important and necessary aspect of a useful behavioral synthesis system. Testability at behavioral level can be enhanced by minimizing the number of self-adjacent registers (self-loops). This paper describes a technique for synthesizing an easy testable (loop-free) data path structure from a behavioral description of a design. The synth... View full abstract»

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  • A diagnostic network for massively parallel processing systems

    Publication Year: 1994, Page(s):348 - 353
    Cited by:  Papers (2)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    Massively parallel processing systems consist of a large number of processing nodes to provide high performance primarily for data-intensive applications. In a system of such dimensions high availability cannot be achieved without relying on redundancy and reconfiguration. An important aspect of highly available design is rapid diagnosis and graceful degradation in the event of a failure. This pap... View full abstract»

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  • On the performance analysis of parallel processing for test generation

    Publication Year: 1994, Page(s):69 - 74
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    The performance of parallel processing for test generation depends on the method of communication among processors. This paper presents two types of parallel processing which differ in communication methods, and analyzes their performance. We formulate the number of test vectors obtained in parallel processing, and analyze the costs of test generation, fault simulation and interprocessor communica... View full abstract»

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  • Random test input generation for supply current testing of TTL combinational circuits

    Publication Year: 1994, Page(s):132 - 137
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB)

    In this paper, a random test generation algorithm for supply current testing of TTL combinational circuits is proposed. In this method, by inserting equivalent faults first in the direction from the primary output ports to the primary input ports, the total number of fault simulations can be decreased. In this paper it is shown that test input vector can be derived more quickly by means of the alg... View full abstract»

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  • Characteristics of a fuzzy test system

    Publication Year: 1994, Page(s):379 - 384
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    Stable outgoing quality is assured by using a test system with a fuzzy controller, even when sudden changes of incoming quality occur. Non test is automatically selected, when incoming quality becomes far better than a target quality. The author studies how to check the stability condition of the fuzzy test system. The condition is that the value, the sample size at the t-th test divided by the si... View full abstract»

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  • A genetic approach to test generation for logic circuits

    Publication Year: 1994, Page(s):101 - 106
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (396 KB)

    This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic app... View full abstract»

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  • A unified method for assembling global test schedules

    Publication Year: 1994, Page(s):268 - 273
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (496 KB)

    In order to make a register transfer structure testable, it is usually divided into functional blocks that can be tested independently by various test methods. The test patterns are shifted in or generated autonomously at the inputs of each block. The test responses of a block are compacted or observed at its output register. In this paper a unified method for assembling all the single tests to a ... View full abstract»

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  • Two techniques for minimizing power dissipation in scan circuits during test application

    Publication Year: 1994, Page(s):324 - 329
    Cited by:  Papers (44)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed. Problems required to exploit these techniques are defined. They are shown to be intractable. Heuristics required to exploit the proposed techniques are discussed. Experimental results are presented View full abstract»

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  • Strongly fail-safe interfaces based on concurrent checking

    Publication Year: 1994, Page(s):45 - 50
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (552 KB)

    This paper presents a strongly fail safe interface which transforms binary signals, generated by a system with error detection capabilities and eventually with fault tolerant capabilities, into fail safe signals. That is to say into signals which in the presence of failures will be either correct or safe. The strongly fail-safe property is achieved by means of concurrent checking techniques. The i... View full abstract»

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  • Fault diagnosis technique for subranging ADCs

    Publication Year: 1994, Page(s):367 - 372
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    This paper describes a fault diagnosis technique for subranging analog to digital converters (ADCs). Functional fault in each of the analog component in the subranging ADC affects the transfer function differently. This property is employed for fault diagnosis. Deviation from ideal of the transfer function which is categorized into offset error, gain error, DNL, and INL data, are used for fault di... View full abstract»

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  • Gate-level design diagnosis using a learning-based search strategy

    Publication Year: 1994, Page(s):255 - 260
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB)

    We propose a procedure for performing design error diagnosis at the gate level. The procedure is applicable to circuits having size parameters. It is based on the search strategy INCREDYBLE introduced before. The unique features of this procedure are that its performance does not deteriorate with circuit size, and that it is able to correct large numbers of errors present in the circuit at the sam... View full abstract»

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  • Design and evaluation of fault-tolerant interleaved memory systems

    Publication Year: 1994, Page(s):354 - 359
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    A highly reliable interleaved memory system for uniprocessor and multiprocessor computer architectures is presented. The memory system is divided into groups. Each group consists of several banks and furthermore, each bank has several memory units. Spare memory units as well as spare banks are incorporated in the system to enhance reliability. Reliability figures are derived to evaluate systems wi... View full abstract»

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  • Easily testable realizations for generalized Reed-Muller expressions

    Publication Year: 1994, Page(s):157 - 162
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (448 KB)

    This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and Saluja-Reddy's methods, and has the following features: 1) The network consists of a literal part, an AND part, an EXOR part, and a check part; 2) The EXOR part can be a tree instead of a cascade. Thus, the network is faster; 3) The network uses generalized Reed-Muller expressions (GRMs) ins... View full abstract»

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  • A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio

    Publication Year: 1994, Page(s):170 - 175
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    In order to simulate the effects of a bridging fault it is necessary to accurately determine the intermediate voltage of the shorted nodes and compare it to the logic threshold voltage of the driven gates. This paper presents a general model called “the configuration ratio model” which can be used to determine if a particular structure of transistors gives an intermediate voltage which... View full abstract»

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  • An efficient logical fault diagnosis for combinational circuits using stuck-at fault simulation

    Publication Year: 1994, Page(s):76 - 81
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    A new efficient method to diagnose faults in a gate or function block is proposed. This method can localize a single logic function fault, which is caused by internal stuck-at, short or open faults in the gate or function block, by using stuck-at fault simulation. Since a practical fault diagnostic system is now under development the effectiveness of the method is demonstrated by experimental resu... View full abstract»

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  • A built-in IDDQ test circuit utilizing upper and lower limits

    Publication Year: 1994, Page(s):138 - 143
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    A test circuit for the built-in IDDQ testing is proposed. The circuit can use two current values, an upper limit and a lower limit, to judge whether CUT is fault-free or not. The test circuit is applicable to fault detection for both digital and analog circuits. We show the efficiency of the test circuit using SPICE3 simulator View full abstract»

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  • To verify manufacturing yield by testing

    Publication Year: 1994, Page(s):385 - 390
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    The effect of test errors should be cancelled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the... View full abstract»

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