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Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on

Date 2-6 May 1994

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  • Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing

    Publication Year: 1994
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    Freely Available from IEEE
  • RETRAN: a recurrent paradigm for massively parallel array computing

    Publication Year: 1994 , Page(s): 478 - 487
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    An applicative paradigm of parallel array processing based on recurrence relations and a data-parallel overloading of constants is presented. It is shown that the suggested principle of anti-currying together with introduction of function-based, eager arrays result in a denotational system superior to array extensions of pragmatic languages in that it can exploit spatial symmetries of arrays to unify the notation. The main novelty here is completely asynchronous treatment of arrays of arrow types (arrays of possibly array-valued functions) which lends itself nicely to a massively parallel data-flow implementation with yet static scheduling due to the imposed strictness of the array constructor. The evolution of data is defined in the tradition form of stream transformation View full abstract»

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  • Massively parallel computing systems with real time constraints: the “Algorithm Architecture Adequation” methodology

    Publication Year: 1994 , Page(s): 44 - 53
    Cited by:  Papers (14)
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    Massively Parallel Computing Systems (MPCS) provide high performance computing generally used to accelerate numerical computation applications. We present a methodology called “Algorithm Architecture Adequation” used to take advantage of the computation power of these systems in the case of real-time applications. With this methodology, the application algorithm as well as the MPCS are specified with graphs, then the implementation of an algorithm on a MPCS in respect with real-time constraints may be formalized in terms of graph transformations. This allows one to optimize the real-time performances of the implementation taking into account critical inter-processor communications. As a result, real-time distributed executives are produced automatically without dead-lock and with minimum overhead. This reduces drastically the development cycle for real-time applications running on MPCS View full abstract»

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  • Dynamic partitioning of large multicomputer systems

    Publication Year: 1994 , Page(s): 413 - 417
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    We consider multiprogramming operation in large scale grid-connected multicomputer systems where the grid is spatially partitioned among the programs. We regard the problem as a two-dimensional resource allocation problem for which different algorithms are proposed. Results from simulation experiments indicate the performance that can be achieved in terms of fragmentation and throughput View full abstract»

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  • Systolic-type implementation of matrix computations based on the Faddeev algorithm

    Publication Year: 1994 , Page(s): 31 - 42
    Cited by:  Papers (1)
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    Deals with the problem of enhancing the versatility of VLSI processor arrays without undue addition of hardware, time/control overhead, and software complexity. A promising approach to this problem is based on matrix computations carried out through the Faddeev algorithm. We design a fixed-size, linear array architecture with fully local communications and straightforward control requirements. This high-throughput, systolic-type architecture allows us to minimize both I/O requirements and the number of processing elements performing complicated operations like divisions. To derive the array from a formal description of the Faddeev algorithm based on Gaussian elimination with partial pivoting, we use purposive transformations of the basic dependence graph of the algorithm before its space-time mappings onto array architectures View full abstract»

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  • A dynamic analysis system for textured images using multiprocessors

    Publication Year: 1994 , Page(s): 375 - 381
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    Vision computing involves the execution of a large number of operations on large sets of structured data. The need for very high speed processing in image processing means parallel architectural solutions have to be explored. In this paper we propose the development of a dynamic texture analysis system using a multiprocessor system MEAP. The project is aimed to recognize and delineate the texture of image regions with robustness and reliability at less computation cost. Based on the successful prototype texture analysis system previously implemented sequentially by us, the system is expected to be flexible for parallel extension with a multiprocessor. The dynamic approach detailed involves a mask tuning scheme for the establishment of a rotational and scale invariant texture classification system in parallel View full abstract»

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  • On scientific research, applications software development, and industrial use of massively parallel computing systems

    Publication Year: 1994 , Page(s): 217 - 219
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    A healthy massively parallel computing system industry requires a well-defined market for their products. The market for massively parallel computing systems has remained stubbornly ill-defined for at least a decade. The primary reason for this is that industrial corporations have not been able to measure value in the new computing technology, due to the absence of commercially supported application software packages for these systems. It is essential for the well-being of everyone engaged in massively parallel computing, from research institutions to industrial end users, and particularly the computer builders themselves, that ways be found to ameliorate this state of affairs. This paper analyses the situation, and proposes some procedures whose implementation would ease the transfer of newly developed application technologies from research groups into the hands of end users, who can then employ massively parallel computers to solve practical industrial problems View full abstract»

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  • A routing strategy for WK-networks

    Publication Year: 1994 , Page(s): 576 - 582
    Cited by:  Papers (4)
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    A requirement for new multicomputers is the decoupling of computation and communication functionalities in order to improve the performance of both. The choice of an interconnection network and the routing strategy adopted define the internal architecture of the communication node. The paper presents a new routing strategy for WK-networks, based on two separate networks for the input and output phases, which enables a cost effective communication node to be designed View full abstract»

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  • Symbolic computing, Lisp languages, and parallel computing

    Publication Year: 1994 , Page(s): 542 - 553
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    In this paper we review symbolic parallel programming issues. We start describing the peculiarities of symbolic programming. Next, we review the standard parallel programming framework for the imperative-like languages. Also the autoscheduling environment, proposed by Polychronopoulos (1990), is introduced. The current extensions for symbolic parallel programming are described. The problem how to efficiently manage the parallelism in LISP is addressed, and the Hierarchical Task Graph, an intermediate program representation in which the parallelism is expressed by the task hierarchy, and the associated run-time model are also described. The extensions necessary to manage the parallelism at run-time in a multiprogramming environment are described View full abstract»

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  • Process migration protocols for massively parallel systems

    Publication Year: 1994 , Page(s): 84 - 95
    Cited by:  Papers (1)  |  Patents (1)
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    Process migration is known as the run time relocation of a process within a network of processors. This capability is mainly used for efficient management of resources in a distributed system. This paper deals with the construction of process migration mechanisms for Massively Parallel Systems (MPS). In particular, we are interested in the correction of communications in presence of migration. Many distributed systems have proposed mechanisms for process migration where different approaches are used to ensure transparency and correctness of the delivery of messages. In MPS, more than achieving correctness and transparency, the emphasis is put also on supporting scalability of the machine architecture, and on efficiency by minimising the overhead introduced by the use of the migration mechanisms at run-time. According to these criteria we propose three migration protocols for correct message passing mechanisms View full abstract»

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  • A parallel symbolic language for vision analysis

    Publication Year: 1994 , Page(s): 518 - 522
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    In this paper we describe the design criteria for a Parallel Symbolic Language for Vision Analysis. The essential feature of a such language is the use of the notion of structured parallelism in order to capture all the forms of parallelism used in vision analysis. After introducing the need for Symbolic Parallel languages for the vision analysis, we show how PARALATION LISP can be extended to manage it in a user transparent way. Then, we describe the design criteria used for our Parallel Symbolic Vision Analysis Language project and the current implementation status View full abstract»

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  • Performance optimization on low-cost cellular array processors

    Publication Year: 1994 , Page(s): 334 - 338
    Cited by:  Papers (4)
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    A massively parallel architecture is composed of a high number of processing elements (PE), but seldom a 1:1 mapping between the PEs and the data set can be achieved. To overcome this problem, a processor virtualization mechanism is needed. This work provides a theoretical study on performance optimization in the specific virtualization process used when a small amount of memory is associated to each PE. Moreover, this paper presents an algorithm for performance optimization and for the determination of the maximum processing speed on low-cost cellular array processors implementing the above mentioned visualization mechanism. These considerations are then used to improve the execution of morphological image processing tasks on the first hardware prototype of the special-purpose cellular array processor PAPRICA View full abstract»

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  • The Paprica massively parallel processor

    Publication Year: 1994 , Page(s): 16 - 30
    Cited by:  Papers (9)  |  Patents (1)
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    This paper describes a complete 6-year project, starting from its theoretical basis up to the hardware and software system implementation, and to the description of its future evolution. The main goal of the project is to develop a subsystem that operates as a processing unit attached to a standard workstation and in perspective as a low-cost low-sized specialized embedded system devoted to low level image analyses and cellular neural networks emulation. The architecture has been extensively used for basic low level image analysis tasks up to optical flow computation and feature tracking, showing encouraging performances even in the first prototype version View full abstract»

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  • Modelling of computer architectures

    Publication Year: 1994 , Page(s): 434 - 442
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    The goal of this article is to present a general theoretical framework for modelling the logical and physical structures underlying computer architectures. The reasoning is based on general system theory and the mathematical theory of constructive computation. Fundamental are discrete functional systems, their partitions, and algorithms on them. For modelling processes in general “time sets” are introduced and the mutual dependences of processes are discussed. In correspondence to the mathematical objects considered, a model of physical computational systems is given. From this a whole range of architectural concepts can be derived View full abstract»

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  • A data parallel approach to Boolean function manipulation using BDDs

    Publication Year: 1994 , Page(s): 163 - 175
    Cited by:  Papers (2)
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    The paper describes an Electronic CAD package exploiting the CM-200 architecture to manipulate boolean functions. The package exploits Binary Decision Diagrams (BDDs) to symbolically operate with boolean functions. The data parallel approach is based on distributing BDD nodes do the available Processing Elements and traversing BDDs in a breadth-first manner. The behaviour of the algorithm is studied and the results which have been obtained obtained for an application developed with the package are reported. They show that the approach exploits well the parallel hardware and is highly scalable; if implemented on state-of-the-art and fully configured systems, it could solve problems which can not be faced with conventional architectures View full abstract»

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  • Communications is more than I/O

    Publication Year: 1994 , Page(s): 2 - 5
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    For the purposes of this paper, it is my premise that hardware is not the problem for the acceptance and utilization of massively parallel computing. If hardware is not the problem, what is? The answer has to be software and a deeper understanding of parallel algorithms. However, I believe that software has to be different if massively parallel computing is to be a major factor in computing in the future. And to become so, we must make major shifts in software to facilitate this development. I present my views on appropriate software for massively parallel computing environments. Before outlining possible directions for future development, I review where we have come from View full abstract»

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  • Massively parallel-processing system with 3D-Flow processors

    Publication Year: 1994 , Page(s): 355 - 369
    Cited by:  Papers (5)
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    The 3D-Flow is a massively parallel-processing system. Its main advantages are embodied in its architecture: the system (integrated and standardized), the assembly (modular with maximum connectivity), and the processor (programmable, powerful and fast). The combination of this architecture with a simple, high-speed processor that has several units working in parallel, with its 10 very-high-speed communication parallel ports in six directions, and the ability to operate the processor in Single Instruction Multiple Data (SIMD), or in Multiple Instruction Multiple Data (MIMD) modes, allows one to build a very versatile engine. This engine is capable of solving at very high speed with a very high degree of interconnectivity a very long algorithm (in SIMD mode), or it can perform digital filtering on high-frequency signals or pattern recognition in a very short time, using a short algorithm that can be different on each processor (in MIMD mode). The overall 3D-Flow project has passed a major design review at Fermilab. (Reviewers included experts in computers, triggering, system assembly, and electronics.) View full abstract»

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  • Supports for performance evaluation in heterogeneous distributed environments

    Publication Year: 1994 , Page(s): 570 - 575
    Cited by:  Patents (1)
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    In heterogeneous environments, very sophisticated modelling techniques and tools are required for the analysis of interactions between hardware and software subsystems. After a detailed discussion about performance evaluation of heterogeneous systems, an online monitoring tool for heterogeneous distributed systems is presented. Portability, modularity and a powerful graphic interface are the main features of the developed tool View full abstract»

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  • Technology against vision architectures

    Publication Year: 1994 , Page(s): 239 - 257
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    Understanding what the problems are in robot-vision architecture, requires a better comparison of major features. But a zoology of vision machines is questioned when, aiming for a well informed architectural feature choice, a rapid presentation of technological trends in the field is proposed. Then an approach closer to physics prompts to a classification from a control point of view: it reveals some duality between operations and communications. A few visual operations are distinguished provided technology is not trailing behind. But emphasis should be put on communication networks, although they do not show any image processing specificity currently, and the conclusion addresses some limits in that respect View full abstract»

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  • Pipelined microprocessor-based architecture: on-the-fly processing

    Publication Year: 1994 , Page(s): 196 - 200
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    This paper presents a new pipelined microprocessor-based architecture (PMA) using On-The Fly processing. The effectiveness of the PMA has been investigated for several applications such as database operations and very large databases using WORM (Write-Once-Read-Many) optical disk technology. In this paper, a pipelined information retrieval algorithm and a pipelined join algorithm are presented and their complexities are analyzed. Extensive simulations of these algorithms have been conducted on an emulated PMA on an AT&T parallel machine. Parallel implementations of these algorithms have been also considered for comparison purposes View full abstract»

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  • Tr-machine architecture

    Publication Year: 1994 , Page(s): 191 - 195
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    In this paper we describe a new parallel computer architecture called Tr-machine. Tr-machine instruction set architecture combines reduction with traditional approaches. The architecture uses two types of processing units and a tree structured organized as a balanced tree. The leaf nodes are called C-nodes and they perform the computation. The internal nodes are called S-nodes. The S-nodes facilitate communication and keep track of different parallel computations View full abstract»

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  • General purpose massively parallel systems: the role of programming environments

    Publication Year: 1994 , Page(s): 584 - 598
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    One of the key obstacles to the widespread adoption of massively parallel computers is the lack of programming environments to support the development of software that can achieve both portability and high performance. The paper discusses alternative methodologies to define static and dynamic tools of this environment. While the main problems posed by a static tool are input dependant behaviour and the definition of a formal and abstract representation of the user program, dynamic tools introduce overhead to collect data about the program behaviour to drive their policy. Proper integration between the two kinds of tools is fundamental to be able to select the most appropriate solution for a given program. The definition and the design of these tools can be largely simplified through the introduction of a virtual machine to be mapped onto different physical machines and that enables the development of software tools and applications that can be ported across different machines View full abstract»

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  • Conditional and iterative structures using a homogeneous static dataflow graph model

    Publication Year: 1994 , Page(s): 391 - 401
    Cited by:  Patents (1)
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    This paper presents a static dataflow graph model, where only data tokens are allowed to flow. The proposed model is formally described, and the dataflow graph is obtained by employing only actors with homogeneous I/O conditions. Each actor, which executes an elemental operation, is characterized by having one output and two input arcs. Even though no control tokens are allowed, so that no T-gate, merge, and switch actors are present in this model, it is always possible to represent conditional and iterative structures whose behavior is well-behaved. As homogeneous I/O conditions are a severe restriction to represent the flow of a computation and the token flow in such dataflow graphs is completely asynchronous, proof is given to guarantee their determinacy View full abstract»

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  • Experimental evaluation of affine schedules for matrix multiplication on the MasPar architecture

    Publication Year: 1994 , Page(s): 452 - 459
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    This paper reports an experimental study on the suitability of systolic algorithm scheduling methods to the automatic parallelization of algorithms on SIMD computers. We consider the matrix multiplication on the MasPar MP-1 architecture. We comparatively study different scheduling methods and the blocking of the best resulting algorithms View full abstract»

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  • Optimal triple modular redundancy embeddings in the hypercube

    Publication Year: 1994 , Page(s): 600 - 610
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    To achieve reliability without sacrificing performance, the tasks of a computation are redundantly assigned to the processors of a hypercube multiprocessor. The computation is represented by a task interaction graph in which nodes represent tasks, and edge weights represent the amount of communication between tasks. To provide fault tolerance, each node in the graph is replaced by three nodes that act together as a triple modular redundancy (TMR) unit. We develop a formula to calculate the number of TMR units that can be supported in an n-dimensional hypercube, and a formula to calculate the distance between true TMR units. Then we give algorithms for TMR embeddings of weighted 1-level k-ary trees and unweighted rings in a hypercube. These algorithms minimize expansion, and are optimal in that they minimize dilation for a given expansion View full abstract»

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