Scheduled Maintenance on March 25th, 2017:
Single article purchases and IEEE account management will be unavailable from 4:00 AM until 6:30 PM (ET). We apologize for the inconvenience.
By Topic

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

11-15 Nov. 1990

Filter Results

Displaying Results 1 - 25 of 125
  • A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays

    Publication Year: 1990, Page(s):2 - 5
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB)

    A novel approach is analyzed for reconfiguring multipipeline arrays from two-dimensional arrays. The proposed approach is fully characterized and the conditions for switching and routing are given. A polynomial time complexity algorithm is proposed for the reconfiguration of multipipeline arrays. It is proved that 100% harvesting is possible using the proposed algorithm while achieving very small ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Topological routing using geometric information

    Publication Year: 1990, Page(s):6 - 9
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB)

    A novel method is proposed for the two-layer topological channel routing problem. The authors' algorithm takes geometric information into consideration when a topological solution is obtained. Experimental results show that the algorithm generates very good solutions. For example, the authors have obtained a height of 41 for Deutsch's difficult example without any parallel overlaps of wires while ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An optimal channel pin assignment algorithm

    Publication Year: 1990, Page(s):10 - 13
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB)

    A study is made of the channel pin assignment problem subject to both position and order constraints. The authors show that the problem is NP-hard in general and present a polynomial time optimal algorithm for an important case where the relative orderings of the terminals are completely fixed. They extend their algorithm to solve the problem for the case where there are also separation constraint... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constraint identification for timing verification

    Publication Year: 1990, Page(s):16 - 19
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Race detection for two-phase systems

    Publication Year: 1990, Page(s):20 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB)

    The authors present RACE2, a tool to find latch race-through in two-phase, non-underlapped-clock systems. Though these systems can run at very high clock speeds, susceptibility to race-through has made them difficult to design. RACE2, by detecting all race-through violations, greatly reduces the design risk on these very fast systems. It combines the exhaustive search of a pattern-independent tool... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Timing constraints for correct performance

    Publication Year: 1990, Page(s):24 - 27
    Cited by:  Papers (24)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB)

    Novel methodology and algorithms for the derivation of timing constraints on all the interconnects were developed and applied to solving layout related timing problems. This methodology is based on detailed information on timing characteristics of cells and nets. A minimax approach for identifying maximal delay bounds for nets which do not violate the timing constraints on any of the logical paths... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An automata-theoretic approach to behavioral equivalence

    Publication Year: 1990, Page(s):30 - 33
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB)

    The problem of verifying the equivalence of a behavioral description against a logic-level implementation is addressed. One major hindrance toward a precise notion of behavioral verification has been that parallel, serial or pipelined implementations of the same behavioral description can be implemented in finite-state automata with different input/output behaviors. The authors use nondeterminism ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Tautology checking using cross-controllability and cross-observability relations

    Publication Year: 1990, Page(s):34 - 37
    Cited by:  Papers (19)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB)

    A novel method is described for verifying the equivalence between a combinational circuit and its specification, when both are given in a modular (e.g., factored) form. It is based on the notion of cross-controllability and cross-observability relations that exist between the internal logic values across a cut of the joint composition of the circuit and the specification. It is proven that even af... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

    Publication Year: 1990, Page(s):38 - 41
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB)

    Automatic and semi-automatic verification methods for switch-level circuits are presented. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a formalism with binary decision diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the unifo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new global router based on a flow model and linear assignment

    Publication Year: 1990, Page(s):44 - 47
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB)

    A novel heuristic for global routing in graphs is developed. Based on a flow model it can handle many nets simultaneously, thus reducing the net ordering problem. To demonstrate the validity of the method it was applied to standard cell design style. For this application the authors combined the flow model approach with linear assignment to achieve a hierarchical global routing scheme. This proced... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A timing-driven global router for custom chip design

    Publication Year: 1990, Page(s):48 - 51
    Cited by:  Papers (32)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB)

    A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous ste... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rubber band routing and dynamic data representation

    Publication Year: 1990, Page(s):52 - 55
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A novel methodology and efficient algorithms are presented for performance driven routing based on computational geometry. A dynamic data representation using constrained triangulation is the key to achieving the efficient routability testing and incremental updating of topological routing. Variable width, variable spacing, evenly distributed spacing and thermal via insertion are used to handle cr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Touch and cross router

    Publication Year: 1990, Page(s):56 - 59
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB)

    A novel general routing algorithm is presented. Each net is routed to minimize the cost function defined by a weighted sum of penalties. Two types of design rule violations, touches and crosses, are factors of the cost function. Using these violations enables the algorithm to achieve 100% completion even when routing problems have nets which must be considered simultaneously. This type of problem ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Exploitation of periodicity in logic simulation of synchronous circuits

    Publication Year: 1990, Page(s):62 - 65
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. A general technique is presented which takes advantage ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SNEL: a switch-level simulator using multiple levels of functional abstraction

    Publication Year: 1990, Page(s):66 - 69
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (422 KB)

    A novel switch-level simulator, called SNEL, is presented. The SNEL simulator preprocesses the circuit description to abstract its functionality prior to simulation. Functional abstraction is concisely defined in terms of the functional domain and the functional application of circuit constructs. SNEL uses four algorithms that operate on levels ranging from single circuit elements to multiple DC-c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of the parallel technique for compiled unit-delay simulation

    Publication Year: 1990, Page(s):70 - 73
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB)

    The parallel technique is a purely compiled method for unit-delay simulation that is based on levelized compiled simulation and bit parallel simulation. The parallel technique provides rapid simulations with a reasonable amount of code, but there are opportunities for optimization. The author presents two schemes: bit-field trimming and shift-elimination. Performance results are presented that dem... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast switch-level fault simulation using functional fault modeling

    Publication Year: 1990, Page(s):74 - 77
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB)

    A novel switch-level fault simulation method is presented for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling. The simulator models both node stuck-at-zero, stuck-at-one faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An algorithm for nearly-minimal collapsing of finite-state machine networks

    Publication Year: 1990, Page(s):80 - 83
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (313 KB)

    An algorithm is presented which simultaneously generates the Cartesian product of a network of finite-state machines and minimizes the resulting product machine. The algorithm can generate collapsed machines, removing a large set of redundant states on the fly, in CPU times comparable to the time required for simple Cartesian product collapsing. The algorithm makes it practical to generate and ana... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implicit state transition graphs: applications to sequential logic synthesis and test

    Publication Year: 1990, Page(s):84 - 87
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    Implicit state enumeration is used in developing strategies to solve key problems in sequential logic synthesis and test. It is shown that it is possible to extract implicit state transition graphs (ISTGs) from logic-gate and flip-flop descriptions of sequential circuits that allow equivalent states to be represented by cubes, and edges from different states to be coalesced into one, thereby decre... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimization of symbolic relations

    Publication Year: 1990, Page(s):88 - 91
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB)

    The problem of minimizing symbolic relations is addressed. The relevance of this problem in the field of optimal encoding is shown by examples. A binate covering formulation of the optimization problems involved is given, for which several algorithms are available. A novel method is proposed which is based on binary decision diagrams (BDDs) and the authors show how the covering problem can be solv... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithms for discrete function manipulation

    Publication Year: 1990, Page(s):92 - 95
    Cited by:  Papers (88)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (423 KB)

    An investigation was made of the analogous graph structure for representing and manipulating discrete variable problems. The authors define the multi-valued decision diagram (MDD), analyze its properties (in particular prove a strong canonical form) and provide algorithms for combining and manipulating MDDs. They give a method for mapping an MDD into an equivalent BDD (binary decision diagram) whi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floorplanning with pin assignment

    Publication Year: 1990, Page(s):98 - 101
    Cited by:  Papers (10)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB)

    A hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diffusion-an analytic procedure applied to macro cell placement

    Publication Year: 1990, Page(s):102 - 105
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB)

    A description is presented of a novel optimization procedure called diffusion which can be used in global circuit placement for suppressing inter-module and module-to-chip boundary overlaps. A salient feature of the proposed diffusion procedure is that multiple decisions on the moves of all variables (module positions) are simultaneously made such that a global, analytic objective function is mini... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floorplanning by topological constraint reduction

    Publication Year: 1990, Page(s):106 - 109
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB)

    The problem considered is that of producing a legal floorplan that respects a given topological constraint set. The floorplanning approach described is targeted for multilayer sea-of-cells based designs. Therefore it is assumed that no channel separations are required between the blocks. The approach can be generalized to incorporate channel separations.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design for circuit quality: yield maximization, minimax, and Taguchi approach

    Publication Year: 1990, Page(s):112 - 115
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A relationship between yield optimization, deterministic minimax design, and the Taguchi 'on-target' design with variability reduction is established. It is shown that all these and other design approaches can be combined into one coherent methodology, using the same statistical optimization algorithms and the same generic gradient evaluation formulas. A specific choice is controlled by the select... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.