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Proceedings of the European Design Automation Conference, 1990., EDAC.

12-15 March 1990

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Displaying Results 1 - 25 of 121
  • EDAC. Proceedings of the European Design Automation Conference

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (308 KB)
    Freely Available from IEEE
  • Transmission gate delay models for circuit optimization

    Publication Year: 1990, Page(s):558 - 562
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Accurate macromodels for CMOS transmission gates are presented. Signal delay, area consumption and power dissipation are determined by a few technology dependent parameters. Different transistor widths, input waveforms and varying loading conditions are considered. The calculated delay times of CMOS circuits including transmission gates differ only 10 percent when compared with SPICE results. The ... View full abstract»

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  • Multirate integration in a direct simulation method

    Publication Year: 1990, Page(s):306 - 309
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Multirate integration is a technique in which a set of differential equations is solved with different timesteps assigned to subsets of equations. In circuit simulation this is commonly used in the waveform relaxation method, where different subcircuits are analyzed independently from the others. An important and obvious advantage is the simulation efficiency: subcircuits which are temporarily cha... View full abstract»

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  • An accurate model for ambiguity delay simulation

    Publication Year: 1990, Page(s):563 - 567
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    This paper presents a new approach for the accurate computation of ambiguously delayed waveforms which is implemented in the event-driven logic simulation system LDSIM. Six logic values are defined to be sets of up to four basic values. The mapping function representing the ambiguity delay model only manipulates these basic values. This principle results in a powerful and versatile ambiguity delay... View full abstract»

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  • Derivation of signal flow for switch-level simulation

    Publication Year: 1990, Page(s):301 - 305
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper presents a new algorithm for deriving the direction of signal flow in MOS circuits. The algorithm detects so-called unidirectional transistors. In a unidirectional transistor, signal flow is restricted to one direction during switch-level simulation, without compromising the simulation results. The algorithm uses a static analysis of the switch-level characteristics of the circuit, such... View full abstract»

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  • An architecture for synthesis of testable finite state machines

    Publication Year: 1990, Page(s):612 - 616
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The authors present a hardware architecture for synthesizing finite state machines (FSM). This architecture is defined at the level of the state transition graph. It contains a test machine with the same number of state variables as the object machine to be synthesized. The state graph of the test machine is so defined that each state is uniquely set and observed by an input sequence no longer tha... View full abstract»

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  • An object-oriented persistent database interface for CAD

    Publication Year: 1990, Page(s):363 - 367
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Much activity in the database community is focused on providing database support to the application programmer in a user-friendly environment that improves productivity and encourages software re-use. Object-oriented and persistent programming are two emerging paradigms that are considered essential to create such an environment. One approach is to converge programming languages and databases to a... View full abstract»

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  • An incremental functional simulator implemented on a network of transputers

    Publication Year: 1990, Page(s):296 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper describes the organisation of a concurrent functional simulator employing transputers which gives considerably improved performance over conventional simulators. The parallel organisation allows a novel feature, incremental simulation, to be provided which allows the simulator to respond very quickly to design changes thereby allowing the design to proceed with the minimum of delay. The... View full abstract»

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  • Solution of a module orientation and rotation problem

    Publication Year: 1990, Page(s):584 - 588
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors study a module orientation and rotation problem. They assume that a set of rectangular modules has been placed according to proximity requirements while they still have the freedom to choose the orientation of the modules, to rotate the modules, and to shift the pins along the boundary of each module. They propose a fast heuristic algorithm to solve the problem, minimising the total le... View full abstract»

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  • NAUTILE: a safe environment for silicon compilation

    Publication Year: 1990, Page(s):605 - 609
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper deals with an environment for IC's layout, to act as a framework for the design of module generators for behavioral silicon compilation. It is built around an object oriented data manager that handles hierarchical design, and multiple representations, with emphasis on a safe design methodology. This manager also allows the use of externally defined elements, and the integration of tools... View full abstract»

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  • A data-structuring technique for gridded VLSI layouts

    Publication Year: 1990, Page(s):356 - 362
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper presents the linked array data structure for storing rectangular structures which are constrained to a grid. The data structure is particularly useful in integrated layout systems for VLSI technologies like gate-arrays; it is also useful for building schematic editors. This data structure has been used to implement a prototype layout system which has significant memory usage and timing ... View full abstract»

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  • A new method for the state reduction of incompletely specified finite sequential machines

    Publication Year: 1990, Page(s):552 - 556
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A new method for the state reduction of incompletely specified finite sequential machines is proposed. Fundamental theorem of minimization theory states that, given an incomplete state table, another state table specifying the same external behavior corresponds to each closed set of compatibility classes which covers all internal states of the given table. The new heuristic algorithm builds up a c... View full abstract»

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  • An efficient two-dimensional compaction algorithm for VLSI symbolic layout

    Publication Year: 1990, Page(s):196 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The 2-dimensional compaction problem for VLSI symbolic layout is considered. Through carefully arranging the constraints among the elements which are represented as rectangles and the compaction strategies including the basic 2-dimensional compaction and the jog, the goal to compact the layout so that its bounding rectangle has a minimum or an approximately minimum area, is achieved. A systematica... View full abstract»

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  • The EVE companion simulator

    Publication Year: 1990, Page(s):290 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    This paper describes the EVE companion simulator, ECS, a four-valued gate level simulator which compliments a simulation methodology that uses the engineering verification engine, EVE. ECS is, like EVE, a zero- and unit-delay cycle simulator, but unlike EVE, ECS is a software simulator which runs on a general purpose computer. The basic simulation paradigm of ECS is event driven to exploit latency... View full abstract»

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  • Event-driven behavioural simulation of analogue transfer functions

    Publication Year: 1990, Page(s):240 - 243
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A method is proposed for simulating analogue circuits, represented by their transfer functions, in an event-driven simulator. Analogue waveforms may be voltage or current, and are represented by a piecewise linear approximate. A novel timestep control technique is presented, whereby individual models maintain this approximation within tolerances, permitting different timesteps in different parts o... View full abstract»

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  • Design to test migration; a tester and a simulator

    Publication Year: 1990, Page(s):578 - 582
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Discusses the advantages of a good migration route from design data to test data. A good route can be established by embedding a design simulator into a test-preparation system, but development of the test-preparation software involves significant engineering work including a close examination of the simulator's interfaces. The test-preparation simulator can then be made available to designers so ... View full abstract»

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  • A dynamic programming approach to the power supply net sizing problem

    Publication Year: 1990, Page(s):600 - 604
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    The author presents a simple dynamic programming approach to find minimum area sizings of power supply nets in VLSI circuits in time O((ΔA)2n), where n is the number of modules and ΔA is the difference between an upper bound of the area and the lower bound resulting from minimum feature size and electromigration constraints. In opposition to known algorithms from literature,... View full abstract»

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  • Fault modelling and fault equivalence in CMOS technology

    Publication Year: 1990, Page(s):407 - 412
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The need of greater confidence for fault coverage of test sequences for VLSI circuits has led to the proposal of more accurate fault models and test pattern generation tools. Such improvement induces a large increase in fault list to be considered and CPU time to generate test. The authors propose a complete methodology to obtain a minimal set of faults. This methodology is based upon theoretical ... View full abstract»

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  • Diagnosis oriented test pattern generation

    Publication Year: 1990, Page(s):470 - 474
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper addresses the generation of test patterns having diagnostic properties. The authors goal is to produce patterns able not only to detect, but also to distinguish faults in combinational circuits. A general formalization of the problem is first given; a new technique is then introduced to improve the diagnostic capabilities of a traditional automatic test pattern generation (ATPG); the ex... View full abstract»

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  • Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring

    Publication Year: 1990, Page(s):350 - 354
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Current monitoring is a well-established technique for detecting stuck-on and bridging faults in CMOS logic circuits. When such faults are activated by an appropriate vector, the circuit draws current which is much larger than normal and the fault is detected. The authors first show that any test set, which detects all single stuck-at faults in any irredundant combinational CMOS logic circuit, als... View full abstract»

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  • An improved layout verification algorithm (LAVA)

    Publication Year: 1990, Page(s):391 - 395
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The correctness of a VLSI circuit layout can be verified by comparing the netlist extracted from the layout with the specification netlist. Ebeling and Zajicek (1983) showed that this problem can be solved by utilizing known techniques for solving the classical graph isomorphism problem. The authors present an improved algorithm for solving the graph isomorphism problem associated with layout veri... View full abstract»

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  • Design data management in a distributed hardware environment

    Publication Year: 1990, Page(s):34 - 38
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The article presents a database system for IC design that combines an optimal logical organization of the design data with the facilities that are offered by a distributed hardware environment which consists of processors, storage provisions and network facilities. It models the physical, logical and distributed aspects of the hardware environment, yielding an environmental schema. The logical str... View full abstract»

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  • SPI: an open interface integrating highly interactive electronic CAD tools

    Publication Year: 1990, Page(s):492 - 495
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    This paper describes the SPI interface as an interface unifying the integration of electronic CAD tools. The goal of the interface is to provide a direct communication and interactive feedback between the primary design tools (schematics editors, symbolic layout editors, module generators etc.) and intelligent verification tools (electrical debugging, timing verification, simulation etc). The SPI ... View full abstract»

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  • State assignment of controllers for optimal area implementation

    Publication Year: 1990, Page(s):547 - 551
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The state assignment of controllers presented aims at preparing further minimizations of the next-state and output logic implementation on standard cells. This is done by detecting situations in the control flowgraph leading to these further minimizations, deducing constraints on the state assignment and finding a solution on the hypercube satisfying them. The originality of this paper is to propo... View full abstract»

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  • Adaptive cluster growth (ACG); a new algorithm for circuit packing in rectilinear region

    Publication Year: 1990, Page(s):191 - 195
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A new algorithm for circuit packing (or detailed placement) in any rectilinear region called adaptive cluster growth (ACG) is described in analogy to the growth of a low-stress crystal in a cavity of any given shape. ACG is an algorithm suitable for packing of circuit modules, either standard cell or macro cell, in a rectilinear region by refining the result of global placement obtained by such te... View full abstract»

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