Proceedings of the European Design Automation Conference, 1990., EDAC.

12-15 March 1990

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Displaying Results 1 - 25 of 121
  • EDAC. Proceedings of the European Design Automation Conference

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (308 KB)
    Freely Available from IEEE
  • Transmission gate delay models for circuit optimization

    Publication Year: 1990, Page(s):558 - 562
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Accurate macromodels for CMOS transmission gates are presented. Signal delay, area consumption and power dissipation are determined by a few technology dependent parameters. Different transistor widths, input waveforms and varying loading conditions are considered. The calculated delay times of CMOS circuits including transmission gates differ only 10 percent when compared with SPICE results. The ... View full abstract»

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  • A procedural interface to CAD data based on EDIF

    Publication Year: 1990, Page(s):496 - 500
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    EDIF is a data interchange format which currently provides a solution to the problem of data transfer between proprietary CAD systems. This paper considers how a procedural interface to a CAD system may be built upon the underlying data model of EDIF. It outlines the procedural interface and describes how a novel implementation has allowed access to, and extension of, the database to be particular... View full abstract»

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  • MOLE-a sea-of-gates detailed router

    Publication Year: 1990, Page(s):446 - 450
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The authors present a new detailed router which was developed as part of a sea-of-gates layout project. It routes nets on two or more layers in a given rectangular or rectilinear region which may contain blockages and interior terminals in addition to terminals on the boundary. It uses a set of templates to perform routing and incorporates several novel features that address sea-of-gates routing i... View full abstract»

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  • SPI: an open interface integrating highly interactive electronic CAD tools

    Publication Year: 1990, Page(s):492 - 495
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    This paper describes the SPI interface as an interface unifying the integration of electronic CAD tools. The goal of the interface is to provide a direct communication and interactive feedback between the primary design tools (schematics editors, symbolic layout editors, module generators etc.) and intelligent verification tools (electrical debugging, timing verification, simulation etc). The SPI ... View full abstract»

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  • Rapid prototyping using high density interconnects

    Publication Year: 1990, Page(s):439 - 443
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper introduces the discretionary interconnect one-day electronic systems (DIODES) for the rapid prototyping of DSP electronic systems. DIODES merges silicon compiler and high-density interconnect technology with the goal of prototyping hardware systems as quickly as possible-within one day. Working from a high-level algorithmic description of a DSP algorithm, DIODES will determine which chi... View full abstract»

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  • Experience in functional-level test generation and fault coverage in a silicon compiler

    Publication Year: 1990, Page(s):485 - 490
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    During the design cycle of VLSI circuits, test vector generation is often a very time consuming and costly step. Many strategies concerning automatic test pattern generation (ATPG) have been published. Usually they are restrictive and consider the circuit as an undifferentiated mass of gates while ignoring the hierarchy used during the design process. The test vectors so generated are based on the... View full abstract»

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  • The use of computer-aided software engineering technology in systems and software design

    Publication Year: 1990, Page(s):434 - 438
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    This paper describes computer aided software engineering (CASE) technology and its use in large-scale systems and software design projects. This paper is written in the form of a tutorial and heavy use is made of real CASE and CAD design examples. The last part of this paper presents recommendations and conclusions, and explores some future ideas about the use of CASE technology for hardware and s... View full abstract»

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  • A flexible hierarchical 3-D module assembler

    Publication Year: 1990, Page(s):124 - 128
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    A module assembler based on a design philosophy that is different from work reported in the literature is presented. Most assemblers are targeted for a `correct by construction' approach. However, the design philosophy in a mostly handcrafted high performance, high density chip is that of `correct by verification'. The authors' module assembler is designed with a view to supporting highly flexible... View full abstract»

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  • A new approach to pipeline optimisation

    Publication Year: 1990, Page(s):83 - 88
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper presents a new algorithm for the generation of pipelined designs developed for use in an interactive behavioural synthesis system. The authors' technique uses a novel iterative optimisation algorithm that allows the user to trade-off interactive response time with solution quality. Two examples are given to demonstrate the effectiveness of the approach. These provide comparisons with: (... View full abstract»

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  • High level test generation using data flow descriptions

    Publication Year: 1990, Page(s):480 - 484
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    To significantly expedite the test generation process for sequential VLSI circuits, the hierarchy in the circuit descriptions should be exploited. Conventional test generators can provide tests for relatively small modules, which are typically embedded in large circuits. This paper considers test generation for complex VLSI circuits composed of many interconnected modules. In contrast to the previ... View full abstract»

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  • Logic optimization on a concurrent processing computer

    Publication Year: 1990, Page(s):429 - 433
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Optimization of combinational logic plays an important role in the automatic synthesis of integrated circuits, often called silicon compilation. The optimization program rewrites a given set of boolean expressions in such a way that, after mapping the expressions onto a set of library cells, an optimal result is obtained. This optimality can be in terms of area (number of transistors), speed, powe... View full abstract»

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  • On the notion of the normal form register-level structures and its applications in design-space exploration

    Publication Year: 1990, Page(s):46 - 51
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The notion of the normal form structural (NFS) implementation of an algorithmic behavioral specification is introduced. The NFS implementation of a behavioral specification is shown to be unique among all the register transfer (RT) level structures implementing the specification. An algorithm to transform a given structure into the equivalent normal form structure is presented. The notion of the N... View full abstract»

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  • On the fault coverage of delay fault detecting tests

    Publication Year: 1990, Page(s):334 - 338
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Existing methodologies for determining gate delay fault coverages are shown to have certain deficiencies. A new and more realistic delay model is presented with the ultimate goal of ensuring error-free circuit operation through obtaining true fault coverages that extend upto the actual slacks. Methods are given that achieve such coverages when possible. Results of experiments performed to evaluate... View full abstract»

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  • CIRCE: a program for parasitic parameter extraction

    Publication Year: 1990, Page(s):387 - 390
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Parameter extraction is one of the crucial points in the integrated circuit design process. This paper describes the features of CIRCE, a parameter extraction program, that produces an electrical description of the network having a geometrical description of the layout as input. Parasitic effects due to the intrinsic resistances of the circuit wires and to the capacitive interactions between the w... View full abstract»

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  • A VLSI floorplanner based on `balloon' expansion

    Publication Year: 1990, Page(s):257 - 261
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    A novel floorplanning method is presented that models blocks as rectangular `balloons', which are gradually expanded to determine their shapes and placement. Unlike the existing approaches, which assume the floorplan to be a slicing structure or which never handle fixed-shaped blocks, this method can handle fixed-shaped blocks as well as variable-shaped blocks on a general (non-slicing) layout str... View full abstract»

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  • Cell based performance optimization of combinational circuits

    Publication Year: 1990, Page(s):594 - 599
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Performance optimization, i.e. the problem of finding an optimal investment of transistor area which meets given delay constraints, is considered from an abstract, cell based point of view which allows only solutions within a discrete solution space of coarse granularity. The main advantages of this problem modelling are the independence of the methods from concrete delay modelling (and thus from ... View full abstract»

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  • Design to test migration; a tester and a simulator

    Publication Year: 1990, Page(s):578 - 582
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Discusses the advantages of a good migration route from design data to test data. A good route can be established by embedding a design simulator into a test-preparation system, but development of the test-preparation software involves significant engineering work including a close examination of the simulator's interfaces. The test-preparation simulator can then be made available to designers so ... View full abstract»

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  • Transistor placement and interconnect algorithms for leaf cell synthesis

    Publication Year: 1990, Page(s):119 - 123
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Picasso is a prototype leaf cell synthesis system capable of mapping a gate level description into a complete set of layout masks, based on the line of diffusion layout style. This paper describes Picasso's algorithms for transistor placement and routing of internal nets. The transistor placement algorithm uses a composite metric which applies connectivity and optimal chaining considerations simul... View full abstract»

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  • SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system

    Publication Year: 1990, Page(s):78 - 82
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A new approach is presented for simultaneous scheduling and connectivity binding in a behavioral synthesis system. A branch-and-bound algorithm is applied for scheduling, with connectivity binding performed at each intermediate step. Costs from the connectivity binder are used to direct the search for optimal solutions. This approach allows the program to optimize user defined objectives without a... View full abstract»

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  • PROOFS: a super fast fault simulator for sequential circuits

    Publication Year: 1990, Page(s):475 - 479
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    This paper describes PROOFS, a super fast fault simulator for synchronous sequential logic circuits. PROOFS achieves high performance by combining all the advantages in differential fault simulation, single fault propagation, and parallel fault simulation to minimize the memory requirements, to reduce events that need to be simulated, and to simplify the complexity of the software implementation. ... View full abstract»

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  • Economics of point acceleration

    Publication Year: 1990, Page(s):424 - 428
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    This paper examines point accelerators from the economic point of view. Point accelerators are devices that speed-up a specific part of the design process. Examples are simulation, routing, and graphics accelerators. The paper presents general mathematical model for the economics of point accelerators. One conclusion of the model is that for many users there is no economic justification for point ... View full abstract»

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  • PEST-a tool for implementing pseudo-exhaustive self test

    Publication Year: 1990, Page(s):639 - 643
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    PEST is a CAD tool for implementing pseudo-exhaustive self test in integrated circuits. PEST's unique features are: parallel testing of all cones; global test point selection; and a new cost effective scheme for test vector generation. AT&T's network interface controller chip was designed using PEST. Effective 100% fault coverage without fault simulation or test generation was obtained with le... View full abstract»

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  • The NMP-CADLAB framework-a common framework for tool integration and development

    Publication Year: 1990, Page(s):39 - 43
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    The NMP-CADLAB framework incorporates a OO/ERA high performance user interface management system, a distributed data handling system for heterogeneous computer networks and a rich set of services for step-wise tool integration. The paper gives an overview of the framework development and its relation to the existing NMP-CAD and CADLAB software View full abstract»

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  • A gate-matrix oriented partitioning approach for multilevel logical networks

    Publication Year: 1990, Page(s):327 - 331
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    A novel approach for gate-matrix synthesis starting from an EDIF logical network description is presented. The networks are automatically decomposed into gate-matrix `macrocells' with approximately equal layout area using a very effective algorithm, which is adapted to the layout topology, featuring simultaneous module placement in conjunction with a new reliable module area estimation technique. ... View full abstract»

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