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Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date 5-9 Nov. 1989

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Displaying Results 1 - 25 of 127
  • Fast test generation for sequential circuits

    Publication Year: 1989 , Page(s): 345 - 347
    Cited by:  Papers (56)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    An efficient sequential circuit test generation algorithm is presented. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of an initial time-frame algorithm and correct implementation of a solution to the previous state information problem. The initial time-frame algorithm determines the number of time-frames required to excite the fault under test and the number of time-frames required to observe the excited fault. This step saves the test generator from doing unnecessary search in the input space. Test generation is done strictly in forward time. The algorithm saves good machine circuit state after test generation to aid in future test generation. Faulty machine state is set to unknown whenever test generation for a fault is begun. This solves the previous state information problem, which has often been ignored by existing test generators.<> View full abstract»

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  • 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers [front cover]

    Publication Year: 1989
    Save to Project icon | Request Permissions | PDF file iconPDF (31 KB)  
    Freely Available from IEEE
  • A powerful global router: based on Steiner min-max trees

    Publication Year: 1989 , Page(s): 2 - 5
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB)  

    A study is made of the global routing of multiterminal nets. The authors propose a novel global router. Each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with the maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An efficient algorithm is presented for obtaining a Steiner min-max tree, in a weighted graph. Experimental results on difficult examples, randomly generated data, master slice chips, and benchmark examples from the physical design workshop are very promising. (In all cases, previous results have been improved.).<> View full abstract»

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  • Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree

    Publication Year: 1989 , Page(s): 6 - 9
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB)  

    A polynomial time algorithm is given for constructing the minimum cost rectilinear Steiner tree (RST) that is derivable from a minimum spanning tree (MST) of a given point set, such that the MST edges have staircase layouts in the RST. RSTs produced by the algorithm have a property called stability, which enables the rerouting of any subset of the RST edges, while maintaining the cost of the RST, and not causing overlaps with each other or with the other RST edges.<> View full abstract»

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  • A minimum separation algorithm for river routing with bounded number of jogs

    Publication Year: 1989 , Page(s): 10 - 13
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (291 KB)  

    The single-layer rectilinear river routing model with no restriction on the number of jogs per wire is considered. In particular, the author studies the model in which there is a fixed constant upper bound J on the number of jogs each wire can have. The author proposes an optimal O(n) time algorithm for the feasibility problem. This leads to an O(n log n) time algorithm for the minimum separation problem. Both algorithms take O(n) space are quite practical. This is a significant improvement over T.C. Tuan and S.L. Hakimi's (1987) minimum separation algorithm, which is designed for J=2 and takes O(n/sup 3/) time and O(n/sup 2/) space.<> View full abstract»

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  • Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

    Publication Year: 1989 , Page(s): 16 - 19
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB)  

    The authors present a novel approach to the problem of register-transfer (RT) design optimization of pipelined data paths. They perform module assignment with the goal of maximizing the interconnect sharing between RT-level components. The interconnect sharing task is modeled as a constrained clique partitioning problem. They have developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30-50 times faster than other existing heuristics while still producing better results for the authors' purposes.<> View full abstract»

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  • A new integer linear programming formulation for the scheduling problem in data path synthesis

    Publication Year: 1989 , Page(s): 20 - 23
    Cited by:  Papers (55)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A novel approach is presented to the operation scheduling problem in a data path synthesis. After obtaining the start time and the require time of each operation by the ASAP (as soon as possible) and ALAP (as late as possible) methods, respectively, an integer linear programming (ILP) formulation is formed to solve the scheduling problem. The objective is to fully utilize the hardware resources, i.e. to minimize the requirement of function units under a given timing constraint. The formulation can be generalized to support multicycle operations, multiple operations per cycle, pipelined data paths, mutually exclusive operations, and variables' lifetime consideration in a data path. A fifth-order filter containing 26 addition and 8 multiplication operations can be scheduled optimally for the cases from 17 cycles to 21 cycles per minute on a VAX-11/8800.<> View full abstract»

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  • Scheduling and hardware sharing in pipelined data paths

    Publication Year: 1989 , Page(s): 24 - 27
    Cited by:  Papers (48)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB)  

    A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers, interconnect overhead, the size of the smallest sharable operator etc. are used to control the amount of sharing globally and produce a heuristically optimized RTL structure. The scheduling algorithm is iterated until a satisfactory structure is obtained. The algorithm also can be used for partitioning a large system into implementable pieces. The algorithm has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.<> View full abstract»

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  • Automating the diagnosis and the rectification of design errors with PRIAM

    Publication Year: 1989 , Page(s): 30 - 33
    Cited by:  Papers (58)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB)  

    The authors present the original extensions brought to PRIAM to automate both the diagnosis and the rectification of the design errors detected by this tool. PRIAM is an industrial automated formal verifier used to check the functional correctness of digital circuits of up to 20000 transistors. These extensions implement a novel approach to diagnosis based on Boolean equation solving. In particular, no enumeration of the faulty patterns is necessary to find out the incorrect gates in the circuit. The diagnosis system can handle any circuit that can be verified by PRIAM.<> View full abstract»

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  • Accurate logic simulation in the presence of unknowns

    Publication Year: 1989 , Page(s): 34 - 37
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB)  

    The authors address the problem of accurate logic simulation in the presence of unknowns. Algorithms to perform exact simulation using high-level descriptions are presented. The complexity of these algorithms is shown to be considerably less than that of existing algorithms. An analysis of realistic programmable logic arrays (PLAs) and some random functions is used to compare the complexity of the two algorithms presented. Data on the SN74181 ALU suggest that function blocks of similar size can be easily dealt with. The feasibility of the approach is demonstrated by a programmed implementation of the algorithms as part of a high-level test generation system.<> View full abstract»

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  • Restricted symbolic evaluation is fast and useful

    Publication Year: 1989 , Page(s): 38 - 41
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB)  

    A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.<> View full abstract»

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  • CRACKER: a general area router based on stepwise reshaping

    Publication Year: 1989 , Page(s): 44 - 47
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    CRACKER is an algorithm able to handle a large class of routing problems. Operating on a grid and using two wiring layers, it can deal with floating and fixed terminals, arbitrarily located in the routing area, and with obstacles in either of the two layers. The routing process consists of two stages. In the first stage, all nets are interconnected quickly, without avoiding conflicts with previously routed nets or obstacles. In the iterative second stage, connectivity-preserving local transformations are applied in a systematic way, such that, eventually, a solution without conflict is reached. There is no rip-up and reroute. The same algorithm is able to solve well-known examples of switchbox routing, routing with irregular boundaries, L-shaped channels, three-sided channels, etc.<> View full abstract»

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  • AGAR: a single-layer router for gate array cell generation

    Publication Year: 1989 , Page(s): 48 - 51
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB)  

    AGAR is a single-layer router which does internal wiring of gate array cells for a variety of technologies and background cell images. It starts by using image-specific heuristics to do a partial routing. The heuristics can be supplied by the circuit designer and may be coded using a rule-based shell or a standard programming language. The routing is completed using an image-independent algorithm which systematically generates legal routings on a virtual grid, in increasing order of cost, until a complete legal routing is found or the search fails. AGAR was used to generate the majority of the cells in a CMOS gate array cell library and to complete partial routings of bipolar gate array cells.<> View full abstract»

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  • A new approach to sea-of-gates global routing

    Publication Year: 1989 , Page(s): 52 - 55
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB)  

    The authors integrate the concepts and techniques of two existing complementary approaches, namely, the rerouting approach and the top-down hierarchical approach based on linear assignment. This combines and enhances the advantages of the two approaches and results in a fast and high-quality router which can handle large sea-of-gates designs. In addition, it solves the problems of routing interdependence and routing resource estimation which heretofore have not been well addressed yet. The method has been implemented and successfully tested on three real gate-arrays chips: Primary 1, Primary 2, and a channelless industrial example with 100 K gates.<> View full abstract»

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  • Manual rescheduling and incremental repair of register-level datapaths

    Publication Year: 1989 , Page(s): 58 - 61
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (335 KB)  

    A description is given of new capabilities of the RLEXT register level exploration tool. RLEXT is an interactive tool that takes a datapath design and allows a user to modify it freely, using transformations that do not themselves preserve correctness. By maintaining a representation of the desired behavior and timing as well as structure, RLEXT is able to 'repair' the design when the user creases modifying, so that the ability of the design to express the specified behavior is once again guaranteed. A description is also given of RLEXT's support for manual changes of schedule in the presence of an existing data-path structure. Such schedule changes invalidate the structure, but the structure is incrementally repaired rather than just thrown out. The author knows of no other high-level synthesis tool that supports this kind of functionality.<> View full abstract»

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  • A resource sharing and control synthesis method for conditional branches

    Publication Year: 1989 , Page(s): 62 - 65
    Cited by:  Papers (53)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB)  

    A scheduling/allocation and control synthesis algorithm is presented. The proposed algorithm can achieve good resource sharing and synthesize an efficient control sequence for nested conditional branches as well as for straight-line codes. The condition vector concept is introduced to allow mutual exclusion to be detected among operators, and is used to produce more efficient control sequences. The condition vector concept is concerned with the handling of nested condition branches and can be used for other scheduling methods. Results obtained from several experiments indicate that the proposed algorithms are efficient and effective.<> View full abstract»

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  • A logic synthesis system for VHDL design descriptions

    Publication Year: 1989 , Page(s): 66 - 69
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (349 KB)  

    The VHSIC hardware description language (VHDL) is emerging as an industry standard for the modeling of electronic systems. A description is given of a logic synthesis system developed to realize ASIC CMOS chip designs from VHDL descriptions, designs optimized for cell count and performance. The utilization of VHDL attributes and the interpretation of attribute data by synthesis transformations are highlighted. Timing optimization algorithms based upon calculated timing slack values are described in detail. The unique means by which clock repowering trees are incorporated is also discussed.<> View full abstract»

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  • A timing model for static CMOS gates

    Publication Year: 1989 , Page(s): 72 - 75
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB)  

    A simple but accurate delay model is presented for both simple and complex static logic gates. Unlike the previous delay models which assume the worst-case scenario, the present model has the capability of handling the different input switching conditions. In the delay analysis of a circuit, failing to take into account the position of the transistor that is switching can result in a delay value which is off by a margin of 100% or more from the actual. This novel modeling technique has been implemented in LISP on a TI Explorer II workstation Lisp Machine as a part of the DROID design automation environment.<> View full abstract»

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  • An accurate timing model for fault simulation in MOS circuits

    Publication Year: 1989 , Page(s): 76 - 79
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB)  

    An accurate timing model is presented for MOS circuits, which is based on a multiple-valued logic representation, accurate RC models for delay calculations derived from transistor characteristics and slope information, and accurate models for physical failures. A delay fault simulator (FACT) based on this model has been implemented. Results for various MOS circuits are described and compared with those for SPICE and RSIM.<> View full abstract»

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  • Event-EMU: an event driven timing simulator for MOS VLSI circuits

    Publication Year: 1989 , Page(s): 80 - 83
    Cited by:  Papers (20)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB)  

    An event-driven approach to MOS timing simulation is presented, which has proved to be more efficient and reliable than time-step-based methods. The MOS network is statically partitioned into groups of strongly coupled nodes called regions. Regions are scheduled for evaluation using a priority event queue. Events are predictions of the time at which nodes within a region will change by more than a voltage threshold. Region evaluation is performed using a single modeling step followed by linear relaxation. The simulator has been used to verify the timing and functionality of a number of large (>500 K transistors) VLSI chips. Performance is 2-5 times faster than time-step-based methods and 200-300 times faster than circuit simulation.<> View full abstract»

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  • Automatic mixed-mode timing simulation

    Publication Year: 1989 , Page(s): 84 - 87
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A novel technique is introduced for automatically performing mixed-mode timing simulation of MOS circuits. A SPICE2 circuit description is assumed to be given, the circuit is first partitioned into channel-connected subcircuits. Each subcircuit is then examined and is statically classified as digital or analog if one of many configurations is detected. Subcircuits which contain memory cells, sense amplifiers, or internal feedback are automatically classified as analog. Any user-specified analog subcircuits are classified as analog. Analog subcircuits are simulated using detailed electrical simulation while digital subcircuits are simulated using fast timing simulation with a ramp waveform representation. Fast timing simulation uses a nonlinear macromodel to model the charging and discharging of subcircuit output nodes. State transitions are initially modeled using a single ramp. Static and dynamic mode selection are used to ensure that accuracy is retained during simulation while minimizing simulation time. The implementation of these techniques in IDSIM2 is discussed. Examples of automatic mixed-mode timing simulation are presented.<> View full abstract»

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  • Global refinement for building block layout

    Publication Year: 1989 , Page(s): 90 - 93
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    A global optimization method with global wiring refinement for building block placement is proposed. The method is based on the notion of a vertex decomposed digraph, called the mixed graph model, which has both orientable edges and directed edges to reflect global routing information and its modification. Global wiring is estimated in terms of chip area and is to be optimized. The graph model is proved to be determinant and legal. A nonconflict precise vertex decomposition (PVD) method is described, and a global wiring refinement method is presented together with a topological bottleneck model. Promising results were obtained in several runs on practical examples.<> View full abstract»

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  • Timing driven placement

    Publication Year: 1989 , Page(s): 94 - 97
    Cited by:  Papers (66)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (371 KB)  

    The authors address the problem of incorporating timing constraints into the physical design of integrated circuits. First they formulate the problem and discuss graph models suitable for its analysis. Next, they describe algorithms resulting in placements of improved performance in comparison to placements whose objective is to minimize the summation of wire lengths on the chip. Finally, the authors show preliminary results of their placement programs for the sea-of-gates designs.<> View full abstract»

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  • Combining partitioning and global routing in sea-of-cells design

    Publication Year: 1989 , Page(s): 98 - 101
    Cited by:  Papers (4)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (297 KB)  

    A report is presented on the partitioning algorithm of a novel automatic layout system for the sea-of-cells design. The algorithm is based on graph partitioning. The principal novelty of the approach is that a global routing is obtained after each iteration to precisely estimate the number of nets crossing a cut. The author also report on the successful application to CMOS chips of the IBM ES/370 chip set.<> View full abstract»

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  • Layout methods for digital optical computing

    Publication Year: 1989 , Page(s): 102 - 105
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB)  

    A recognized model for an all-optical digital computer consists of arrays of optical logic devices interconnected in free space. In order to simplify device requirements and to reduce the complexity of the optics, regular interconnects between logic gates are considered such as crossovers. Problems and solutions related to the computer-aided design of these systems are identified, such as layout, fault avoidance, pipelining, and other considerations. An algorithm for determining settings for an optical programmable logic array that maintains a strict crossover interconnect at the gate level is described as an example of computer-aided design applied to this model.<> View full abstract»

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