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Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

2-4 Oct. 1989

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Displaying Results 1 - 25 of 116
  • A hierarchical constraint graph generation and compaction system for symbolic layout

    Publication Year: 1989, Page(s):532 - 535
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB)

    A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in... View full abstract»

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  • Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.89CH2794-6)

    Publication Year: 1989, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (920 KB)
    Freely Available from IEEE
  • Computer aided design system for VLSI interconnections

    Publication Year: 1989, Page(s):237 - 241
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A simulation environment for prediction of electrical characteristics of integrated circuit packaging structures is described. The simulation shell, Packaging Design Support Environment (PDSE), integrates tools for modeling and simulation of electrical characteristics in VLSI packages. It also provides facilities for supporting design of VLSI packages. Two simulation tools model inductance and cap... View full abstract»

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  • Motion estimation VLSI architecture for image coding

    Publication Year: 1989, Page(s):78 - 81
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Special-purpose chips based on highly parallel architectures, for possible use in videophone, videoconference, digital TV distribution and HDTV codecs, are considered. Functional interface specifications for a motion estimator to be inserted in a coder system are detailed. The range of possible operative part-kernel architectures is derived, based on formal high-level synthesis methods. A novel im... View full abstract»

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  • Comparison of chip crossing delay in various packaging environments

    Publication Year: 1989, Page(s):233 - 236
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The effect of packaging on computer performance is becoming increasingly significant because of delay due to package parasitics and connectivity between functional blocks. The first issue is addressed with an example of how chip crossing delay is influenced by the choice of packaging environment. Five separate packaging technologies are investigated. Simulation of this delay is useful for comparin... View full abstract»

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  • A module-sliced approach for high yield VLSI/WSI processors

    Publication Year: 1989, Page(s):500 - 503
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2... View full abstract»

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  • Electromigration median time-to-failure based on a stochastic current waveform

    Publication Year: 1989, Page(s):447 - 450
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The estimation of the median time-to-failure (MTF) due to electromigration in the power and ground buses of VLSI circuits is addressed. In their previous work (Proc. 25th ACM/IEEE Design Autom. Conf., p.294-9, 1988), the authors presented a novel technique for MTF estimation based on a stochastic current waveform model. They derived the mean (or expected) waveform (not a time average) of such a cu... View full abstract»

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  • A general-purpose video signal processor: architecture and programming

    Publication Year: 1989, Page(s):74 - 77
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Programming aspects of a new digital, flexible processor especially designed for the effective processing of real-time video signals are addressed. The modular architecture contains a number of programmable, pipelined processing elements. A programmable crossbar switch provides a flexible interconnection between the processing elements. The programs can be constructed with the aid of graphical, in... View full abstract»

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  • Accurate prediction of physical design characteristics for random logic

    Publication Year: 1989, Page(s):100 - 108
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    An accurate model is presented for the prediction of physical design characteristics, such as interconnection lengths and layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the logic design specification, the physical design process, and the physical implementation technol... View full abstract»

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  • Integration and packaging plateaus of processor performance

    Publication Year: 1989, Page(s):229 - 232
    Cited by:  Papers (1)  |  Patents (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Integration and packaging performance limits are refined in the context of computer systems. In particular, limits of computer performance under various packaging, architectural, organizational, and design techniques (e.g. gate-array versus custom) are explored. It is concluded that fully integrated processors can have modest electrical signal I/O requirements because the frequency of signals cros... View full abstract»

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  • Digital and analog integrated-circuit design with built-in reliability

    Publication Year: 1989, Page(s):496 - 499
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated-circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigr... View full abstract»

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  • A yield model for the evaluation of topologically constrained chip architectures

    Publication Year: 1989, Page(s):443 - 446
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Conventional M-out-of-N yield models can only roughly represent many practical chip architectures. On the other hand, representative models have the drawback of computational complexity. A yield model is introduced that overcomes the limits of existing models and provides ease of computation and predictability in approximation levels. The model is versatile enough to be included ... View full abstract»

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  • A low-impedance load detector circuit for optical interconnects

    Publication Year: 1989, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Optical interconnects provide an alternative for long-distance electrical clock distribution in high-speed VLSI circuits. In an optical interconnect system, the response of the detector circuit is an important factor in determining the speed of the overall system. A simple, low-impedance nMOS detector circuit is presented and modeled for optical interconnect application in CMOS systems. A maximum-... View full abstract»

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  • A fast floor planning algorithm for architectural evaluation

    Publication Year: 1989, Page(s):96 - 99
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A method for producing a chip floor plan from a list of blocks and their interconnections is presented. The blocks can be of different sizes, and each block can have several possible aspect ratios. The algorithm places the blocks and chooses the orientation and aspect ratio of each to produce a near-minimum area floor plan. The preliminary placement of the blocks is done using a standard min-cut p... View full abstract»

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  • Adaptive and pipelined VLSI designs for tree-based codes

    Publication Year: 1989, Page(s):369 - 372
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A new class of VLSI architectures for data transformation of tree-based codes is proposed. The focus is on transformation functions used for data compression and decompression. The encoding algorithm is based on a pipeline architecture and can generate the code bits in parallel. The algorithms use the principle of propagation of a token in a reverse binary tree constructed from the original codes.... View full abstract»

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  • An IBM second generation RISC processor architecture

    Publication Year: 1989, Page(s):134 - 137
    Cited by:  Papers (6)  |  Patents (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A second-generation RISC (reduced-instruction-set computer) architecture designed to support superscalar implementations which can execute multiple instructions every cycle is described. The architecture provides compound function instructions which allow application path lengths to be less than would be required on many complex-instruction-set computers. This second-generation RISC architecture a... View full abstract»

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  • The design of a multi-chip single package digital signal processing module

    Publication Year: 1989, Page(s):224 - 228
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A 32-b floating-point digital signal processor IC is integrated with eight 16 K×4-b SRAM chips on a silicon substrate, thus minimizing the parasitic loading to the processor buffer and enabling zero-wait-state access of the full 64-kB of memory. The module is rated at 25 MHz up to 125°C and 70 MHz at liquid nitrogen temperature. A large percentage of modules operate up to 40 MHz at room ... View full abstract»

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  • OPAM: an efficient output phase assignment for multilevel logic minimization

    Publication Year: 1989, Page(s):270 - 273
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    When a multiple-output function (z1, z2, . . ., zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the pr... View full abstract»

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  • Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability

    Publication Year: 1989, Page(s):492 - 495
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A framework for a reliability simulation tool to assess the hot-carrier-induced degradation of MOS circuits is presented, and the major components of this framework are examined. A method is introduced for dynamic simulation of hot-carrier-induced transistor degradation within the circuit environment. The approach accounts for the gradual degradation of terminal voltage waveforms of MOS transistor... View full abstract»

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  • Reliability issues of MOS and bipolar ICs

    Publication Year: 1989, Page(s):438 - 442
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Reliability issues affecting MOS and bipolar ICs are reviewed. Hot-carrier-induced degradation of MOS and bipolar circuits are used to illustrate the potential role of reliability CAD tools. Electromigration lifetimes under pulse DC and AC current stressing are longer than previously thought. Oxide breakdown offers a case study for accelerated test modeling, defect statistics, and burn-in optimiza... View full abstract»

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  • An integrated free space optical bus

    Publication Year: 1989, Page(s):62 - 65
    Cited by:  Papers (8)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    As integrated circuit linewidths are reduced, single-chip system functionality and speed increase. Conventional electronic chip input/output does not follow this trend: bonding pad sizes and off chip capacitive loads remain essentially constant. Shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by pro... View full abstract»

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  • Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture

    Publication Year: 1989, Page(s):580 - 584
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A unified solution to the problems that arise in the design, development, and test of VLSI processors is offered. The JTAG/IEEE P1149.1 standard boundary-scan architecture is proposed as the basis for designing testable, defect-tolerant, VLSI processors. The test access port (TAP) provided by the boundary-scan architecture is used to control and repair the microprogram control unit, as well as to ... View full abstract»

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  • A global floorplanning technique for VLSI layout

    Publication Year: 1989, Page(s):92 - 95
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The floorplanning of rectangular cells is discussed. A new global approach that simultaneously accounts for different design goals is presented. A key aspect of this approach is a more general slicing structure representation of the floorplan that is not restricted to a special case of rectangular dissection and a two-dimensional partitioning procedure. A new model for the prediction of the associ... View full abstract»

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  • Systolic L-U decomposition array with a new reciprocal cell

    Publication Year: 1989, Page(s):460 - 465
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A systolic architecture for L-U decomposition using a recently developed reciprocal cell is presented. The arithmetic of this new cell is based on second-order polynomial interpolation, which results in high speed and inherent stability in inversion. In part, the speed of the cell is realized by use of a special empirical mapping. For the 16-b mantissa of a floating point number,... View full abstract»

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  • A VLSI module for IEEE floating-point multiplication/division/square root

    Publication Year: 1989, Page(s):366 - 368
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0-μm CMOS standard cell technology, the total area ... View full abstract»

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