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Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date 2-4 Oct. 1989

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  • Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.89CH2794-6)

    Publication Year: 1989 , Page(s): 0_1
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    Freely Available from IEEE
  • FPC: a floating-point processor controller chip for systolic signal processing

    Publication Year: 1989 , Page(s): 14 - 17
    Cited by:  Papers (1)
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    The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-b instruction word that provides concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams. The novel architectural features of the cell are described, and a matrix multiplication example is used to demonstrate their usefulness View full abstract»

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  • A fast algorithm for mixed-radix conversion in residue arithmetic

    Publication Year: 1989 , Page(s): 18 - 21
    Cited by:  Papers (4)
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    An algorithm based on a partitioning of the coefficient matrix when the mixed-radix conversion problem is cast as a set of linear congruent equations is presented. The algorithm partitions the moduli set into disjoint subsets such that the product of the moduli in each subset is less than the largest integer representable by the computer. It is shown that, with this partitioning strategy, mixed-radix representation of a residue number can be computed using less than O (n2) arithmetic steps where n is the cardinality of the moduli set. It is also shown that if a good partitioning exists, then the algorithm requires only O(n 1.5) arithmetic steps. The algorithm is particularly suitable for single processor implementation of algorithms from the residue number system applications View full abstract»

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  • Generic ASIC architecture for digital signal processing

    Publication Year: 1989 , Page(s): 82 - 85
    Cited by:  Papers (7)
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    The architectural methodology behind a novel high-level VLSI cell compiler currently under development is described. The tool is aimed specifically at digital signal processing applications, synthesizing powerful arithmetic kernel processors from high-level parameterized schematics. Underlying the tool is a generic pipelined numerical processing architecture, flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. Machines are synthesized using this architecture as a blueprint. To this end, the tool encapsulates the essential knowledge required to assemble a useful set of arithmetic operators over all local and global parametric combinations. Some multiplier instances are illustrated View full abstract»

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  • Issues in the test of artificial neural networks

    Publication Year: 1989 , Page(s): 487 - 490
    Cited by:  Papers (2)
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    Test concepts for artificial neural networks are discussed. It is shown that the traditional design-for-test techniques such as (boundary) scan are of limited use owing to the high connectivity and redundancy of neural networks. An information-theoretical approach that allows for wafer as well as chip test is outlined. This approach involves testing directly on the macro properties of the neural network. The influence of device faults and built-in fault tolerance of the network is captured in so-called fault tolerant curves. These curves, obtained by simulation, link the various macro and micro properties together and allow an information-driven test of the neural network View full abstract»

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  • Performance and microarchitecture of the i486 processor

    Publication Year: 1989 , Page(s): 182 - 187
    Cited by:  Papers (2)  |  Patents (3)
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    The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5× reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4× clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion View full abstract»

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  • SLAM: a smart analog module layout generator for mixed analog-digital VLSI design

    Publication Year: 1989 , Page(s): 24 - 27
    Cited by:  Papers (7)
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    A tool for the smart layout of analog modules, which aims to provide a flexible analog layout solution for the mixed analog-digital VLSI design environment, is described. New algorithms have been developed for novel primitive cell recognition, intelligent layout and detail routing, and performance-driven optimization. Software implementation and experimental results on several analog VLSI modules such as operational amplifiers and voltage-controlled oscillators are presented View full abstract»

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  • Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems

    Publication Year: 1989 , Page(s): 362 - 365
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    A counter-based residue arithmetic circuit composed of ring counters which performs residue arithmetic operations by pulse counting is proposed for easily testable VLSI digital signal processing systems. A master-slice LSI on which counter-based residue arithmetic circuits are regularly arranged is also presented. It is demonstrated that the counter-based residue arithmetic circuit has a self-testable structure, and a highly regular and easily testable system implementation can be realized using the circuits View full abstract»

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  • The matrix transform chip

    Publication Year: 1989 , Page(s): 86 - 89
    Cited by:  Papers (1)  |  Patents (3)
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    The matrix transform chip (MTC) is designed to perform matrix computations of the form Y=UDV where D is the input data matrix of 16-bit twos complement fixed-point numbers and U, V, are arbitrary coefficient matrices of the same precision. The data matrix D is input to the chip in raster scanned order at a maximum sample rate of 40 MHz, and the output matrix is provided in the same order. On a single chip, the maximum dimension of all matrices must be less than eight, but multiple chips can be cascaded to obtain arbitrary dimensions. The MTC consists of 16 16-bit parallel multipliers/40-bit accumulators, a kilobyte of dual-ported transposition static RAM, and a kilobyte of coefficient static RAM, arranged to interact in a regular iterative architecture. At peak operation, the MTC is capable of performing 0.64 billion fixed-point multiples, 0.64 billion 40-bit accumulates, along with 1.92 billion pseudorandom memory-access operations per second View full abstract»

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  • Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability

    Publication Year: 1989 , Page(s): 492 - 495
    Cited by:  Papers (10)
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    A framework for a reliability simulation tool to assess the hot-carrier-induced degradation of MOS circuits is presented, and the major components of this framework are examined. A method is introduced for dynamic simulation of hot-carrier-induced transistor degradation within the circuit environment. The approach accounts for the gradual degradation of terminal voltage waveforms of MOS transistors during long-term operation. It is demonstrated that the estimation of individual device lifetimes is not sufficient for circuit reliability assessment. The critical transistors that are most likely to cause circuit performance failures are identified by combining the long-term degradation estimates with the corresponding circuit performance sensitivities View full abstract»

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  • Novel architecture for a high performance full custom graphics processor

    Publication Year: 1989 , Page(s): 410 - 414
    Cited by:  Patents (21)
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    The design and architectural features of a 32-b microprogrammed graphics processor are discussed. A description is given of the application of datapath elements and the exploitation of VRAM hardware, to achieve state-of-the-art processor performance levels. The host interface is discussed, along with video control, screen refresh control, and emulation and testability View full abstract»

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  • High performance I/O processors for real-time pulse handling

    Publication Year: 1989 , Page(s): 415 - 418
    Cited by:  Papers (1)
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    Two peripheral processor LSIs, the FTI (fast timed input port) and the FTO (fast timed output port), have been developed for real-time pulse handling. By using the time-wheel scheme, these processors provide a high-level command interface with the host CPU, thus alleviating the CPU load. New features, such as time difference measurement between channels and user reprogrammability during operation have been realized using this approach. The prototypes of both FTI and FTO were designed and fabricated using a 1.5-μm CMOS sea-of-gates technology, and demonstrated the effectiveness of the time-wheel scheme View full abstract»

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  • A VLSI module for IEEE floating-point multiplication/division/square root

    Publication Year: 1989 , Page(s): 366 - 368
    Cited by:  Patents (5)
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    The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0-μm CMOS standard cell technology, the total area of this module is approximately 7.0 mm×6.5 mm, which is just 25% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns View full abstract»

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  • A cost function based optimization technique for scheduling in data path synthesis

    Publication Year: 1989 , Page(s): 424 - 427
    Cited by:  Papers (12)
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    A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods View full abstract»

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  • A 32-bit microprocessor with high performance bit-map manipulation instructions

    Publication Year: 1989 , Page(s): 406 - 409
    Cited by:  Papers (3)  |  Patents (2)
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    The GMICRO/100, a 32-b microprocessor based on the TRON architecture specification, is described. The GMICRO/100 uses high-level instructions, such as those in bit-map manipulation. The bit-map instructions are implemented by pipelining micro-operations, and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 to 3 times faster than repeating move instructions by the software. Microprogram development tools for the GMICRO/100 design are described View full abstract»

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  • An integrated free space optical bus

    Publication Year: 1989 , Page(s): 62 - 65
    Cited by:  Papers (8)  |  Patents (25)
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    As integrated circuit linewidths are reduced, single-chip system functionality and speed increase. Conventional electronic chip input/output does not follow this trend: bonding pad sizes and off chip capacitive loads remain essentially constant. Shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high-speed connections between chips. A description is given of the application of free-space optics, quantum-well modulators, and CMOS photodetectors to this task View full abstract»

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  • Internal ECL-BiCMOS translator circuits in half micron technology

    Publication Year: 1989 , Page(s): 314 - 317
    Cited by:  Patents (2)
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    BiCMOS associates high-speed circuits with the low power requirements of CMOS. Traditional BiCMOS circuits are mainly CMOS-based with bipolar buffers to improve driving capability and speed. Increased performance can be obtained with BiCMOS technology if CMOS/BiCMOS circuits are merged with an ECL (emitter-coupled logic) low swing circuit. Mixing of logic is possible if very-high-speed level translators for levels conversion are designed. The benefits of such an approach in 0.5-μm BiCMOS technology have been estimated for the proposed ECL-to-CMOS-level convertor circuits View full abstract»

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  • Correctness verification of VLSI modules supported by a very efficient Boolean prover

    Publication Year: 1989 , Page(s): 266 - 269
    Cited by:  Papers (2)  |  Patents (1)
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    A description is given of efficient techniques for checking tautology of a Boolean expression, i.e. whether two Boolean expressions are equivalent, taking into account `don't care' behavior if necessary. If two Boolean expressions appear to be not equivalent, a test case is generated. The tautology checker has been developed to perform functional and logical verification of combinational modules and is integrated in an environment for formal electrical verification. Its efficiency is based on a delicate and optimized interaction between a carefully chosen set of Boolean rewriting rules and a number of heuristics. A number of test cases show its performance as compared to existing tautology checkers. Figures on industrial PLAs are included View full abstract»

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  • An enhanced high performance combinational fault simulator using two-way parallelism

    Publication Year: 1989 , Page(s): 294 - 297
    Cited by:  Papers (2)
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    A combinational fault simulator using two-way parallelism and a number of refinements to reduce memory usage is presented. The results show the approach to be generally superior to the basic parallel patterns single fault propagation (PPSFP) algorithm. One of the refinements, processing to encourage the sharing of fault machine indices by independent faults, appears to require substantially more processing time than it saves during simulation. The remaining preprocessing steps are comparable to those used for basic PPSFP, and are highly justified by their run-time savings. The concept of adjusting the parallelism factor to account for increasingly random-resistant faults seems to work quite well View full abstract»

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  • Architectural features of the i860-microprocessor RISC core and on-chip caches

    Publication Year: 1989 , Page(s): 385 - 390
    Cited by:  Papers (5)  |  Patents (35)
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    The Intel i860 is a one-million-transistor, high-performance RISC (reduced-instruction-set computer) microprocessor. The performance of the i860 CPU is derived using supercomputer architectural concepts such as parallel instruction execution and a 64-b architecture that provides the data and instruction bandwidth necessary to support multiple operations. The novel features of the i860 RISC integer core are explored. The on-chip cache architecture, which is optimized for large data and instruction bandwidth, is described View full abstract»

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  • A framework for evaluating test pattern generation strategies

    Publication Year: 1989 , Page(s): 44 - 47
    Cited by:  Papers (4)
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    A formal approach for the analysis of heuristics used in automatic test pattern generation for combinational circuits is presented. A test pattern generation system that constructs a satisfying assignment for a Boolean formula describing the legal set of tests is discussed. Heuristics as modifications to the formula or the satisfier acting on the formula are described. Experimental results are provided for the system as a whole, and for the effects of four heuristics View full abstract»

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  • An algorithm for voice and data integration on packet-switched local area networks

    Publication Year: 1989 , Page(s): 156 - 159
    Cited by:  Papers (1)
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    The single-cycle protocol for integrating voice and data transmission on local area networks is introduced. This protocol is capable of maintaining low average data delays while supporting a large number of simultaneous voice calls. It makes more efficient use of silence suppression than classical time-assignment speech interpolation (TASI). Simulation results are presented and the performance with respect to other voice/data networks is discussed View full abstract»

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  • Design of TSC checkers for implementation in CMOS technology

    Publication Year: 1989 , Page(s): 116 - 119
    Cited by:  Papers (2)
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    A fault model for CMOS digital circuits includes FET stuck-open and FET stuck-on faults, in addition to line stuck-at faults used conventionally. It has been shown that delays in CMOS circuits, under test, may invalidate tests derived by neglecting such delays. This necessitates reinvestigation of existing totally self-checking (TSC) checker designs from a new perspective. It was shown earlier that TSC checkers derived on the basis of the line stuck-at fault model for constant weight codes may not be self-testing for the CMOS fault model, violating one of the conditions of TSC circuits. A design procedure for constructing a self-testing circuit for the CMOS fault model using at most four levels is suggested. Thus previous designs can be adapted for the CMOS fault model without any penalty. The new design also makes it possible to meet arbitrary fan-in restrictions View full abstract»

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  • DAGAR: an automatic pipelined microarchitecture synthesis system

    Publication Year: 1989 , Page(s): 428 - 431
    Cited by:  Papers (2)
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    An automated microarchitecture synthesis system called DAGAR is presented. DAGAR takes as input a behavioral description of a digital system and outputs a microinstruction (MI) sequence and a data path. In microarchitectures synthesized by DAGAR the functional units (FUs) may take one or more clocks (i.e. MIs) to perform an operation. These are called multiclocked FUs. Additionally, if these FUs can accept new data while processing data from a previous MI, they are called pipelined FUs. The use of pipelined FUs is shown to decrease the number of FUs in the data path without a time penalty. Unlike other systems, DAGAR deals with the partitioning of a single FU into stages View full abstract»

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  • Computer aided design system for VLSI interconnections

    Publication Year: 1989 , Page(s): 237 - 241
    Cited by:  Papers (6)  |  Patents (1)
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    A simulation environment for prediction of electrical characteristics of integrated circuit packaging structures is described. The simulation shell, Packaging Design Support Environment (PDSE), integrates tools for modeling and simulation of electrical characteristics in VLSI packages. It also provides facilities for supporting design of VLSI packages. Two simulation tools model inductance and capacitance for multiconductor, multidielectric, two-dimensional structures with lossy dielectrics. Another accepts the L and C matrices and computes pulse response characteristics of uniform multiple, coupled, lossless transmission lines which are terminated at discrete points with R, L, and C elements. The design process in PDSE proceeds in three major phases: modeling, simulation, and evaluation. These processes are interactive and allow the designer to refine a design model, modify simulation experiments, and apply various evaluation processes View full abstract»

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