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Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

2-4 Oct. 1989

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Displaying Results 1 - 25 of 116
  • A hierarchical constraint graph generation and compaction system for symbolic layout

    Publication Year: 1989, Page(s):532 - 535
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB)

    A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in... View full abstract»

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  • Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.89CH2794-6)

    Publication Year: 1989, Page(s): 0_1
    Request permission for commercial reuse | PDF file iconPDF (920 KB)
    Freely Available from IEEE
  • Design of TSC checkers for implementation in CMOS technology

    Publication Year: 1989, Page(s):116 - 119
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A fault model for CMOS digital circuits includes FET stuck-open and FET stuck-on faults, in addition to line stuck-at faults used conventionally. It has been shown that delays in CMOS circuits, under test, may invalidate tests derived by neglecting such delays. This necessitates reinvestigation of existing totally self-checking (TSC) checker designs from a new perspective. It was shown earlier tha... View full abstract»

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  • A system simulation environment within Digital

    Publication Year: 1989, Page(s):555 - 560
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The authors discuss the use of simulation as an integral part of the product development process at the Digital Equipment Corporation. One engineering computer-aided-design group within Digital provides a proven process and tool suite which was used to simulate such products as the MicroVAX II, MicroVAX 3500, VT320, and others. This process includes model libraries and specific design verification... View full abstract»

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  • Floorplan optimization on multiprocessors

    Publication Year: 1989, Page(s):109 - 114
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A parallel formulation of a branch-and-bound algorithm for floorplan optimization in VLSI design is given. Implementation details and performance analyses of the authors' formulation are presented. This implementation was done on a 128-node Symult s2010 multicomputer, as well as on a network of 16 SUN workstations. In the experiments with realistic problems, linear speedups on both machine configu... View full abstract»

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  • Efficient double asymmetric error correcting codes

    Publication Year: 1989, Page(s):166 - 171
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Two constructions for double-asymmetric-error-correcting codes are given. These codes offer some desirable properties for optical communication, where it is important that most codewords have small weights. The first construction gives a subset of a double-error-correcting BCH code. The code offers considerable improvement in the weight distribution at the expense of one extra bit of redundancy (i... View full abstract»

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  • System-level design verification in the AT&T Computer Division: tools

    Publication Year: 1989, Page(s):548 - 554
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The authors present the CAD tools used for system-level design verification (DV) in the AT&T computer division. They discuss features of the tools for building and preparing the model of the system, developing tests, simulation, static timing analysis, results analysis, and circuit comparison. While a good simulator is an essential component, many other tools are required. Although some of the... View full abstract»

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  • An IBM second generation RISC processor architecture

    Publication Year: 1989, Page(s):134 - 137
    Cited by:  Papers (6)  |  Patents (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A second-generation RISC (reduced-instruction-set computer) architecture designed to support superscalar implementations which can execute multiple instructions every cycle is described. The architecture provides compound function instructions which allow application path lengths to be less than would be required on many complex-instruction-set computers. This second-generation RISC architecture a... View full abstract»

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  • Accurate prediction of physical design characteristics for random logic

    Publication Year: 1989, Page(s):100 - 108
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    An accurate model is presented for the prediction of physical design characteristics, such as interconnection lengths and layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the logic design specification, the physical design process, and the physical implementation technol... View full abstract»

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  • Improved testability evaluations in combinational logic networks

    Publication Year: 1989, Page(s):352 - 355
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Two methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a ... View full abstract»

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  • A microprogrammable VLSI routing controller for HARTS

    Publication Year: 1989, Page(s):160 - 163
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The design and implementation of a VLSI routing controller for use in the Hexagonal Architecture for Real-Time Systems (HARTS), which is currently being built, are presented. The routing controller is a microprogrammed unit designed to function as an intelligent front-end interface for the interconnection network. Unlike other routine controllers known to date, this routing controller allows for t... View full abstract»

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  • System-level design verification in the AT&T computer division: overview and strategy

    Publication Year: 1989, Page(s):542 - 547
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors present the experience and strategy guiding the system-level computer-aided design verification (CADV) process used in the AT&T computer division. Specifically, they provide an overview of processes, results, and the strategy used to choose among modeling options, styles for the verification process, methods for test development, timing models, and techniques for analyzing results.... View full abstract»

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  • A cached system architecture dedicated for the system IO activity on a CPU board

    Publication Year: 1989, Page(s):518 - 522
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The architecture of a cached IO subsystem on a CPU board of a high-performance workstation is described. The cached IO subsystem is intended to reduce the memory latency for IO activity and minimize the number of processor cycles stolen by IO traffic, to achieve a better balanced computer system in terms of both the CPU computation power and the system IO bandwidth. The model of the cached IO subs... View full abstract»

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  • Ordered binary decision diagrams and circuit structure

    Publication Year: 1989, Page(s):392 - 395
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The relationship between two important means of representing Boolean functions, combinational circuits and ordered binary decision diagrams (OBDDs), is studied. Circuit width is related to OBDD size, and it is shown how register allocation can be used to determine a good variable order of OBDD construction. It is shown that if C has n inputs, m outputs, and width ... View full abstract»

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  • Computation with simultaneously concurrent error detection using bi-directional operands

    Publication Year: 1989, Page(s):128 - 131
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A novel method of computation with simultaneously concurrent error detection using bidirectional operands (BIDO) is presented. This technique will provide an efficient and optimal design for an arithmetic unit with fault tolerance. The technique retains all the capabilities of the space redundancy and time redundancy methods, but does not inherit their drawbacks. BIDO requires less hardware overhe... View full abstract»

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  • FPC: a floating-point processor controller chip for systolic signal processing

    Publication Year: 1989, Page(s):14 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique ... View full abstract»

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  • Schematic specification of datapath layout

    Publication Year: 1989, Page(s):28 - 34
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    A graphical assembly language for specifying custom VLSI datapaths is described. By applying certain restrictions to the format, hierarchical annotated schematics which specify the logical structure of a datapath can also be used to specify the physical layout. The close coupling of the logical and physical specifications allows more efficient implementations by highlighting the implications of ar... View full abstract»

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  • Automatic verification of speed-independent circuits with Petri net specifications

    Publication Year: 1989, Page(s):212 - 216
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Asynchronous designs are of increasing interest because of the cost of broadcasting clocks over large areas of a chip. A tool for comparing implementations of speed-independent circuits with specifications is described. Petri nets are used throughout as a user-level description language. These are translated into trace structures, which can then be processed by an existing automatic verifier. This... View full abstract»

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  • A fast floor planning algorithm for architectural evaluation

    Publication Year: 1989, Page(s):96 - 99
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A method for producing a chip floor plan from a list of blocks and their interconnections is presented. The blocks can be of different sizes, and each block can have several possible aspect ratios. The algorithm places the blocks and chooses the orientation and aspect ratio of each to produce a near-minimum area floor plan. The preliminary placement of the blocks is done using a standard min-cut p... View full abstract»

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  • A VLSI residue arithmetic multiplier with fault detection capability

    Publication Year: 1989, Page(s):348 - 351
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A programmable residue-arithmetic-based multiplier is presented. The modulo-m multipliers are implemented using a set of identical multiplexer modules designed in pass logic. This makes the design simple, easily expandable, and ideally suited for VLSI implementation. The multiplier has single residue fault detection capability View full abstract»

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  • Computer aided design and built in self test on the i486 CPU

    Publication Year: 1989, Page(s):199 - 202
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    The computer-aided design tools created to accelerate the design of the i486 CPU are described. Emphasis is on the logic synthesis, layout synthesis, and timing verification programs. The impact of the state-of-the-art tools on the project schedule is described, and the built-in self-test features on the processor are detailed. The type of advanced tools that will be required to design and test fu... View full abstract»

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  • An algorithm for voice and data integration on packet-switched local area networks

    Publication Year: 1989, Page(s):156 - 159
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The single-cycle protocol for integrating voice and data transmission on local area networks is introduced. This protocol is capable of maintaining low average data delays while supporting a large number of simultaneous voice calls. It makes more efficient use of silence suppression than classical time-assignment speech interpolation (TASI). Simulation results are presented and the performance wit... View full abstract»

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  • Macrocell-level compaction with automatic jog introduction

    Publication Year: 1989, Page(s):536 - 539
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A novel algorithm for compacting a VLSI chip on the macrocell level is presented. Compared to previous algorithms, the technique can handle larger designs, produces higher-quality output, and reduces designer intervention as much as possible. Jogs are automatically introduced in the connecting wires to achieve the needed flexibility for placing cells into optimal positions View full abstract»

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  • A design of a memory management unit for object-based systems

    Publication Year: 1989, Page(s):512 - 517
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Object-based operating systems have the desirable property of separating policies from mechanisms while providing a protected procedure call interface for accessing system services. However, the kernel mechanisms in such systems rely very heavily on efficient memory management. A set of criteria for supporting the kernel mechanisms in object-based systems is presented. The design of a simple MMU (... View full abstract»

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  • Generic ASIC architecture for digital signal processing

    Publication Year: 1989, Page(s):82 - 85
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The architectural methodology behind a novel high-level VLSI cell compiler currently under development is described. The tool is aimed specifically at digital signal processing applications, synthesizing powerful arithmetic kernel processors from high-level parameterized schematics. Underlying the tool is a generic pipelined numerical processing architecture, flexible enough in its use of innate p... View full abstract»

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