Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

2-4 Oct. 1989

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Displaying Results 1 - 25 of 116
  • A hierarchical constraint graph generation and compaction system for symbolic layout

    Publication Year: 1989, Page(s):532 - 535
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (378 KB)

    A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in... View full abstract»

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  • Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.89CH2794-6)

    Publication Year: 1989, Page(s): 0_1
    Request permission for commercial reuse | |PDF file iconPDF (920 KB)
    Freely Available from IEEE
  • The channel intersection problem in the building block style layout

    Publication Year: 1989, Page(s):528 - 531
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    A new routing region definition and ordering algorithm are presented for building block layout consisting of rectangular blocks. In contrast to other works, this algorithm enables a router to deal with the channel intersections efficiently, while permitting the expansion of any region when being routed. Before this algorithm is run, it is assumed that proper routing space has been assigned between... View full abstract»

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  • Hamming count-a compaction testing technique

    Publication Year: 1989, Page(s):344 - 347
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (220 KB)

    A signature compaction method called Hamming count (H-count) is introduced. H-count is similar to a reduced Walsh spectral coefficient test, and encompasses all syndrome testable faults. H-count has both a lower masking probability and a simpler circuit design than the index vector test. The method provides an efficient and effective compaction technique View full abstract»

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  • Automatic signal net-matching for VLSI layout design

    Publication Year: 1989, Page(s):524 - 527
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (312 KB)

    In high-speed VLSI design, the matching of signal net lengths is often critical to the proper performance of a circuit. Given a design which specifies groups of signal nets to be matched, a physical layout must be generated which conforms to these constraints. Different aspects of the problem in VLSI design layout are investigated, and the approaches used to automate the process are presented View full abstract»

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  • A low-impedance load detector circuit for optical interconnects

    Publication Year: 1989, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    Optical interconnects provide an alternative for long-distance electrical clock distribution in high-speed VLSI circuits. In an optical interconnect system, the response of the detector circuit is an important factor in determining the speed of the overall system. A simple, low-impedance nMOS detector circuit is presented and modeled for optical interconnect application in CMOS systems. A maximum-... View full abstract»

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  • Testability of digital circuits via the spectral domain

    Publication Year: 1989, Page(s):340 - 343
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (228 KB)

    The authors demonstrate how the spectral testability of digital circuits can be evaluated in the spectral domain using two standard testability measures: controllability and observability. It is shown how these measures are obtained. Software considerations are discussed, and the evaluation of the testability of an SN74181 arithmetic logic chip is given as an example View full abstract»

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  • A module-sliced approach for high yield VLSI/WSI processors

    Publication Year: 1989, Page(s):500 - 503
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (236 KB)

    The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2... View full abstract»

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  • A systolic approach to multistage interconnection network design

    Publication Year: 1989, Page(s):456 - 459
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    An algorithm to map a multistage interconnection network (MIN) onto a systolic array is developed. The algorithm provides a systematic approach that lays out a cube MIN in a compact area. An area-delay analysis is presented and is compared with that of a crossbar. It is shown that the cube MIN performs better than crossbar in both area and delay View full abstract»

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  • Comparison of chip crossing delay in various packaging environments

    Publication Year: 1989, Page(s):233 - 236
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (200 KB)

    The effect of packaging on computer performance is becoming increasingly significant because of delay due to package parasitics and connectivity between functional blocks. The first issue is addressed with an example of how chip crossing delay is influenced by the choice of packaging environment. Five separate packaging technologies are investigated. Simulation of this delay is useful for comparin... View full abstract»

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  • Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture

    Publication Year: 1989, Page(s):580 - 584
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    A unified solution to the problems that arise in the design, development, and test of VLSI processors is offered. The JTAG/IEEE P1149.1 standard boundary-scan architecture is proposed as the basis for designing testable, defect-tolerant, VLSI processors. The test access port (TAP) provided by the boundary-scan architecture is used to control and repair the microprogram control unit, as well as to ... View full abstract»

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  • High performance circuits for the i486 processor

    Publication Year: 1989, Page(s):188 - 192
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    Three high-performance circuit blocks of the i486 processor are described: a large, on-chip cache; a 1× clock generator; and a high-speed, 32-b adder. In addition, a summary of the methodology used to design these circuits are given. The circuit used to regulate the clock duty cycle used a feedback technique to adjust timer delays, preventing clock overlap. The timer circuit uses current mir... View full abstract»

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  • A cached system architecture dedicated for the system IO activity on a CPU board

    Publication Year: 1989, Page(s):518 - 522
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    The architecture of a cached IO subsystem on a CPU board of a high-performance workstation is described. The cached IO subsystem is intended to reduce the memory latency for IO activity and minimize the number of processor cycles stolen by IO traffic, to achieve a better balanced computer system in terms of both the CPU computation power and the system IO bandwidth. The model of the cached IO subs... View full abstract»

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  • HYPER: an interactive synthesis environment for high performance real time applications

    Publication Year: 1989, Page(s):432 - 435
    Cited by:  Papers (37)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    A synthesis system called HYPER is proposed for real-time applications. HYPER takes a flow graph description of an algorithm as the input and performs scheduling, resource allocation, optimizations, and transformations. A dedicated bit-sliced data path cluster is generated by the system and the layouts can be further generated through the LAGER IV system View full abstract»

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  • An integrated free space optical bus

    Publication Year: 1989, Page(s):62 - 65
    Cited by:  Papers (8)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    As integrated circuit linewidths are reduced, single-chip system functionality and speed increase. Conventional electronic chip input/output does not follow this trend: bonding pad sizes and off chip capacitive loads remain essentially constant. Shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by pro... View full abstract»

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  • Logic decomposition algorithms for the timing optimization of multi-level logic

    Publication Year: 1989, Page(s):329 - 333
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    Novel fast decomposition algorithms that rely on precise linear models for gate delays are presented. Within the limits of the models, the algorithm performs locally optimal m-way balanced and unbalanced decompositions of logic gates to achieve a maximal timing gain. The decompositions take the output load into account and are characterized by a near-minimal area increase. The models were... View full abstract»

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  • Frigg: a simulation environment for multiple-processor DSP system development

    Publication Year: 1989, Page(s):280 - 283
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    A simulation environment oriented to the needs of the developer of custom multi-DSP systems has been developed and implemented. The simulator, Frigg, builds on the capabilities of a general-purpose behavioral simulator and manufacturer-supplied processor simulators. Frigg allows a user to simultaneously view the detailed behavior of the hardware and software comprising a complete multiprocessor sy... View full abstract»

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  • Digital and analog integrated-circuit design with built-in reliability

    Publication Year: 1989, Page(s):496 - 499
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB)

    A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated-circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigr... View full abstract»

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  • On a class of (2n-1)-stage rearrangeable interconnection networks

    Publication Year: 1989, Page(s):452 - 455
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    A class of (2n-1)-stage rearrangeable multistage interconnection networks (MINs) that includes all the previously proposed 2n-1 stage MINs as special cases or subsets is proposed. Both permutation routing and generalized distributed tag routing algorithms of this class of MINs are proposed. It is shown that previously proposed routing algorithms for some specific rearrangeable ne... View full abstract»

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  • Integration and packaging plateaus of processor performance

    Publication Year: 1989, Page(s):229 - 232
    Cited by:  Papers (1)  |  Patents (56)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    Integration and packaging performance limits are refined in the context of computer systems. In particular, limits of computer performance under various packaging, architectural, organizational, and design techniques (e.g. gate-array versus custom) are explored. It is concluded that fully integrated processors can have modest electrical signal I/O requirements because the frequency of signals cros... View full abstract»

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  • Mind: a module binder for high level synthesis

    Publication Year: 1989, Page(s):420 - 423
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (240 KB)

    Mind, a module binder for the Bridge synthesis system, is described. The practical considerations for generating production-quality designs are emphasized. These considerations include the separation of single-function and multiple-function ALU (arithmetic and logic unit) generators, the extraction of constant and feedthrough control signals, as well as the incorporation of a net-list post process... View full abstract»

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  • An efficient approach to pseudo-exhaustive test generation for BIST design

    Publication Year: 1989, Page(s):576 - 579
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by... View full abstract»

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  • Intelligent backtracking in test generation for combinational circuits

    Publication Year: 1989, Page(s):48 - 51
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (204 KB)

    An intelligent backtracking algorithm for the test generation of combinational circuits is introduced. This algorithm, called INBACK, differs from PODEM and FAN in that, when a contradiction occurs, it chooses a backtracking element which is most likely to eliminate the contradiction and change its value. An efficient method of identifying such backtracking elements is established. Experiments on ... View full abstract»

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  • Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes

    Publication Year: 1989, Page(s):120 - 123
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    Totally self-checking (TSC) circuits are considered. If the first erroneous output is a noncodeword then the TSC goal is said to be achieved. The author has recently defined a new class of checkers which meet the TSC goal, namely, the strongly self-checking (SSC) checkers. A TSC or SSC checker can be guaranteed to meet the TSC goal if it receives the required set of codeword tests from the functio... View full abstract»

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  • Internal ECL-BiCMOS translator circuits in half micron technology

    Publication Year: 1989, Page(s):314 - 317
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (220 KB)

    BiCMOS associates high-speed circuits with the low power requirements of CMOS. Traditional BiCMOS circuits are mainly CMOS-based with bipolar buffers to improve driving capability and speed. Increased performance can be obtained with BiCMOS technology if CMOS/BiCMOS circuits are merged with an ECL (emitter-coupled logic) low swing circuit. Mixing of logic is possible if very-high-speed level trans... View full abstract»

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