[1989] Proceedings of the 1st European Test Conference

12-14 April 1989

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  • Proceedings of the 1st European Test Conference (IEEE Cat. No.89CH2696-3)

    Publication Year: 1989
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    Freely Available from IEEE
  • Mixed level test generation for MOS circuits

    Publication Year: 1989, Page(s):208 - 211
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    The authors present a test-generation system for combinational circuits described at mixed gate and switch levels. The circuit under test is hierarchically partitioned into blocks characterized by their I/O function. Only the faulty block is eventually expanded to perform fault injection. The algorithm also exploits dynamic partitioning and adaptive backtrace to speed up the test search. Robust te... View full abstract»

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  • Hazards effect on stuck-open fault testability

    Publication Year: 1989, Page(s):201 - 207
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Testing of stuck-open faults requires sequences of input vectors. The authors discuss test invalidation problems produced by hazard switching due to internal delays or timing skews in input changes. To avoid invalidation possibilities in stuck-open fault-test sequences, the proposed solutions lead to structural modifications of the circuit or robust test sequences composed of more than two vectors View full abstract»

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  • Designing mixed-mode test pattern generators for minimum-overhead self-testing VLSI circuits

    Publication Year: 1989, Page(s):409 - 413
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A simple technique for designing self-testable VLSI circuits, characterized by low silicon area overhead and maximum testing speed, is proposed. An original feature of this built-in self-test design technique is a procedure for synthesis of test pattern generators. Its objective is to design mixed-mode generators of minimal complexity that maximize the fault-sensitizing capabilities of test sequen... View full abstract»

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  • New directions in electronics test philosophy, strategy, and tools

    Publication Year: 1989, Page(s):5 - 13
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors review test objectives and related test strategies throughout the life cycle of electronic products, from system design conception to field maintenance. They reinforce the philosophy of integrating test methodology into the design process and outline the organizational responsibilities within the design and development communities. Consideration is given to product objectives and relat... View full abstract»

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  • Test generation for current testing

    Publication Year: 1989, Page(s):194 - 200
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Current testing has been found to be useful for testing CMOS ICs because it can detect a large class of manufacturing defects. The concept of current testing is described; the classes of defects detectable by current testing and the conditions to detect a given defect are described; and a general test-vector generation algorithm for current testing is developed and applied to two examples View full abstract»

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  • Testing and characterization of ASICs by the user

    Publication Year: 1989, Page(s):268 - 275
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The use of simulation data obtained during user development of an application-specific IC (ASIC) to generate a test program is discussed. It is shown that the quality of the test program generated in this way depends on the accuracy of the simulation and the thoroughness of the applied stimuli. The simulation needs to take account of both the tester and the device specifications. The tester impose... View full abstract»

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  • Implementing exhaustive self test using minimal cycle count and reduced area overhead

    Publication Year: 1989, Page(s):403 - 408
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The problem of determining the number of cycles of test-pattern generation required to exhaustively test a block of logic is investigated, considering the case where the generator has more stages than the logic has inputs. Some statistical results are presented, and these are then compared with simulation results. The results show that it is easily possible to simulate the configurations used in c... View full abstract»

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  • Electrical properties and detection methods for CMOS IC defects

    Publication Year: 1989, Page(s):159 - 167
    Cited by:  Papers (86)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees dete... View full abstract»

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  • Debugging integrated circuits: AI can help

    Publication Year: 1989, Page(s):184 - 191
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    An overview of Pesticide, a Prolog-written expert system for integrated-circuit debugging is presented. Pesticide relies on the knowledge of structural and functional properties of both combinational and sequential ICs. Its external environment consists of a scanning electron microscope used in voltage contrast mode and linked to CAD tools. Particular attention is given to the modeling of the devi... View full abstract»

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  • Automatic test program generation for a block oriented VLSI chip design

    Publication Year: 1989, Page(s):71 - 76
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A system for automatic test program generation is presented that is based on a block-oriented chip design. The testability is verified by a test access checker, test patterns are generated by test pattern generators, and everything is linked together by a test assembler to form a complete chip test. The testing part of the system is known as the computer-aided test (CAT) system, and consists of fo... View full abstract»

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  • Fast test method for serial A/D and D/A converters

    Publication Year: 1989, Page(s):262 - 267
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    An efficient test method for so-called serial analog/digital (A/D) and D/A converters which can be executed on digital automated test equipment is described. The method is applicable for stand-alone converters and for mixed-signal devices containing this type of converters. The proposed solution makes use of some special properties of serial converters. The method consists of a measurement of the ... View full abstract»

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  • Built-in self test using perturbed deterministic patterns

    Publication Year: 1989, Page(s):398 - 402
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A built-in self-test method that applies perturbed deterministic patterns (PDPs) generated by an on-chip memory and compresses signatures on-chip is presented. The deterministic patterns are perturbed using a predefined algorithm. Software and hardware implementation in a level-sensitive-scan design environment are described. Using six industrial benchmarks as examples, it is shown that the PDP te... View full abstract»

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  • On the definition of critical areas for IC photolithographic spot defects

    Publication Year: 1989, Page(s):152 - 158
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The model presented is a generalization of existing theory. The sensitive areas are a function of the geometrical patterns in the layers, their electrical significance, their relationship to patterns in other layers, and the defect size. Identifying composite sensitive areas makes it possible to predict the probability of failure of special structures such as transistors and capacitors, which in t... View full abstract»

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  • Acceptance tests of distributed processing orientated supervisory control and data acquisition (SCADA) systems for offshore platforms

    Publication Year: 1989, Page(s):221 - 228
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Higher-level test techniques for acceptance testing are described, and the implications of such testing at various levels are analyzed. Simulated tests involving autonomous interfacing units are also discussed. The testing at the card level is batch-oriented and goes through automated or semiautomated testing schemes View full abstract»

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  • 100 MHz circuit pack test system: a reality

    Publication Year: 1989, Page(s):86 - 93
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A high-performance 100-MHz prototype test system for in-circuit or functional testing of complex high-speed digital circuit packs is described, including the test fixture, pin electronics, and the system software. The high-speed test system (HSTS) uses a high-frequency fixture in which the twisted-wire pair of the conventional fixtures is eliminated by providing a shielded fixed-length and control... View full abstract»

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  • Timing accuracy in VLSI testing

    Publication Year: 1989, Page(s):100 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Timing errors arising during VLSI device testing are reviewed. Particular attention is given to internal tester errors caused by the characteristics of the hardware and the autocalibration procedure used, and application-related errors in DC testing, function testing, and AC testing (testing of dynamic parameters). It is concluded that extremely expensive testers or testers highly geared to specif... View full abstract»

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  • Testability strategy for registers and memories in a multi-processor architecture

    Publication Year: 1989, Page(s):294 - 303
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A testability strategy is presented for registers and memories embedded in multiprocessor chips designed with the Cathedral-II silicon compilation environment. The implementation requires the design of a scan register that is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived.... View full abstract»

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  • Fully-integrated dynamic fault imaging system for failure analysis and performance enhancement of VLSI

    Publication Year: 1989, Page(s):180 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Advances in electron-beam dynamic fault imaging (DFI) are reviewed. DFI is a powerful technique for diagnosing failure mechanisms in VLSI devices, and is particularly helpful in situations where there is little knowledge of the device under test. It provides direct automated comparison of images from a failing die and a fully functional or `golden' die, greatly, increasing diagnosis productivity. ... View full abstract»

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  • Hybrid design of parallel signature analyzers

    Publication Year: 1989, Page(s):354 - 360
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Parallel signature analyzers implemented as multiple-input linear-feedback shift registers (MISRs) are very useful for compressing test response data. The author presents a top-bottom exclusive (TBE) MISR which uses only (t+1)/2 XOR gates, in its linear feedback instead of t XOR gates used in other types of MISRs. An algebraic analysis of the operation and certain analytical resu... View full abstract»

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  • Using hierarchy in macro cell test assembly

    Publication Year: 1989, Page(s):63 - 70
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    Test generation and assembly are investigated for hierarchical VLSI designs of modules with testable macro cells and an associated local controller. To create a testable (a) synchronous controller structure, the use of state cells is proposed. It is shown that a state-cell controller can be tested by reconfiguration into a token scanpath and that because of the direct correspondence between implem... View full abstract»

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  • A fault model for PLAs

    Publication Year: 1989, Page(s):252 - 260
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    A fault model for programmable logic arrays (PLAs) is discussed that handles four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that a test that detects all multiple crosspoint faults also detects all multiple stuck-at faults, multiple bridging faults, and any combination of the above. It is also sh... View full abstract»

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  • Fault simulation for delay faults

    Publication Year: 1989, Page(s):328 - 335
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Methods to quantify the effectiveness of a delay test are presented. The notion of hazard insensitivity, which generalizes the notion of a robust delay test, is used to identify instances of test invalidation due too glitches. The delay fault-simulator is used to evaluate some built-in-self-test (BIST) schemes. The delay-fault simulator is built around a stuck-at fault simulator. This makes the ov... View full abstract»

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  • Pseudoexhaustive test techniques: a new algorithm to partition combinational networks

    Publication Year: 1989, Page(s):392 - 397
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Pseudoexhaustive test techniques based on partition and segmentation are described. These methods provide a higher fault coverage than standard automatic-test-program generation programs, and neither fault simulation nor fault modeling is required. Finding optimal partitions of combinational networks is an np-complete problem; an algorithm based on a heuristic approach that is faster and more reli... View full abstract»

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  • A three-valued fast fault simulator for scan-based VLSI-logic

    Publication Year: 1989, Page(s):41 - 48
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Based on an effective three-valued coding, the methods of two-valued fault simulation are extended to three-valued fault simulation. Solidly and potentially detected faults are considered. Parallel processing of patterns is applied at all stages of the calculation procedure, and the expensive fault simulation is restricted to fanout stems by adopting the concept of fanout-free regions. In addition... View full abstract»

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