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European Test Conference, 1989., Proceedings of the 1st

Date 12-14 April 1989

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Displaying Results 1 - 25 of 58
  • Proceedings of the 1st European Test Conference (IEEE Cat. No.89CH2696-3)

    Publication Year: 1989
    Request permission for commercial reuse | PDF file iconPDF (16 KB)
    Freely Available from IEEE
  • The use of a test specification format in automatic test program generation

    Publication Year: 1989, Page(s):362 - 368
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Test specifications formats (TSFs) to facilitate standardization of testing information on ICs and circuit boards are examined. The author describes the application areas of a TSF and shows the practical use of one particular TSF, the neutral code format (NCF) proposed by C. Mortensen (1987). By writing a translator from NCF to a test programming language, it was seen that automatic test program g... View full abstract»

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  • New directions in electronics test philosophy, strategy, and tools

    Publication Year: 1989, Page(s):5 - 13
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors review test objectives and related test strategies throughout the life cycle of electronic products, from system design conception to field maintenance. They reinforce the philosophy of integrating test methodology into the design process and outline the organizational responsibilities within the design and development communities. Consideration is given to product objectives and relat... View full abstract»

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  • Testability strategy for registers and memories in a multi-processor architecture

    Publication Year: 1989, Page(s):294 - 303
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A testability strategy is presented for registers and memories embedded in multiprocessor chips designed with the Cathedral-II silicon compilation environment. The implementation requires the design of a scan register that is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived.... View full abstract»

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  • 100 MHz circuit pack test system: a reality

    Publication Year: 1989, Page(s):86 - 93
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A high-performance 100-MHz prototype test system for in-circuit or functional testing of complex high-speed digital circuit packs is described, including the test fixture, pin electronics, and the system software. The high-speed test system (HSTS) uses a high-frequency fixture in which the twisted-wire pair of the conventional fixtures is eliminated by providing a shielded fixed-length and control... View full abstract»

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  • Easily testable iterative unidimensional CMOS circuits

    Publication Year: 1989, Page(s):240 - 245
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The C-testability of combinational unidimensional iterative circuits implemented in CMOS technology is discussed. In this technology the stuck-open faults impose additional requirements beyond the usual C-testability conditions. The requirements are considered for the classical adder and incrementer circuits, and these circuits are shown to be potentially C-testable even when stuck-open faults are... View full abstract»

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  • Hybrid design of parallel signature analyzers

    Publication Year: 1989, Page(s):354 - 360
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Parallel signature analyzers implemented as multiple-input linear-feedback shift registers (MISRs) are very useful for compressing test response data. The author presents a top-bottom exclusive (TBE) MISR which uses only (t+1)/2 XOR gates, in its linear feedback instead of t XOR gates used in other types of MISRs. An algebraic analysis of the operation and certain analytical resu... View full abstract»

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  • The testability of a modified Booth multiplier

    Publication Year: 1989, Page(s):286 - 293
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The author describes the generation of the test view of a multiplier-accumulator based on a modified Booth algorithm. It is shown that an algorithm can be found that rapidly generates the test patterns as a function of the parameters of the module. The fault model used is an extension of the traditional stuck-at model switch-level faults occurring in pass transistor logic. To achieve full testabil... View full abstract»

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  • How to treat transmission line effects when testing high speed devices with a high performance test system

    Publication Year: 1989, Page(s):78 - 85
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    State-of-the-art digital ASICs have even faster clock rates and signal transition times; testing these devices may cause problems regarding delivering the signals to the device under test (DUT) and precisely measuring the response of the DUT. Transmission-line techniques have to be applied to the tester-to-DUT interconnection in order to maintain signal fidelity. The author illustrates how to impl... View full abstract»

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  • Hierarchical testability measurement and design for test selection by cost prediction

    Publication Year: 1989, Page(s):50 - 57
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Problems associated with test costs for complex electronic systems are discussed and a test strategy planner (TSP) is proposed which uses cost prediction throughout each design stage of a product to analyze the test costs and suggest methods of reducing the total product cost by design for test (DFT) choices. The TSP described is aimed at DFT applied to large integrated circuits designed within a ... View full abstract»

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  • UUT and model data for multiple test-techniques

    Publication Year: 1989, Page(s):229 - 237
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Techniques for constructing a single description of the unit under test (UUT) for use with multiple test methods are proposed. They conclude a consistent user interface, a set of library and model tools, and a coherent set of data structures. The board and library software provide: an interface for use in bulk loading of board data; interactive software tools to allow modification and correction o... View full abstract»

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  • Aliasing in signature analysis testing with multiple-input shift-registers

    Publication Year: 1989, Page(s):346 - 353
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Signature analysis with multiple-input shift registers (MISRs) is often used to realize efficient built-in self-test of digital VLSI circuits. The authors present a statistical theory that explains the dependence of aliasing probability on the main MISR features, such as length and feedback network, and thus makes it possible to prove criteria for the MISR design. The assumption of independent err... View full abstract»

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  • Test and screening strategies for large memories

    Publication Year: 1989, Page(s):276 - 283
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    The possibilities and limits of testing and screening large memories are reviewed. Practical results are given. The procedures for the qualification test of different types of memories are discussed. The concept of test strategy is introduced. Future trends in testing large memories are presented. It is shown that AC, functional, and DC test should be performed under several different conditions t... View full abstract»

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  • An expert system for the functional specification of test programs

    Publication Year: 1989, Page(s):383 - 390
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    The design concept and implementation of a knowledge-based test-strategy specification tool for logic systems are described. The test strategy selects the subset of functions that is required to ensure the test of all hardware primitives and to provide an order for the application of those functions. This process results in the functional specification of the test program. The structure of the kno... View full abstract»

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  • Are random vectors useful in test generation?

    Publication Year: 1989, Page(s):22 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Most automatic test generation systems start by generating random vectors, then switch to a fault-oriented algorithm which targets the remaining undetected faults. Experimental results are presented which show that, for most circuits, using random vectors increases both the total test generation time and the total number of tests. This is true not only for random-pattern resistant circuits, but al... View full abstract»

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  • Automatic test program generation for a block oriented VLSI chip design

    Publication Year: 1989, Page(s):71 - 76
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A system for automatic test program generation is presented that is based on a block-oriented chip design. The testability is verified by a test access checker, test patterns are generated by test pattern generators, and everything is linked together by a test assembler to form a complete chip test. The testing part of the system is known as the computer-aided test (CAT) system, and consists of fo... View full abstract»

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  • A three-valued fast fault simulator for scan-based VLSI-logic

    Publication Year: 1989, Page(s):41 - 48
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Based on an effective three-valued coding, the methods of two-valued fault simulation are extended to three-valued fault simulation. Solidly and potentially detected faults are considered. Parallel processing of patterns is applied at all stages of the calculation procedure, and the expensive fault simulation is restricted to fanout stems by adopting the concept of fanout-free regions. In addition... View full abstract»

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  • Acceptance tests of distributed processing orientated supervisory control and data acquisition (SCADA) systems for offshore platforms

    Publication Year: 1989, Page(s):221 - 228
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Higher-level test techniques for acceptance testing are described, and the implications of such testing at various levels are analyzed. Simulated tests involving autonomous interfacing units are also discussed. The testing at the card level is batch-oriented and goes through automated or semiautomated testing schemes View full abstract»

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  • Aliasing errors in multiple input signature analysis registers

    Publication Year: 1989, Page(s):338 - 345
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Aliasing errors in linear feedback shift registers used as multiple-input signature-analysis registers (MISARs) for self-testing networks are investigated analytically. The authors derive the final value for aliasing errors for a MISAR with the same probability of an error on each of the different inputs. They also derive the final value for aliasing with the same register if there are different p... View full abstract»

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  • Hazards effect on stuck-open fault testability

    Publication Year: 1989, Page(s):201 - 207
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Testing of stuck-open faults requires sequences of input vectors. The authors discuss test invalidation problems produced by hazard switching due to internal delays or timing skews in input changes. To avoid invalidation possibilities in stuck-open fault-test sequences, the proposed solutions lead to structural modifications of the circuit or robust test sequences composed of more than two vectors View full abstract»

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  • Testing and characterization of ASICs by the user

    Publication Year: 1989, Page(s):268 - 275
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The use of simulation data obtained during user development of an application-specific IC (ASIC) to generate a test program is discussed. It is shown that the quality of the test program generated in this way depends on the accuracy of the simulation and the thoroughness of the applied stimuli. The simulation needs to take account of both the tester and the device specifications. The tester impose... View full abstract»

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  • Testability measures with concurrent good simulation

    Publication Year: 1989, Page(s):144 - 149
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Methods designed to speed up the computation of controllability within an event-driven fault-free simulation environment are described. Input generation techniques are presented which reduce the activity of the simulator, thus achieving a considerable speed-up. Concurrent simulation of fault-free devices is shown to be very effective in this domain. Experimental results are reported for benchmark ... View full abstract»

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  • Separating timing, data, and format in a tester-independent waveform representation

    Publication Year: 1989, Page(s):377 - 382
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a tester-independent representation for digital waveforms which permits the separate manipulation of timing, data and format. This object-oriented approach is compact, extensible, and independent of tester architecture while still permitting the representation of a variety of tester featured such as multiclock modes, multiplex modes, and midcycle I/O transitions. Several examp... View full abstract»

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  • ATE and quality-an user's view

    Publication Year: 1989, Page(s):18 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    The test strategy for a manufacturer of a high-technology electronic system is directly related to a more general strategy involving the implementation of industrial means to reach high-level quality standards. To meet these quality standards, quality-improvement programs involving the whole personnel as well as the manufacturing processes are considered more efficient than systematic sorting. The... View full abstract»

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  • High-level test generation for sequential circuits

    Publication Year: 1989, Page(s):314 - 321
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    An algorithm is presented for VLSI-circuit test-data transport at high levels of abstraction above gate-level. It can be used in the course of the test-pattern lift proposed by H. Hofestadt and M. Gerner (1987) for generating tests of sequential circuits. A precondition for its efficient use is a circuit under test without critical feedback cycles. Thus, an important aspect of the test strategy-th... View full abstract»

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