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European Test Conference, 1989., Proceedings of the 1st

Date 12-14 April 1989

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Displaying Results 1 - 25 of 58
  • Proceedings of the 1st European Test Conference (IEEE Cat. No.89CH2696-3)

    Publication Year: 1989
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    Freely Available from IEEE
  • Aliasing errors in multiple input signature analysis registers

    Publication Year: 1989 , Page(s): 338 - 345
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    Aliasing errors in linear feedback shift registers used as multiple-input signature-analysis registers (MISARs) for self-testing networks are investigated analytically. The authors derive the final value for aliasing errors for a MISAR with the same probability of an error on each of the different inputs. They also derive the final value for aliasing with the same register if there are different probability values of an error on each of the different inputs. This analysis assumes that the different inputs are all independent of one another. The analysis is based on the Markov model. In either case, the final value is shown to be 1/2k where k is the length of the shift register View full abstract»

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  • Easily testable iterative unidimensional CMOS circuits

    Publication Year: 1989 , Page(s): 240 - 245
    Cited by:  Papers (7)
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    The C-testability of combinational unidimensional iterative circuits implemented in CMOS technology is discussed. In this technology the stuck-open faults impose additional requirements beyond the usual C-testability conditions. The requirements are considered for the classical adder and incrementer circuits, and these circuits are shown to be potentially C-testable even when stuck-open faults are taken into account. C-testable sets of test patterns that detect all the single stuck-open and all the single stuck-at faults are presented. Results for Moore-type sequential iterative circuits are also presented View full abstract»

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  • Aliasing in signature analysis testing with multiple-input shift-registers

    Publication Year: 1989 , Page(s): 346 - 353
    Cited by:  Papers (18)
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    Signature analysis with multiple-input shift registers (MISRs) is often used to realize efficient built-in self-test of digital VLSI circuits. The authors present a statistical theory that explains the dependence of aliasing probability on the main MISR features, such as length and feedback network, and thus makes it possible to prove criteria for the MISR design. The assumption of independent errors at the register inputs is used to model the register behavior as a Markov process, whose equations are then solved to obtain the exact dependence of aliasing probability as a function of test length, input error probabilities, and feedback structure View full abstract»

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  • Testability design for PLA-implemented finite state machine

    Publication Year: 1989 , Page(s): 246 - 251
    Cited by:  Papers (2)
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    Design-for-testability (DFT) techniques are presented for the finite state machine implemented in programmable logic arrays (PLAs). The proposed techniques are developed from physical, electrical and functional points of view. Within the framework of deterministic test, these DFT techniques make the fault under consideration either unlikely to occur, equivalent to other faults, or more easily testable. They allow a significant reduction in fault locations and in fault models. A detailed example illustrates the proposed techniques, highlighting the improvements. It is shown that specific DFT techniques developed for regular structures allow the automatic generation of easily testable functional blocks. For CMOS PLA, the test sequence is reduced in such a way that the automatic generation of self-testable finite-state machines is possible View full abstract»

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  • Timing accuracy in VLSI testing

    Publication Year: 1989 , Page(s): 100 - 104
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    Timing errors arising during VLSI device testing are reviewed. Particular attention is given to internal tester errors caused by the characteristics of the hardware and the autocalibration procedure used, and application-related errors in DC testing, function testing, and AC testing (testing of dynamic parameters). It is concluded that extremely expensive testers or testers highly geared to specific characteristics are not necessarily the most economical or most cost-effective solution, not even for standard applications View full abstract»

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  • ATE and quality-an user's view

    Publication Year: 1989 , Page(s): 18 - 19
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    The test strategy for a manufacturer of a high-technology electronic system is directly related to a more general strategy involving the implementation of industrial means to reach high-level quality standards. To meet these quality standards, quality-improvement programs involving the whole personnel as well as the manufacturing processes are considered more efficient than systematic sorting. These programs affect the test implementation and impose two contradictory demands: new products use new technologies stimulating the use of increasingly sophisticated automatic test equipment (ATE), but older products, or fielded products, favor the retention of obsolete ATE due to the cost and difficulty of transposing data between ATE from different generations. It is felt that the issue of supporting obsolete (or at least not state-of-the-art) ATE will exist until this problem is solved View full abstract»

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  • The use of a test specification format in automatic test program generation

    Publication Year: 1989 , Page(s): 362 - 368
    Cited by:  Papers (8)
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    Test specifications formats (TSFs) to facilitate standardization of testing information on ICs and circuit boards are examined. The author describes the application areas of a TSF and shows the practical use of one particular TSF, the neutral code format (NCF) proposed by C. Mortensen (1987). By writing a translator from NCF to a test programming language, it was seen that automatic test program generation is possible. It is found, however, that only GO/NOGO test programs could be generated View full abstract»

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  • Hazards effect on stuck-open fault testability

    Publication Year: 1989 , Page(s): 201 - 207
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    Testing of stuck-open faults requires sequences of input vectors. The authors discuss test invalidation problems produced by hazard switching due to internal delays or timing skews in input changes. To avoid invalidation possibilities in stuck-open fault-test sequences, the proposed solutions lead to structural modifications of the circuit or robust test sequences composed of more than two vectors View full abstract»

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  • Are random vectors useful in test generation?

    Publication Year: 1989 , Page(s): 22 - 25
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    Most automatic test generation systems start by generating random vectors, then switch to a fault-oriented algorithm which targets the remaining undetected faults. Experimental results are presented which show that, for most circuits, using random vectors increases both the total test generation time and the total number of tests. This is true not only for random-pattern resistant circuits, but also for circuits where random vectors easily achieve high fault coverage. Running only a fault-oriented algorithm that selects its next target as close as possible to primary inputs, and coupling it with random fill, is more efficient than a two-phase strategy using random vectors in phase one View full abstract»

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  • Fast test method for serial A/D and D/A converters

    Publication Year: 1989 , Page(s): 262 - 267
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    An efficient test method for so-called serial analog/digital (A/D) and D/A converters which can be executed on digital automated test equipment is described. The method is applicable for stand-alone converters and for mixed-signal devices containing this type of converters. The proposed solution makes use of some special properties of serial converters. The method consists of a measurement of the output quantity at a number of stationary inputs, distributed over a full input range. The static transfer curve is determined by a number of DC measurements. An accurate DC source is required for testing the sigma-delta modulators, and a low-speed digitizer is needed for the serial D/A. In addition, simple computations must be performed on the acquired data (Fourier transforms are not necessary). A reduction of test time and computational effort is claimed, still giving sufficient information on gain, offset, noise and distortion View full abstract»

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  • Hybrid design of parallel signature analyzers

    Publication Year: 1989 , Page(s): 354 - 360
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    Parallel signature analyzers implemented as multiple-input linear-feedback shift registers (MISRs) are very useful for compressing test response data. The author presents a top-bottom exclusive (TBE) MISR which uses only (t+1)/2 XOR gates, in its linear feedback instead of t XOR gates used in other types of MISRs. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a TBE-type MISR are included View full abstract»

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  • UUT and model data for multiple test-techniques

    Publication Year: 1989 , Page(s): 229 - 237
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    Techniques for constructing a single description of the unit under test (UUT) for use with multiple test methods are proposed. They conclude a consistent user interface, a set of library and model tools, and a coherent set of data structures. The board and library software provide: an interface for use in bulk loading of board data; interactive software tools to allow modification and correction of the board and device descriptions; mechanisms for test preparation tools to be used to select data from the library; and facilities to allow the user to create special versions of models for use in the preparation and running of test data for a single board View full abstract»

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  • Debugging integrated circuits: AI can help

    Publication Year: 1989 , Page(s): 184 - 191
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    An overview of Pesticide, a Prolog-written expert system for integrated-circuit debugging is presented. Pesticide relies on the knowledge of structural and functional properties of both combinational and sequential ICs. Its external environment consists of a scanning electron microscope used in voltage contrast mode and linked to CAD tools. Particular attention is given to the modeling of the device under test, the strategies adopted for fault detection and localization within the circuit under test, and some simple execution examples View full abstract»

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  • New directions in electronics test philosophy, strategy, and tools

    Publication Year: 1989 , Page(s): 5 - 13
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    The authors review test objectives and related test strategies throughout the life cycle of electronic products, from system design conception to field maintenance. They reinforce the philosophy of integrating test methodology into the design process and outline the organizational responsibilities within the design and development communities. Consideration is given to product objectives and related test requirements; test economics; test objectives and test activities; structural, functional, application-mode, and characterization testing; design for testability techniques; the test tool box; and test program generation View full abstract»

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  • Hierarchical fault simulation in combinational circuits

    Publication Year: 1989 , Page(s): 33 - 40
    Cited by:  Papers (5)
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    A method is presented for speeding up fault simulation in combinational circuits by taking advantage of a hierarchical circuit description. The parallel-pattern single-fault-propagation technique is combined with the concept of fanout-free regions, and this approach is then extended to exploit hierarchy. A number of illustrative experiments demonstrate the efficiency of the proposed method and substantiate the gains in simulation speed. Besides the savings in CPU time, the method results in a significant reduction in the memory requirements for creating and maintaining the computational model of the circuit to be simulated View full abstract»

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  • A switching criterion for hybrid ATPG

    Publication Year: 1989 , Page(s): 26 - 32
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    Test pattern generation for VLSI circuits is typically performed in a hybrid environment of different automatic test pattern generation (ATPG) programs of different levels of sophistication. Here, the problem of balancing the computational load between fault simulation and conventional ATPG is addressed. A criterion for switching from fault simulation to deterministic ATPG is derived. The criterion is based on a model of monitoring the simulation process and online estimating the fault detection probabilities. Based on these probabilities a decision is made as to whether it is more advantageous to proceed with fault simulation or to switch to deterministic ATPG. For a prototype implementation of the hybrid ATPG system, significant savings in test preparation time have been measured View full abstract»

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  • Testability measures with concurrent good simulation

    Publication Year: 1989 , Page(s): 144 - 149
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    Methods designed to speed up the computation of controllability within an event-driven fault-free simulation environment are described. Input generation techniques are presented which reduce the activity of the simulator, thus achieving a considerable speed-up. Concurrent simulation of fault-free devices is shown to be very effective in this domain. Experimental results are reported for benchmark circuits. No general law has been derived, but a rich set of heuristics has been collected which may be useful in many other cases View full abstract»

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  • Estimate of signal probability in combinational logic networks

    Publication Year: 1989 , Page(s): 132 - 138
    Cited by:  Papers (47)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency View full abstract»

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  • Testing regular arrays: the boundary problem

    Publication Year: 1989 , Page(s): 304 - 311
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    The authors present a unifying approach to the testing of fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. It includes the often overlooked but nontrivial problem of observing the fault effects, especially at the edges of the arrays. The problems and possible solutions are illustrated using the example of a systolic correlator View full abstract»

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  • Cerberus: hierarchical DFT rule checker

    Publication Year: 1989 , Page(s): 58 - 62
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices. Cerberus utilizes a general approach to testability rule checking and is part of a computer-aided engineering system to integrate design and test. Cerberus consists of the following components: an extractor to provide a levelized directed graph representation from a circuit netlist, a preprocessor to provide acyclic graphs and for topological sorting of circuit nodes, a rule checker nucleus to perform the DFT verification process hierarchically, and a protocol generator to output the rule-checker results in a user-friendly representation View full abstract»

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  • Test preparation and fault analysis using a bottom-up methodology

    Publication Year: 1989 , Page(s): 168 - 174
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    The testing methodology for digital VLSI circuits proposed by J.P. Teixeira et al. (1988) is based on the automatic definition of a realistic fault list which depends on the technology, the manufacturing process, and the IC layout. The proposed methodology is extended to include an initial stage of test preparation during the top-down design phase. In this step, an initial test-pattern generation is performed, to be used for test refinement during the bottom-up verification phase. Fault collecting is done by means of a hierarchical layout-to-fault extractor based on the physical failures most likely to occur in MOS designs. Fault list compression is performed, according to user-defined fault listing objectives, by means of a postprocessor. Test vectors derived by means of a gate-level automatic test-pattern generator are validated by using a concurrent switch-level fault simulator. The visualization of undetected faults in the layout is made possible by means of a graphite display facility View full abstract»

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  • Mixed level test generation for MOS circuits

    Publication Year: 1989 , Page(s): 208 - 211
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    The authors present a test-generation system for combinational circuits described at mixed gate and switch levels. The circuit under test is hierarchically partitioned into blocks characterized by their I/O function. Only the faulty block is eventually expanded to perform fault injection. The algorithm also exploits dynamic partitioning and adaptive backtrace to speed up the test search. Robust tests for stuck-open faults are derived with the help of a ternary simulation technique. Preliminary results show that on large circuits a saving of an order of magnitude can be expected in CPU time when compared with performance on a flat gate-level implementation View full abstract»

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  • Design and implementation of a hierarchical testable architecture using the boundary scan standard

    Publication Year: 1989 , Page(s): 112 - 118
    Cited by:  Papers (3)  |  Patents (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail View full abstract»

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  • Designing mixed-mode test pattern generators for minimum-overhead self-testing VLSI circuits

    Publication Year: 1989 , Page(s): 409 - 413
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    A simple technique for designing self-testable VLSI circuits, characterized by low silicon area overhead and maximum testing speed, is proposed. An original feature of this built-in self-test design technique is a procedure for synthesis of test pattern generators. Its objective is to design mixed-mode generators of minimal complexity that maximize the fault-sensitizing capabilities of test sequences produced within the allowable test running time. The approach does not require that any internal register of the original circuit be modified, and the built-in test control logic is extremely simple. Applying test patterns on consecutive clock cycles with the normal-operation clock frequency leads to substantial enhancement of dynamic fault-detection capabilities View full abstract»

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