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Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on

Date 22-24 March 1989

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Displaying Results 1 - 25 of 110
  • Eighth Annual International Phoenix Conference on Computers and Communications. 1989 Conference Proceedings (Cat. No.89CH2713-6)

    Publication Year: 1989
    Request permission for commercial reuse | PDF file iconPDF (19 KB)
    Freely Available from IEEE
  • Unanticipated behavior as a cue for system-level diagnosis

    Publication Year: 1989, Page(s):4 - 8
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A general method is described for detecting and using unanticipated or surprise events for system-level diagnosis. The author describes an approach which uses these ideas in controlling resource utilization for an intelligent diagnostic system whose immediate application is real-time diagnosis of communication networks. The system is in 24-hr, real-time operation and has been used successfully in ... View full abstract»

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  • Use of A*N+B codes for fault-tolerant bit-serial array processors

    Publication Year: 1989, Page(s):9 - 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (497 KB)

    An approach to error detection in bit-serial array processors based on coding is presented. The optimal choice of such a code is also discussed. Methodologies to design array processors with high error-detection capability, low silicon area consumption, and low computational overhead are proposed and evaluated. A*N+B coding is considered both at a local and array level. In the first case each proc... View full abstract»

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  • An echo-back protocol for a fault tolerant bus architecture

    Publication Year: 1989, Page(s):14 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (489 KB)

    A bus protocol for detecting and avoiding latent faults and multiple faults on buses is presented. The hardware overhead is small, and the design is easily implementable by extensions to existing bus systems. The theoretical maximum performance degradation can be up to 33% in communication bound tasks if no other activity interferes with the operation of the system. The results of the simulation, ... View full abstract»

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  • Fault tolerance and reliable routing in augmented hypercube architectures

    Publication Year: 1989, Page(s):19 - 23
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (501 KB)

    Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the presence of faults is accomplished by distributed algorithms that deliver messages reliably to their destination nodes. A message destined to a faulty node will be delivered to the spare... View full abstract»

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  • A shared-memory multiprocessor logic simulator

    Publication Year: 1989, Page(s):26 - 28
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (213 KB)

    A simple multiprocessor logic simulation kernel is described and preliminary benchmark results presented. Communication between processors is through shared global memory, with locking/unlocking provided by the host operating system. Partitioning the gate evaluation list and current event queue among processors gives a dynamic self-balancing effect which tends to evenly distribute the load associa... View full abstract»

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  • Using simulation and Markov modeling to select data flow threads

    Publication Year: 1989, Page(s):29 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB)

    An algorithm is provided to give the set of all maximal sequential partitionings for a data-flow graph. Selecting an optimal partitioning from this set is incomputable. The authors explore two heuristics for selecting a partitioning: typical instance simulation and Markov analysis. In the two programs they tried, Markov heuristic selected the same partitionings as typical-instance simulation. Sele... View full abstract»

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  • On a cyclic multiqueue with customer's thinking process

    Publication Year: 1989, Page(s):34 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    A symmetric multiqueue with Poisson arrival and an exponential customer thinking processor is analyzed under the so-called independent hypothesis. With generating functions for the probability of the number of waiting customers, a mean waiting time is obtained by using the occupation time and approximate-cycle-time distribution. Some numerical examples for the mean waiting time are given along wit... View full abstract»

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  • On the mapping problem using simulated annealing

    Publication Year: 1989, Page(s):40 - 44
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB)

    Mapping a problem graph of communicating tasks onto a network graph of processing elements so that the communication distance is minimized and the problem graph is evenly distributed over the network, is an NP-complete problem. The authors demonstrate that an approximation technique called simulated annealing can be applied to find acceptable solutions to this problem. For this purpose, they first... View full abstract»

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  • Noise reduction during digital signal generation

    Publication Year: 1989, Page(s):45 - 48
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB)

    Quantitative methods are presented for ensuring that the digital oscillator noise introduced into a digital signal generation circuit is below the quantization error of the digital-to-analog converter (DAC), and will thus not affect system performance. An overview of digital methods of generating RF waveforms is also presented. It is shown that careful selection of computer algorithms and attentio... View full abstract»

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  • A bit-level pipelined implementation of a CMOS multiplier-accumulator using a new pipelined full-adder cell design

    Publication Year: 1989, Page(s):49 - 53
    Cited by:  Papers (3)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB)

    A bit-level pipelined 12*12-bit two's-complement multiplier with a 27-bit accumulator has been designed for applications in high-speed digital communication systems. A new quasi n-p domino logic structure has been investigated and adopted in this multiplier-accumulator design. When used in fully-pipelined circuits, this logic structure results in a much shorter propagation delay in comparison with... View full abstract»

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  • A VLSI architecture for bicubic surface patch image generation

    Publication Year: 1989, Page(s):54 - 58
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB)

    A VLSI architecture is presented for generating ray-tracing images of bicubic surface in Bezier form by using the subdivision algorithm. It uses a set of tree transverse operators to find the nearest intersection between a surface patch and a ray by traversing the entire subdivision tree in preorder. This scheme retains the advantage of subdivision and substantially reduces the circuit area by eli... View full abstract»

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  • Performance analysis of the OPTIMUL multiprocessor interconnect

    Publication Year: 1989, Page(s):60 - 63
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB)

    A description is given of a interconnect called OPTIMUL. The central feature is an optical processor-memory channel, which allows simultaneous access of a memory chip, both with respect to all bits in the chip, and, in tightly coupled systems, with respect to all processors. The authors present a simulation analysis of the performance of a specific multiprocessor based on this technology.<> View full abstract»

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  • Effect of the interprocessor communication mechanism on performance of a parallel processor system

    Publication Year: 1989, Page(s):64 - 68
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The effect of the interprocessor communication (IPC) mechanism on system performance in a multiple-instruction-stream-multiple-data-stream (MIMD) parallel-processor system is investigated. The architecture and a high-level implementation are specified for a parallel-processor system which uses multiple horizontal and vertical buses to interconnect processing elements. A software simulator is devel... View full abstract»

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  • Hardware rollback recovery schemes for multiprocessor systems

    Publication Year: 1989, Page(s):69 - 73
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (407 KB)

    Two rollback recovery schemes are proposed for tolerating transient and permanent faults, respectively. In both schemes a system state is saved in parallel with process execution periodically and automatically by dedicated hardware. The performance of proposed recovery schemes is studied. Closed-form expressions of the mean and variance of a task execution time are derived.<> View full abstract»

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  • Systolic RNS arithmetic using feedback shift logic

    Publication Year: 1989, Page(s):74 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB)

    The author presents an alternative architecture for the arithmetic units in pipelined residue-number-system applications. This architecture uses feedback shift logic to implement residue adders and multipliers, together with novel data representations derived from the multiplicative group of finite rings. Each stage can be implemented with only one exclusive-OR delay. Thus this architecture shows ... View full abstract»

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  • Detection of upset induced execution errors in microprocessors

    Publication Year: 1989, Page(s):82 - 86
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB)

    The authors discuss the types of errors in a radiation environment and propose fault models for instruction execution errors. A scheme is suggested for detecting execution errors through the online monitoring of the system. The theoretical estimate for the error coverage of the proposed scheme is about 85% of all single-bit errors in an instruction word. The exact error coverage will vary as it de... View full abstract»

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  • Project AX: an automatic schematic design system. I. Interactive transistor placement

    Publication Year: 1989, Page(s):87 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB)

    Based on mode structure analysis, circuit patterns, and human factors, the authors are building a high speed placement system which follows the practical circuit design procedures for CMOS digital/analog circuits at the transistor level. Built on top of the X window, the system provides a highly automatic, interactive graphics editor with modularity and easily added-on features. The node-based str... View full abstract»

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  • A unified bit-parallel arithmetic processor using redundant binary representation

    Publication Year: 1989, Page(s):91 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (363 KB)

    An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combining all the MSD-first arithmetic operations, a unifi... View full abstract»

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  • An augmented torus processing surface for MIMD

    Publication Year: 1989, Page(s):97 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB)

    The torus processing surface has been introduced and analyzed by A.J. Martin and C.H. Sequin (1981). An augmented torus processing surface is proposed and operated as a message-passing MIMD machine. The augmented torus is obtained by drawing the torus as a mesh with end-around connections in each row and each column and then augmenting each row and column with a row bus and column bus, respectivel... View full abstract»

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  • Towards a synthesis of direct and indirect cube structures for multiprocessors

    Publication Year: 1989, Page(s):102 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB)

    The author characterizes the exact structural relationship between the hypercube and the multistage indirect n-cube network, two popular interconnection structures for multiprocessors. He shows that the multistage networks can be viewed as direct connections of nodes (each node being a process-memory-switch combination) and that all of the performance difference between the two interconnection sch... View full abstract»

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  • Performance analysis of degradable multiprocessor systems

    Publication Year: 1989, Page(s):109 - 113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB)

    A method for performance evaluation of degradable multiprocessor systems with random failure and repair using hierarchical generalized stochastic Petri net (GSPN) model is presented. The failure and repair rates in a multiprocessor system are an order of magnitude smaller than the rates of job arrival and completion; therefore, the GSPN model can be decomposed into a hierarchical sequence of aggre... View full abstract»

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  • A new strategy for processors allocation in an N-cube multiprocessor

    Publication Year: 1989, Page(s):114 - 118
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB)

    A description is given of two known strategies for static-processor allocation in an n-cube multiprocessor, namely, the buddy-system strategy and the gray-code strategy. A strategy is proposed that outperforms the first by (n-k+1) and the second by (n-k+1)/2 in a cube recognition. The authors' strategy is suitable for static as well as dynamic processor allocation, and it results in less system fr... View full abstract»

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  • Limited service token ring with local message priorities

    Publication Year: 1989, Page(s):122 - 126
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB)

    A symmetric limited-service token-ring network is considered. Messages in a station are served with a priority structure. For all priority classes, the message arrivals are assumed to be identically distributed with no further restriction on the type of the distribution. First a nonpriority-limited-service network is studied. Using an auxiliary variable, virtual service time, the model is transfor... View full abstract»

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  • Distributed reconfiguration algorithm for a unidirectional optical bus local area network

    Publication Year: 1989, Page(s):127 - 132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    A distributed algorithm to reconfigure a unidirectional optical-bus local-area network following topological changes, giving protection against any kind and number of faults, is presented. A sequence of operations is introduced based on which a system configuration is established, allowing information exchange between live stations. The faulty element is detected and isolated from the network, and... View full abstract»

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