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[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

3-6 Jan. 1989

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  • Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Vol.I: Architecture Track (IEEE Cat. No. 89TH0242-8)

    Publication Year: 1989
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    Freely Available from IEEE
  • High-performance architectures

    Publication Year: 1989, Page(s):252 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The author discusses the following architectures: mini-supercomputers; super-minicomputers; and high performance workstations. Such systems are becoming increasingly important in applications ranging from transaction processing to modeling physical systems, and are blurring the traditional performance/price hierarchy of minicomputers, mainframes, and traditional supercomputers View full abstract»

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  • HP Precision: a spectrum architecture

    Publication Year: 1989, Page(s):242 - 251 vol.1
    Cited by:  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    The author discusses the Hewlett-Packard Precision architecture, which was designed as a common architecture for HP computer systems. It has a RISC (reduced-instruction-set computer)-like execution model, with features for code compaction and execution time reduction for frequent instruction sequences. In addition, it has features for making the architecture extendible, for enhancing its longevity... View full abstract»

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  • NS32532: case study in general-purpose microprocessor design tradeoffs

    Publication Year: 1989, Page(s):230 - 241 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    The NS32532, a third-generation 32-bit microprocessor, is used to examine the effect of the constraints of VLSI semiconductor and packaging technologies, as well as those stemming from the wide variety of systems to which the processor will be applied, on design. Its microarchitecture, fabrication technology, system interface, and design methodology are discussed. The design tradeoffs are consider... View full abstract»

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  • Cedar architecture and its software

    Publication Year: 1989, Page(s):306 - 315 vol.1
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    The Cedar system is clustered shared-memory multiprocessor system. The architecture and the main system features of the Cedar system were designed to meet the following goals: (1) to be a general-purpose high-performance machine for parallel processing; (2) to be scalable both architecturally and physically to a very large system; and (3) to be easy to program with a good environment for user supp... View full abstract»

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  • Integrated circuit design productivity advancements in the 1980s and 1990s

    Publication Year: 1989, Page(s):74 - 81 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade View full abstract»

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  • Diffractive optical elements

    Publication Year: 1989, Page(s):440 - 444 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Diffractive optical elements that can be used to manipulate the amplitude, phase, and polarization of a wavefront in very complex ways are treated. Optical components whose feature size is larger than one wavelength, about equal to one wavelength, and smaller than one wavelength are considered. The analytical development that describes these elements is outlined View full abstract»

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  • Design of the Titan graphics supercomputer

    Publication Year: 1989, Page(s):223 - 229 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The Titan was intended to be a personal visualization tool, i.e. a machine that would allow an engineer or scientist to model a physical entity and then visualize the results of the model. This was achieved by the use of several technologies, namely, dense CMOS gate arrays, a commercial RISC IPU (reduced-instruction-set computer instruction processing unit), and pipelinable floating-point units, a... View full abstract»

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  • Application-transparent process-level error recovery for multicomputers

    Publication Year: 1989, Page(s):296 - 305 vol.1
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    An application-transparent, process-level, distributed error recovery scheme for multicomputers is proposed. Checkpointing is initiated by timers at intervals determined by the needs of the application. Checkpointing and recovery involve only as much of the system as is necessary: a set of interacting processes. Processes that are not part of the interacting set do not participate in checkpointing... View full abstract»

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  • Towards a consistent view of the design tools and process in distributed problem solving environment

    Publication Year: 1989, Page(s):29 - 38 vol.1
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    A description is given of the issues encountered in generating an integrated design environment (IDE) based on the DEMETER workbench (DWB) and PIE (a parallel programming and instrumentation environment for UNIX machines). Some of the reasons for using a general integration methodology are explained. DEMETER, which supports complexity reduction, CAD tools management and manipulation, and distribut... View full abstract»

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  • Space-variant optical parallel logic gate technique and its application to cellular logic architectures

    Publication Year: 1989, Page(s):460 - 468 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A general approach is described for optically implementing massively parallel logic. A space-variant logic related to the MIMD (multiple-instruction-multiple-data) logic operation technique is proposed and extended to a ternary logic. A cellular array based on the ternary logic is proposed, and its application to a dynamic interconnection architecture in which optical data flow is changed by an op... View full abstract»

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  • BOLD: The Boulder Optimal Logic Design system

    Publication Year: 1989, Page(s):59 - 73 vol.1
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavior... View full abstract»

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  • An optical learning machine

    Publication Year: 1989, Page(s):432 - 439 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The authors report on what they believe to be the first demonstration of a fully operational optical learning machine. Learning in this machine takes place stochastically in a self-organizing trilayered optoelectronic neural net with plastic connectivity weights that are formed in a programmable nonvolatile spatial light modulator. The net learns by adapting its connectivity weights in accordance ... View full abstract»

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  • A top-down parsing co-processor for compilation

    Publication Year: 1989, Page(s):403 - 413 vol.1
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The architecture of a top-down parsing coprocessor is presented. This processor aims at fast compilation for programming languages in LL(1) grammar. It accepts a stream of tokens from the lexical coprocessor and produces a stream of codes representing semantic action to be taken by the CPU. The coprocessor organization has a pipeline and two register stacks. The pipeline has four stages during whi... View full abstract»

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  • Engineering design of the CONVEX C2

    Publication Year: 1989, Page(s):214 - 222 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    The CONVEX C220 and C240 supercomputers, a family of 64-bit multiprocessors tightly coupled through a shared main memory, are discussed. The structure of the C2 family and of the C1 family that preceded it is described. The product definition process and the technology selection are examined. The way in which the project was organized and staffed, the tools used, and some of the significant crisis... View full abstract»

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  • A decentralized virtual memory scheme implemented on an emulated multiprocessor

    Publication Year: 1989, Page(s):286 - 295 vol.1
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    A decentralized scheme for virtual memory management on MIMD (multiple-instruction-multiple-data) multiprocessors with shared memory has been developed. Control and data structures are kept local to the processing elements (PE), which reduces the global traffic and makes a high degree of parallelism possible. Each of the PEs in the target architecture consists of a processor and part of the shared... View full abstract»

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  • Tailoring functional units and memory in a high performance Prolog architecture

    Publication Year: 1989, Page(s):375 - 384 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    A description is given of PLUM, a Prolog machine with multiple specialized functional units and memory ports that operate in parallel using data-driven control. Unification parallelism is utilized by multiple unification units. Bookkeeping operations, such as choicepoint and environment manipulation, are executed by special functional units in parallel with unification. The performance of the syst... View full abstract»

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  • A dedicated data flow architecture for hardware compilation

    Publication Year: 1989, Page(s):181 - 190 vol.1
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedica... View full abstract»

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  • A methodology for quick turn-around of high performance DSP ASICS

    Publication Year: 1989, Page(s):23 - 28 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    An approach that has been successfully in the design of a family of high-performance digital signal processors is described. It offers the advantage of a short design cycle without sacrificing performance. The method relies on the availability of a well-characterized standard cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators... View full abstract»

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  • The design of processing elements on a multiprocessor system with a high-bandwidth, high-latency interconnection network

    Publication Year: 1989, Page(s):319 - 328 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    A description is given of the ways in which the environment of a highly parallel, high-latency interconnection network is different from that encountered in a uniprocessor system. The impact of these differences on the design of the processing elements is discussed. Methods that can be used to evaluate the impact of architectural choices on the performance of any system that uses a similar network... View full abstract»

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  • Optical modules for future signal processing systems

    Publication Year: 1989, Page(s):450 - 459 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    Analog optical modules must be part of a larger signal-processing system, and it is difficult to pass information from an optical module operating near maximum throughput to the other parts of a signal-processing system. The basis for this difficulty is often thought to be the high bandwidth and large number of channels of the optical module, but more quantitatively, optical modules do not yet hav... View full abstract»

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  • The design of an integrated environment for the automated synthesis of small computer systems

    Publication Year: 1989, Page(s):49 - 58 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The synthesis tools provided by the MICON system are described. They are M1, which utilizes a knowledge-based approach to represent and apply design knowledge, and the knowledge acquisition tool CGEN, which allows hardware designers to deposit their expertise into M1 without writing any code. The authors explore the development of an automated design environment for M1/CGEN, where computer design ... View full abstract»

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  • Interconnection and systems components for digital optics

    Publication Year: 1989, Page(s):424 - 431 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Thick holograms for the infrared based on dichromated gelatin have been studied. Since these holograms are recorded in the blue wavelength region, detuning techniques are necessary for reply with diode lasers. Beam-splitting and beam-combination devices have also been investigated. Beam splitters with low splitting ratios are needed for the implementation of symbolic substitution. Beam splitters w... View full abstract»

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  • Extending a Prolog architecture for high performance numeric computations

    Publication Year: 1989, Page(s):393 - 402 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    The Aquarius numeric processor (ANP) is an extended numeric instruction set architecture that is based on the Berkeley programmed logic machine (PLM) and supports integrated symbolic and numeric calculations. This extension expands the existing numeric data type to include 32- and 64-bit integers and single- and double-precision floating-point numbers conforming to the IEEE Standard P754. A class ... View full abstract»

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  • The Cydra 5 Departmental Supercomputer: design philosophies, decisions and trade-offs

    Publication Year: 1989, Page(s):202 - 213 vol.1
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1160 KB)

    The Cydra 5 Departmental Supercomputer is a comparatively moderately priced supercomputer intended for use by small work groups or departments of scientists and engineers. It is priced at about the same level as a high-end superminicomputer but is able to achieve about one-fourth to two-thirds the performance of a supercomputer. The discussion covers the Cydra 5 system architecture, the directed d... View full abstract»

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