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COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Date Feb. 27 1989-March 3 1989

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Displaying Results 1 - 25 of 107
  • A programmer's view of the 80960 architecture

    Publication Year: 1989 , Page(s): 4 - 9
    Cited by:  Papers (4)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (521 KB)  

    The 80960 processor integrates many architectural features normally found in RISC (reduced-instruction-set computer) processors with others found in more traditional architectures. The result is a processor providing high performance while presenting few difficulties for either applications or compiler writers. A discussion is presented of the programming model of the 960, including aspects of the... View full abstract»

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  • 80960 tool technology for embedded control

    Publication Year: 1989 , Page(s): 10 - 12
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (199 KB)  

    The author addresses the design cycle where development tools are used. Design issues are addressed in the context of deterministic debug technology and the Intel 80960 embedded microprocessor. In the coding phase of design, intrinsic component capabilities and development languages are highlighted. In the debug phase, the in-circuit emulator, source-level debugger, and software execution vehicle ... View full abstract»

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  • 80960-next generation

    Publication Year: 1989 , Page(s): 13 - 17
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (315 KB)  

    A discussion is presented of the next generation core for the 80960 family of embedded processor chips. It is shown that the next generation 960 core incorporates several features for high performance. It has wide and concurrent internal buses. It can decode and issue a sustained two instructions per clock even with loads and branches. It implements branch lookahead with branch prediction to minim... View full abstract»

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  • Motorola's 88000: integration, performance and applications

    Publication Year: 1989 , Page(s): 20 - 26
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (415 KB)  

    A discussion is presented of Motorola's microprocessor family, the 88000. Specifically, the 88100 central processing unit and the 88200 cache/memory management unit are addressed. Topics covered include the architecture, integration, performance, and applications for the chip set.<> View full abstract»

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  • An ECL implementation of the Motorola 88000

    Publication Year: 1989 , Page(s): 27 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (206 KB)  

    The high performance of the Motorola 88000 architecture, which uses ECL (emitter-coupled logic) technology, is discussed. The ECL 88000 is implemented using Motorola's MCA4 technology. This provides about 50000 ECL gates in a macro cell array structure. The ECL 88000 uses both standard and custom macros within the array. The chip is packaged in a TAB (tape automated bonding) package and dissipates... View full abstract»

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  • The binary compatibility standard

    Publication Year: 1989 , Page(s): 32 - 37
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (456 KB)  

    An overview is presented of the binary compatibility standard (BCS) for the Motorola M88000 family. This standard has defined the interface between the operating system kernel and the binary executable application. Specifically, the BCS describes the data types, common object file format, the memory map, entry into the user process, signal handling, common header file values, system calls. and req... View full abstract»

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  • New-media document (NewDoc) and dynamic navigation on the BTRON specification

    Publication Year: 1989 , Page(s): 40 - 42
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (209 KB)  

    The authors discuss how to handle multimedia documents including video data. The multimedia document is called NewDoc, which stands for new-media document. Two important features are discussed. One is the handling of the video data. The other is the navigation method, which can be applied to the video data, whose contents vary with time. This navigation method is called dynamic navigation. For edi... View full abstract»

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  • The effectiveness of TRONCHIP instructions in the TX1 system

    Publication Year: 1989 , Page(s): 43 - 47
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (338 KB)  

    A description is given of the architecture of the TX1, which is the first 32-bit microprocessor of the Toshiba TX series. The TX1 supports 92 instructions including high-level instructions for efficient use of compilers and operating systems. The effectiveness of the high-level instructions was evaluated by comparing their execution cycles on the TX1 board computer with their equivalent programs u... View full abstract»

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  • Design concept and implementation of mu ITRON specification for the H8/500 series

    Publication Year: 1989 , Page(s): 48 - 53
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (425 KB)  

    A description is given of HI8, a compact operating system (OS) based on the mu ITRON specification that has been developed for the H8/500 series of single-chip microcomputers. HI8 fully implements level three of the mu ITRON specification. Concerning two critical parameters of real-time operation, HI8 has been confirmed to have a maximum interrupt-masked time of 15.0 mu s and maximum task dispatch... View full abstract»

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  • Transputer supernodes: models for communication

    Publication Year: 1989 , Page(s): 58 - 60
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (254 KB)  

    A transputer supernode consists of multiple basic transputer nodes taken together as a unit, or of one or more of the basic nodes grouped with additional circuitry, providing for enhancements to the interprocessor communication capabilities of transputers alone. The authors explore methods for interconnecting relatively large numbers of transputers, say from 10 to 1000 or more. Consideration is gi... View full abstract»

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  • The XTM parallel desktop supercomputer: transputers play host

    Publication Year: 1989 , Page(s): 61 - 62
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (79 KB)  

    The Cogent Research XTM is a desktop parallel computer based on the INMOS T800 transputer. Designed to expand from two to several hundred processors, the XTM provides a transparent distributed computing environment both within a single workstation and among a collection of workstations. Using Linda tuple spaces as the basis for interprocess communication and synchronization, a Unix-compatible, ser... View full abstract»

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  • A new distributed real-time controller for robotics applications

    Publication Year: 1989 , Page(s): 63 - 69
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (647 KB)  

    A description is given of a dual-board real-time distributed control module based on the INMOS T414/T800 transputers. The CPU board provides fast external memory, support for the four 10-MHz serial transputer links including two fiber-optic links, and an I/O expansion connector. The board's backplane connector is pin-compatible with the INMOS ITEM development system. The plug-in I/O board provides... View full abstract»

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  • Shared memory multiprocessors: the right approach to parallel processing

    Publication Year: 1989 , Page(s): 72 - 80
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (727 KB)  

    The authors discuss the inherent bandwidth limitations of shared buses, which are assumed to set a ceiling on the performance and scalability of this architecture. They report on three years of experience with production multiprocessor systems. Advances in bus and cache technologies have greatly raised the ceiling which limits the throughput of bus-based multiprocessors. Sophisticated hierarchies ... View full abstract»

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  • An instruction set architecture for the 1990s: parallel and retargetable

    Publication Year: 1989 , Page(s): 81 - 83
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (139 KB)  

    The G ISA has proved its retargetability by being implemented on three disparate hardware platforms. The first implementation was on a platform with software address translation and floating point; later versions incorporated these features in hardware. The SPS-1 and SPS-2 have distributed memory and use message passing. The PPWB (a Sun 3 workstation with simulated parallelism) uses memory buffers... View full abstract»

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  • Dataflow principles applied to real-time multiprocessing

    Publication Year: 1989 , Page(s): 84 - 89
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (526 KB)  

    A discussion is presented of the merits of data-flow principles as applied to real-time multiprocessing. It also outlines the architecture and characteristics of a practical data-flow multiprocessor, called HyperFlo. The properties of real-time computing are discussed along with a comparison of control flow with data flow. Data flow advantages are outlined. The Hyperflow system is examined as is t... View full abstract»

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  • CFTP (Cray Fortran/ANSI Fortran '77 prefine): a tool to aid in hand-parallelizing sequential code

    Publication Year: 1989 , Page(s): 92 - 97
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (293 KB)  

    CFTP is a software tool designed to aid programmers in hand-parallelizing sequential ANSI Fortran 77 or CFT code. It assists the programmer by providing information about the code which the programmer must have in order to determine where parallel execution is safe and where it is not. CFTP collects information regarding the input code's usage of its variables. In doing so it builds a call graph, ... View full abstract»

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  • Linda: some current work

    Publication Year: 1989 , Page(s): 98 - 101
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (227 KB)  

    The authors briefly outline the Linda tuple space model and then comment on current work. This includes recent experiments involving Linda programs on a 64-node hypercube, the development of an improved version of C-Linda, and research which will culminate in a multiple tuple space system.<> View full abstract»

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  • Design and implementation of parallel programs with LGDF2

    Publication Year: 1989 , Page(s): 102 - 107
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (466 KB)  

    The authors present a method of parallel program design using large-grain data-flow constructs that approaches these problems head-on. The resultant modules can be implemented in virtually any language, and efficient, automatic scheduling of these modules is possible for both shared- and distributed-memory processors. The methods also show promise for sequential design.<> View full abstract»

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  • Introduction to redundant arrays of inexpensive disks (RAID)

    Publication Year: 1989 , Page(s): 112 - 117
    Cited by:  Papers (50)  |  Patents (133)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (574 KB)  

    The authors discuss various types of RAIDs (redundant arrays of inexpensive disks), a cost-effective option to meet the challenge of exponential growth in the processor and memory speeds. They argue that the size reduction of personal-computer (PC) disks is the key to the success of disk arrays. While large arrays of mainframe processors are possible, it is certainly easier to construct an array f... View full abstract»

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  • How reliable is a RAID?

    Publication Year: 1989 , Page(s): 118 - 123
    Cited by:  Papers (20)  |  Patents (107)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (421 KB)  

    Disk arrays offer greatly increased transfer bandwidth at low cost, but without additional data redundancy they can suffer from significantly degraded reliability. The authors examine the reliability of RAID (redundant arrays of inexpensive disks) systems and find that although extremely reliable disk arrays cannot be attained with data redundancy alone, RAID system reliability can be made better ... View full abstract»

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  • Log-structured file systems

    Publication Year: 1989 , Page(s): 124 - 129
    Cited by:  Papers (2)  |  Patents (46)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (499 KB)  

    A discussion is presented of several techniques for improving I/O performance, including caches, battery-backed-up caches, and cache logging. The authors then examine in particular detail an approach called log-structured file systems, where the file system's only representation on disk is in the form of an append-only log. Log-structured file systems potentially provide order-of-magnitude improve... View full abstract»

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  • Arm scheduling in shadowed disks

    Publication Year: 1989 , Page(s): 132 - 136
    Cited by:  Papers (62)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB)  

    The author describes a number of configurations and disk scheduling algorithms for shadow sets, and presents an analysis of seek time based on both a simulation and an analytic model. She focuses on the algorithm based on assigning a read request to the arm that is within the shortest seek distance of the target location. With this scheduling algorithm, shadowing five disks decreases the expected ... View full abstract»

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  • Some design issues of disk arrays

    Publication Year: 1989 , Page(s): 137 - 142
    Cited by:  Papers (11)  |  Patents (65)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (355 KB)  

    Some of the issues that should be considered in the design of a disk array subsystem are discussed. The objective is not to come up with a standard, or the best disk array solution, but rather to bring out some of the design options, to provide a better understanding of the tradeoffs of some of the choices, and to point out some pitfalls to avoid.<> View full abstract»

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  • Disk array systems

    Publication Year: 1989 , Page(s): 143 - 146
    Cited by:  Papers (1)  |  Patents (85)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (166 KB)  

    A description is given of the Strategy 2 Architecture, which consists of a control processor, a large data buffer, direct memory access controllers, disk drive control interfaces, a high-speed FIFO (first-in first-out) interface, and a data-flow processor for data reconstruction and parity. Strategy 2 is an intelligent controller capable of storing and retrieving data from multiple banks of four o... View full abstract»

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  • Increasing diskette capacity with Floptical technology

    Publication Year: 1989 , Page(s): 148 - 150
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (198 KB)  

    Both cost and storage capacity breakthroughs are achieved by combining optical servo with magnetic data-recording techniques. The technology, allowing increased capacity, is commercially practical due to the use of low-cost components similar to those developed for compact-disk (CD) technology combined with existing flexible-disk drive technologies and hardware. This combination in a flexible disk... View full abstract»

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